AMD Ryzen 9 7950X CPU Floorplan

Physical Layout Diagram

+-----------------------------------------------------------------------------------+
|▲                     +-----------------------------------+                       |
|                      |                                   |                       |
|                      |                                   |                       |
|                      |                                   |                       |
|                      |             I/O Die               |                       |
|                      |                                   |                       |
|                      |                                   |                       |
|                      |                                   |                       |
|                      |                                   |                       |
|                      +-----------------------------------+                       |
|                                                                                  |
|        +-----------------------------+   +-----------------------------+         |
|        |           CCD 0             |   |           CCD 1             |         |
|        |-----------------------------|   |-----------------------------|         |
|        |      C0      |      C1      |   |      C8      |      C9      |         |
|        |--------------|--------------|   |--------------|--------------|         |
|        |      C2      |      C3      |   |     C10      |     C11      |         |
|        |--------------|--------------|   |--------------|--------------|         |
|        |      C4      |      C5      |   |     C12      |     C13      |         |
|        |--------------|--------------|   |--------------|--------------|         |
|        |      C6      |      C7      |   |     C14      |     C15      |         |
|        +-----------------------------+   +-----------------------------+         |
+-----------------------------------------------------------------------------------+

CCD Layout Image

Component Descriptions

I/O Die (IOD)

• Central communications hub
• Contains:
  • Memory controller
  • PCIe lanes
  • USB controllers
  • Other I/O functionality
• Primary temperature sensor located centrally
• Reports the "CPU temperature" in monitoring software
• Manufactured on a different process than compute dies

Compute Chiplet Dies (CCDs)

• CCD 0 (Left):

  • Contains cores C0-C7 (8 cores)
  • Each core has its own temperature sensor
  • Each core has dedicated L1/L2 cache
  • Shares L3 cache (not shown in diagram)

• CCD 1 (Right):

  • Contains cores C8-C15 (8 cores)
  • Each core has its own temperature sensor
  • Identical configuration to CCD 0

Temperature Sensor Locations

I/O Die:

• Central SoC (System on Chip) temperature sensor

Each CCD:

• One sensor per core (8 per CCD, 16 total)
• Additional sensors in L3 cache regions
• The highest temperature reading from any core is reported as "Tdie" or "CPU Core temperature"

Architecture Highlights

• Total of 16 cores in an 8+8 arrangement
• Uses AMD's "chiplet" approach instead of a monolithic die
• Zen4
• Benefits:
  • Better manufacturing yields
  • More efficient thermal distribution
  • Selective core boosting
  • Easier binning of high-performing chips

Thermal Characteristics

• Heat concentrated in three distinct areas (IOD and two CCDs)
• Important for thermal paste application and cooler mounting
• Pressure needs to be appropriately distributed across all three chiplets