Have been using AXI Interconnect and SmartConnect in Vivado block designs to map multiple different peripherals to access via PCIe, without previously finding issues.
For the U200_100G_ether_simplex_tx went to add a second CMAC block.
The AXI SmartConnect assignments in the /xdma_0/M_AXI_LITE address space were:
| Master Segment Name | Slave Segment | Offset | Range |
|---|---|---|---|
| SEG_cmac_usplus_0_Reg | /cmac_usplus_0/s_axi/Reg | 0x0000 | 8K |
| SEG_axi_gpio_0_Reg | /axi_gpio_0/S_AXI/Reg | 0x2000 | 8K |
| SEG_system_management_wiz_0_Reg | /system_management_wiz_0/S_AXI_LITE/Reg | 0x4000 | 8K |