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May 17, 2022 13:36
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| module checksum( | |
| i_clk, | |
| i_da, | |
| i_data, | |
| o_da, | |
| o_data | |
| ); | |
| // Module Port Definitions | |
| input wire i_clk; | |
| input wire i_da; | |
| input wire [3:0] i_data; | |
| output reg o_da; | |
| output reg o_data; | |
| initial o_da = 0; | |
| initial o_data = 0; | |
| // Data and checksum | |
| reg [19:0] r_data; | |
| initial r_data = 20'h00; | |
| // Counter | |
| reg [4:0] r_cnt; | |
| initial r_cnt = 5'h00; | |
| // FSM States | |
| localparam s_DATA_IN = 1'b0; | |
| localparam s_SER_OUT = 1'b1; | |
| reg r_state; | |
| initial r_state = s_DATA_IN; | |
| // FSM Logic | |
| always @(posedge i_clk) | |
| case (r_state) | |
| s_DATA_IN: begin | |
| // Output data invalid | |
| o_da <= 0; | |
| // Check if we have valid data at the inputs | |
| if(i_da) begin | |
| // Read the data into the shift register | |
| r_data[15:12] <= i_data; | |
| r_data[11:0] <= r_data[15:4]; | |
| // Calculate the checksum | |
| r_data[19:16] <= r_data[19:16] + i_data; | |
| // Count how many 4-bit chunks we've read in | |
| r_cnt <= r_cnt + 1; | |
| if(r_cnt == 5'b11) begin | |
| r_cnt <= 5'b0; | |
| r_state <= s_SER_OUT; | |
| end | |
| end | |
| end | |
| s_SER_OUT: begin | |
| // Output data valid | |
| o_da <= 1; | |
| // Shift the data out | |
| o_data <= r_data[0]; | |
| r_data <= r_data[19:1]; | |
| // Count the number of bits shifted out | |
| r_cnt <= r_cnt + 1; | |
| if(r_cnt == 5'b10011) begin | |
| r_cnt <= 5'b0; | |
| r_state <= s_DATA_IN; | |
| end | |
| end | |
| endcase | |
| endmodule |
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| module testbench; | |
| reg clk = 0; | |
| always #1 clk = ~clk; | |
| reg i_da = 1; | |
| reg [3:0] i_data = 4'b0001; | |
| wire o_da; | |
| wire o_data; | |
| checksum chk0 ( | |
| .i_clk(clk), | |
| .i_da(i_da), | |
| .i_data(i_data), | |
| .o_da(o_da), | |
| .o_data(o_data) | |
| ); | |
| always @(posedge clk) begin | |
| if(o_da) | |
| $display("[%0t] o_da: %d, o_data: %d", $time, o_da, o_data); | |
| end | |
| initial #100 $finish(); | |
| endmodule |
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