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Minimal (boot pre-reqs & MTP ONLY) t8112 DT
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| // SPDX-License-Identifier: GPL-2.0+ OR MIT | |
| /* | |
| * Apple T8122 "M3" SoC | |
| * | |
| * Other names: H15G | |
| * | |
| * Copyright The Asahi Linux Contributors | |
| */ | |
| #include <dt-bindings/interrupt-controller/apple-aic.h> | |
| #include <dt-bindings/interrupt-controller/irq.h> | |
| / { | |
| compatible = "apple,t8122", "apple,arm-platform"; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| aliases { | |
| keyboard = &keyboard; | |
| }; | |
| cpus { | |
| #address-cells = <2>; | |
| #size-cells = <0>; | |
| cpu-map { | |
| cluster1 { | |
| core0 { | |
| cpu = <&cpu_p0>; | |
| }; | |
| }; | |
| }; | |
| cpu_p0: cpu@10100 { | |
| compatible = "apple,everest"; | |
| device_type = "cpu"; | |
| reg = <0x0 0x10100>; | |
| enable-method = "spin-table"; | |
| cpu-release-addr = <0 0>; /* To be filled by loader */ | |
| capacity-dmips-mhz = <1024>; | |
| next-level-cache = <&l2_cache_1>; | |
| i-cache-size = <0x30000>; | |
| d-cache-size = <0x20000>; | |
| }; | |
| l2_cache_1: l2-cache-1 { | |
| compatible = "cache"; | |
| cache-level = <2>; | |
| cache-unified; | |
| cache-size = <0x1000000>; | |
| }; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupt-parent = <&aic>; | |
| interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; | |
| interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, | |
| <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, | |
| <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, | |
| <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; | |
| }; | |
| clkref: clock-ref { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <24000000>; | |
| clock-output-names = "clkref"; | |
| }; | |
| soc { | |
| compatible = "simple-bus"; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| ranges; | |
| nonposted-mmio; | |
| /* Required to get >32-bit DMA via DARTs */ | |
| dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; | |
| fpwm1: pwm@2a1044000 { | |
| compatible = "apple,t8122-fpwm", "apple,s5l-fpwm"; | |
| reg = <0x2 0xa1044000 0x0 0x4000>; | |
| clocks = <&clkref>; | |
| interrupt-parent = <&aic>; | |
| interrupts = <AIC_IRQ 790 IRQ_TYPE_LEVEL_HIGH>; | |
| #pwm-cells = <2>; | |
| power-domains = <&ps_fpwm1>; | |
| }; | |
| aic: interrupt-controller@2d1000000 { | |
| compatible = "apple,t8122-aic", "apple,aic3"; | |
| #interrupt-cells = <3>; | |
| #address-cells = <0>; | |
| interrupt-controller; | |
| reg = <0x2 0xd1000000 0x0 0x184000>, | |
| <0x2 0xd1040000 0x0 0x4>; | |
| reg-names = "core", "event"; | |
| config-offset = <0x10000>; | |
| cap0-offset = <4>; | |
| maxnumirq-offset = <12>; | |
| power-domains = <&ps_aic>; | |
| }; | |
| pmgr: power-management@2d0700000 { | |
| compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x2 0xd0700000 0 0x80000>; | |
| /* child nodes are added in t8122-pmgr.dtsi */ | |
| }; | |
| pmgr_mini: power-management@2e4280000 { | |
| compatible = "apple,t8122-pmgr", "apple,pmgr", "syscon", "simple-mfd"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x2 0xe4280000 0 0x4000>; | |
| /* child nodes are added in t8122-pmgr.dtsi */ | |
| }; | |
| wdt: watchdog@2e42b0000 { | |
| compatible = "apple,t8122-wdt", "apple,wdt"; | |
| reg = <0x2 0xe42b0000 0x0 0x4000>; | |
| clocks = <&clkref>; | |
| interrupt-parent = <&aic>; | |
| interrupts = <AIC_IRQ 432 IRQ_TYPE_LEVEL_HIGH>; | |
| }; | |
| mtp_mbox: mbox@2fa408000 { | |
| compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; | |
| reg = <0x2 0xfa408000 0x0 0x4000>; | |
| interrupt-parent = <&aic>; | |
| interrupts = <AIC_IRQ 838 IRQ_TYPE_LEVEL_HIGH>, | |
| <AIC_IRQ 839 IRQ_TYPE_LEVEL_HIGH>, | |
| <AIC_IRQ 840 IRQ_TYPE_LEVEL_HIGH>, | |
| <AIC_IRQ 841 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "send-empty", "send-not-empty", | |
| "recv-empty", "recv-not-empty"; | |
| #mbox-cells = <0>; | |
| }; | |
| mtp_dart: iommu@2fa808000 { | |
| compatible = "apple,t8110-dart"; | |
| reg = <0x2 0xfa808000 0x0 0x4000>; | |
| interrupt-parent = <&aic>; | |
| interrupts = <AIC_IRQ 822 IRQ_TYPE_LEVEL_HIGH>; | |
| #iommu-cells = <1>; | |
| }; | |
| mtp_dockchannel: fifo@2fab14000 { | |
| compatible = "apple,t8112-dockchannel"; | |
| reg = <0x2 0xfab14000 0x0 0x4000>; | |
| interrupt-parent = <&aic>; | |
| interrupts = <AIC_IRQ 824 IRQ_TYPE_LEVEL_HIGH>; | |
| ranges; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| nonposted-mmio; | |
| mtp_hid: input@2fab30000 { | |
| compatible = "apple,t8112-dockchannel-hid"; | |
| reg = <0x2 0xfab30000 0x0 0x4000>, | |
| <0x2 0xfab34000 0x0 0x4000>, | |
| <0x2 0xfa400000 0x0 0x4000>, | |
| <0x2 0xfa050000 0x0 0x100000>; | |
| reg-names = "config", "data", "coproc-asc", "coproc-sram"; | |
| mboxes = <&mtp_mbox>; | |
| iommus = <&mtp_dart 1>; | |
| interrupt-parent = <&mtp_dockchannel>; | |
| interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, | |
| <3 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "tx", "rx"; | |
| keyboard: keyboard { | |
| /* Filled by bootloader */ | |
| hid-country-code = <0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| #include "t8122-pmgr.dtsi" |
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