redstone.hdl

A random HDL brainstorm for Minecraft redstone.

module ComparatorClock(delay_ticks) {
    default input toggle: 1
    default output out: 1
    component comp: Comparator(mode: "subtract")
    wiring {
        toggle -- comp
        comp -- Repeater(delay: delay_ticks) -- comp.side
        comp -- out
    }
}

• braces
• a module is the basic component
• modules have inputs, outputs, and parameters
• inputs and outputs are for redstone, parameters are for config
• inputs and outputs defined by their respective keyword
• inputs and outputs have a width, like in verilog. here both 1
• subcomponents use the function-call-like syntax
• wiring defines the implemenation
• -- is a redstone connection
• Repeater(delay: delay_ticks) is a repeater subcomponent, with the delay set to the delay_ticks module parameter
• module parameters passed by name
• component is basically a variable for subcomponents
• Repeater(delay: delay_ticks) -- comp.side wires a repeater to the side input of the comp (which is a Comparator)
• default allows you to wire inputs/outputs without specifying them explicitly
• here, the comparator has a default input, a side input, and a default output