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December 8, 2025 21:33
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Mangmi Air X - Running Kernel Device Tree dump (Android)
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| /dts-v1/; | |
| / { | |
| #address-cells = <0x02>; | |
| model = "Qualcomm Technologies, Inc. Panda PVT IDP"; | |
| qcom,board-id = <0x22 0x02>; | |
| #size-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp"; | |
| qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; | |
| mem-offline { | |
| offline-sizes = <0x01 0x40000000 0x00 0x40000000 0x01 0xc0000000 0x00 0x80000000 0x02 0xc0000000 0x01 0x40000000>; | |
| granule = <0x200>; | |
| compatible = "qcom,mem-offline"; | |
| }; | |
| soc { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| phandle = <0x13a>; | |
| qcom,rpm-smd { | |
| power-domains = <0x18>; | |
| rpm-channel-name = "rpm_requests"; | |
| interrupts = <0x00 0xc2 0x01>; | |
| compatible = "qcom,rpm-smd"; | |
| phandle = <0x151>; | |
| rpm-channel-type = <0x0f>; | |
| rpm-regulator-ldoa17 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x11>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l17 { | |
| regulator-max-microvolt = <0x151e40>; | |
| qcom,init-voltage = <0x119400>; | |
| regulator-min-microvolt = <0x119400>; | |
| regulator-name = "pm6125_l17"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x21>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa7 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x07>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l7 { | |
| regulator-max-microvolt = <0x13e5c0>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm6125_l7"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x15b>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa15 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x0f>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l15 { | |
| regulator-max-microvolt = "", "1Q"; | |
| qcom,init-voltage = <0x2c8e40>; | |
| regulator-min-microvolt = <0x2c8e40>; | |
| regulator-name = "pm6125_l15"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x82>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa5 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x05>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l5 { | |
| regulator-max-microvolt = <0x2ea180>; | |
| qcom,init-voltage = <0x192580>; | |
| regulator-min-microvolt = <0x192580>; | |
| regulator-name = "pm6125_l5"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x159>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa23 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x17>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l23 { | |
| regulator-max-microvolt = <0x33e140>; | |
| qcom,init-voltage = <0x30d400>; | |
| regulator-min-microvolt = <0x30d400>; | |
| regulator-name = "pm6125_l23"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x22>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa13 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x0d>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l13 { | |
| regulator-max-microvolt = <0x1dc900>; | |
| qcom,init-voltage = <0x16f300>; | |
| regulator-min-microvolt = <0x16f300>; | |
| regulator-name = "pm6125_l13"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x15f>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa3 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x00>; | |
| status = "okay"; | |
| qcom,resource-name = "rwlc"; | |
| regulator-l3 { | |
| regulator-name = "pm6125_l3"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| }; | |
| regulator-l3-level { | |
| regulator-max-microvolt = <0x200>; | |
| qcom,use-voltage-level; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm6125_l3_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| phandle = <0x2c>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa21 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x15>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l21 { | |
| regulator-max-microvolt = <0x36ee80>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x249f00>; | |
| regulator-name = "pm6125_l21"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x164>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa11 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x0b>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l11 { | |
| regulator-max-microvolt = <0x1dc900>; | |
| qcom,init-voltage = <0x1a0040>; | |
| regulator-min-microvolt = <0x1a0040>; | |
| regulator-name = "pm6125_l11"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x15e>; | |
| }; | |
| }; | |
| rpm-regulator-smpa7 { | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x07>; | |
| status = "okay"; | |
| qcom,resource-name = "smpa"; | |
| regulator-s7 { | |
| regulator-max-microvolt = <0x1fbd00>; | |
| qcom,init-voltage = <0x138800>; | |
| regulator-min-microvolt = <0x138800>; | |
| regulator-name = "pm6125_s7"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x156>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa1 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x01>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l1 { | |
| regulator-max-microvolt = <0x119400>; | |
| qcom,init-voltage = <0xe86c0>; | |
| regulator-min-microvolt = <0xe86c0>; | |
| regulator-name = "pm6125_l1"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x158>; | |
| }; | |
| }; | |
| rpm-regulator-smpa5 { | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x00>; | |
| status = "okay"; | |
| qcom,resource-name = "rwmx"; | |
| regulator-s5-floor-level { | |
| regulator-max-microvolt = <0x200>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm6125_s5_floor_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,always-send-voltage; | |
| phandle = <0x153>; | |
| qcom,use-voltage-floor-level; | |
| }; | |
| regulator-s5 { | |
| regulator-name = "pm6125_s5"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| }; | |
| regulator-s5-level-ao { | |
| regulator-max-microvolt = <0x200>; | |
| qcom,use-voltage-level; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm6125_s5_level_ao"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x01>; | |
| phandle = <0x154>; | |
| }; | |
| mx-cdev-lvl { | |
| compatible = "qcom,regulator-cooling-device"; | |
| phandle = <0x155>; | |
| regulator-cdev-supply = <0x2b>; | |
| regulator-levels = <0x100 0x00>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| regulator-s5-level { | |
| regulator-max-microvolt = <0x200>; | |
| qcom,use-voltage-level; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm6125_s5_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| phandle = <0x2b>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa18 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x12>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l18 { | |
| regulator-max-microvolt = <0x140500>; | |
| qcom,init-voltage = <0x10d880>; | |
| regulator-min-microvolt = <0x10d880>; | |
| regulator-name = "pm6125_l18"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x161>; | |
| }; | |
| }; | |
| rpm-regulator-smpa3 { | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x00>; | |
| status = "okay"; | |
| qcom,resource-name = "rwcx"; | |
| regulator-s3-floor-level { | |
| regulator-max-microvolt = <0x200>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm6125_s3_floor_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,always-send-voltage; | |
| phandle = <0x2a>; | |
| qcom,use-voltage-floor-level; | |
| }; | |
| regulator-s3-level { | |
| regulator-max-microvolt = <0x200>; | |
| qcom,use-voltage-level; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm6125_s3_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| phandle = <0x32>; | |
| }; | |
| regulator-s3 { | |
| regulator-name = "pm6125_s3"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| }; | |
| cx-cdev-lvl { | |
| compatible = "qcom,regulator-cooling-device"; | |
| phandle = <0x152>; | |
| regulator-cdev-supply = <0x2a>; | |
| regulator-levels = <0x100 0x00>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| regulator-s3-level-ao { | |
| regulator-max-microvolt = <0x200>; | |
| qcom,use-voltage-level; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm6125_s3_level_ao"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x01>; | |
| phandle = <0x5a>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa8 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x08>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l8 { | |
| regulator-max-microvolt = <0xb1bc0>; | |
| qcom,init-voltage = <0x61a80>; | |
| regulator-min-microvolt = <0x61a80>; | |
| regulator-name = "pm6125_l8"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x15c>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa16 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x10>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l16 { | |
| regulator-max-microvolt = <0x1d0d80>; | |
| qcom,init-voltage = <0x1a0040>; | |
| regulator-min-microvolt = <0x1a0040>; | |
| regulator-name = "pm6125_l16"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x23>; | |
| }; | |
| }; | |
| rpm-regulator-smpa1 { | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x00>; | |
| status = "disabled"; | |
| qcom,resource-name = "rwmx"; | |
| regulator-s1 { | |
| regulator-name = "pm6125_s1"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa6 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x06>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l6 { | |
| regulator-max-microvolt = <0xa0280>; | |
| qcom,init-voltage = <0x8ca00>; | |
| regulator-min-microvolt = <0x8ca00>; | |
| regulator-name = "pm6125_l6"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x15a>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa24 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x18>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l24 { | |
| regulator-max-microvolt = <0x36ee80>; | |
| qcom,init-voltage = <0x294280>; | |
| regulator-min-microvolt = <0x294280>; | |
| regulator-name = "pm6125_l24"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x166>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa14 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x0e>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l14 { | |
| regulator-max-microvolt = <0x1d0d80>; | |
| qcom,init-voltage = <0x1a0040>; | |
| regulator-min-microvolt = <0x1a0040>; | |
| regulator-name = "pm6125_l14"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x160>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa4 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x04>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l4 { | |
| regulator-max-microvolt = <0xf4240>; | |
| qcom,init-voltage = <0x77240>; | |
| regulator-min-microvolt = <0x77240>; | |
| regulator-name = "pm6125_l4"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x80>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa22 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x16>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l22 { | |
| regulator-max-microvolt = <0x326a40>; | |
| qcom,init-voltage = <0x2d0b40>; | |
| regulator-min-microvolt = <0x2d0b40>; | |
| regulator-name = "pm6125_l22"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x165>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa12 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x0c>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l12 { | |
| regulator-max-microvolt = <0x1e4600>; | |
| qcom,init-voltage = <0x18c7c0>; | |
| regulator-min-microvolt = <0x18c7c0>; | |
| regulator-name = "pm6125_l12"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x81>; | |
| }; | |
| }; | |
| rpm-regulator-smpa8 { | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x08>; | |
| status = "okay"; | |
| qcom,resource-name = "smpa"; | |
| regulator-s8 { | |
| regulator-max-microvolt = <0x13e5c0>; | |
| qcom,init-voltage = <0x103c40>; | |
| regulator-min-microvolt = <0x103c40>; | |
| regulator-name = "pm6125_s8"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x157>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa2 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x00>; | |
| status = "okay"; | |
| qcom,resource-name = "rwlm"; | |
| regulator-l2-level { | |
| regulator-max-microvolt = <0x200>; | |
| qcom,use-voltage-level; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm6125_l2_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| phandle = <0x2d>; | |
| }; | |
| regulator-l2 { | |
| regulator-name = "pm6125_l2"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa20 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x14>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l20 { | |
| regulator-max-microvolt = <0x326a40>; | |
| qcom,init-voltage = <0x18c7c0>; | |
| regulator-min-microvolt = <0x18c7c0>; | |
| regulator-name = "pm6125_l20"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x163>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa10 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x0a>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l10 { | |
| regulator-max-microvolt = <0x1d0d80>; | |
| qcom,init-voltage = <0x1a0040>; | |
| regulator-min-microvolt = <0x1a0040>; | |
| regulator-name = "pm6125_l10"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x15d>; | |
| }; | |
| }; | |
| rpm-regulator-smpa6 { | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x06>; | |
| status = "okay"; | |
| qcom,resource-name = "smpa"; | |
| regulator-s6 { | |
| regulator-max-microvolt = <0x163780>; | |
| qcom,init-voltage = <0x4a380>; | |
| regulator-min-microvolt = <0x4a380>; | |
| regulator-name = "pm6125_s6"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x105>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa19 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x13>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l19 { | |
| regulator-max-microvolt = <0x326a40>; | |
| qcom,init-voltage = <0x18c7c0>; | |
| regulator-min-microvolt = <0x18c7c0>; | |
| regulator-name = "pm6125_l19"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x162>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa9 { | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,regulator-hw-type = "pmic5-ldo"; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-id = <0x09>; | |
| status = "okay"; | |
| qcom,resource-name = "ldoa"; | |
| regulator-l9 { | |
| regulator-max-microvolt = <0x1e8480>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm6125_l9"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| status = "okay"; | |
| qcom,set = <0x03>; | |
| phandle = <0x20>; | |
| }; | |
| }; | |
| }; | |
| qcom,wb-display@0 { | |
| cell-index = <0x00>; | |
| label = "wb_display"; | |
| compatible = "qcom,wb-display"; | |
| status = "disabled"; | |
| phandle = <0x321>; | |
| }; | |
| tz-log@c125720 { | |
| hyplog-address-offset = <0x410>; | |
| compatible = "qcom,tz-log"; | |
| qcom,hyplog-enabled; | |
| reg = <0xc125720 0x3000>; | |
| phandle = <0x14b>; | |
| hyplog-size-offset = <0x414>; | |
| }; | |
| tpdm@8850000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-pimem"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8850000 0x1000>; | |
| phandle = <0x19d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x98>; | |
| phandle = <0xce>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@147d078 { | |
| qcom,no-status-check-on-disable; | |
| regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x147d078 0x04>; | |
| phandle = <0xec>; | |
| }; | |
| hwlock { | |
| syscon = <0x61 0x00 0x1000>; | |
| compatible = "qcom,tcsr-mutex"; | |
| phandle = <0x63>; | |
| #hwlock-cells = <0x01>; | |
| }; | |
| cti@8017000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti7"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8017000 0x1000>; | |
| phandle = <0x1d8>; | |
| }; | |
| pinctrl@400000 { | |
| wakeup-parent = <0x59>; | |
| gpio-controller; | |
| interrupts = <0x00 0xe3 0x04>; | |
| compatible = "qcom,bengal-pinctrl"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x400000 0xc00000>; | |
| phandle = <0x1f>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| sdc1_on { | |
| phandle = <0x1e1>; | |
| clk { | |
| pins = "sdc1_clk"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| rclk { | |
| pins = "sdc1_rclk"; | |
| bias-pull-down; | |
| }; | |
| data { | |
| pins = "sdc1_data"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| cmd { | |
| pins = "sdc1_cmd"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| rgbr_suspend { | |
| phandle = <0x2fb>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio37"; | |
| }; | |
| config { | |
| pins = "gpio37"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| pmx_ts_int_suspend { | |
| ts_int_suspend { | |
| phandle = <0x213>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio69"; | |
| }; | |
| config { | |
| pins = "gpio69"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| qupv3_se4_2uart_pins { | |
| phandle = <0x1ea>; | |
| qupv3_se4_2uart_sleep { | |
| phandle = <0xf2>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio12", "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio12", "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se4_2uart_active { | |
| phandle = <0xf1>; | |
| mux { | |
| function = "qup4"; | |
| pins = "gpio12", "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio12", "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| mcu_gpios { | |
| mcu_ctrl { | |
| phandle = <0x2f2>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio22", "gpio27", "gpio28", "gpio26", "gpio25"; | |
| }; | |
| config { | |
| pins = "gpio22", "gpio27", "gpio28", "gpio26", "gpio25"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| qupv3_se3_4uart_pins { | |
| phandle = <0x1eb>; | |
| qupv3_se3_cts { | |
| phandle = <0xf9>; | |
| mux { | |
| function = "qup3"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se3_rts { | |
| phandle = <0xfa>; | |
| mux { | |
| function = "qup3"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se3_default_cts { | |
| phandle = <0xf5>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se3_tx { | |
| phandle = <0xfb>; | |
| mux { | |
| function = "qup3"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se3_rx { | |
| phandle = <0xfc>; | |
| mux { | |
| function = "qup3"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se3_default_tx { | |
| phandle = <0xf7>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se3_default_rx { | |
| phandle = <0xf8>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se3_default_rts { | |
| phandle = <0xf6>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| rgbl_suspend { | |
| phandle = <0x2f8>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_csi_mux_oe_active { | |
| phandle = <0x209>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio66"; | |
| }; | |
| config { | |
| pins = "gpio66"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se2_i2c_pins { | |
| phandle = <0x1ee>; | |
| qupv3_se2_i2c_sleep { | |
| phandle = <0x107>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio6", "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio6", "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se2_i2c_active { | |
| phandle = <0x106>; | |
| mux { | |
| function = "qup2"; | |
| pins = "gpio6", "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio6", "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_csi_mux_oe_suspend { | |
| phandle = <0x20a>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio66"; | |
| }; | |
| config { | |
| pins = "gpio66"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| cam_sensor_rear1_reset_active { | |
| phandle = <0x203>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| vibra_vcc_default { | |
| phandle = <0x2f3>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio96"; | |
| }; | |
| config { | |
| pins = "gpio96"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| bias-pull-up; | |
| }; | |
| }; | |
| sdc2_off { | |
| phandle = <0x1e4>; | |
| clk { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| sd-cd { | |
| pins = "gpio88"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| data { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| cmd { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cam_sensor_rear2_reset_suspend { | |
| phandle = <0x206>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio65"; | |
| }; | |
| config { | |
| pins = "gpio65"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| qupv3_se2_spi_pins { | |
| phandle = <0x1f2>; | |
| qupv3_se2_spi_sleep { | |
| phandle = <0x111>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio6", "gpio7", "gpio71", "gpio80"; | |
| }; | |
| config { | |
| pins = "gpio6", "gpio7", "gpio71", "gpio80"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se2_spi_active { | |
| phandle = <0x110>; | |
| mux { | |
| function = "qup2"; | |
| pins = "gpio6", "gpio7", "gpio71", "gpio80"; | |
| }; | |
| config { | |
| pins = "gpio6", "gpio7", "gpio71", "gpio80"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| smb_int_default { | |
| phandle = <0x2fe>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio105"; | |
| }; | |
| config { | |
| pins = "gpio105"; | |
| bias-pull-up; | |
| input-enable; | |
| }; | |
| }; | |
| pm8008_active { | |
| phandle = <0x101>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio26"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| drive-strength = <0x02>; | |
| output-high; | |
| bias-pull-up; | |
| }; | |
| }; | |
| gpio_pwm_pins { | |
| gpio_pwm_default { | |
| phandle = <0x2f5>; | |
| mux { | |
| function = "GCC_GP1"; | |
| pins = "gpio86"; | |
| }; | |
| config { | |
| pins = "gpio86"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk1_suspend { | |
| phandle = <0x1fc>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_rear0_reset_suspend { | |
| phandle = <0x202>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| pmx_ts_int_bias_pullup { | |
| ts_int_bias_pullup { | |
| phandle = <0x326>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio69"; | |
| }; | |
| config { | |
| pins = "gpio69"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| wcd937x_reset_active { | |
| phandle = <0x1e8>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio92"; | |
| }; | |
| config { | |
| pins = "gpio92"; | |
| drive-strength = <0x10>; | |
| output-high; | |
| }; | |
| }; | |
| pmx_ts_reset_suspend { | |
| ts_reset_suspend { | |
| phandle = <0x215>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio68"; | |
| }; | |
| config { | |
| pins = "gpio68"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| qupv3_se0_2uart_pins { | |
| phandle = <0x1f0>; | |
| qupv3_se0_2uart_sleep { | |
| phandle = <0x10d>; | |
| mux { | |
| function = "qup0"; | |
| pins = "gpio2", "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio2", "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se0_2uart_active { | |
| phandle = <0x10c>; | |
| mux { | |
| function = "qup0"; | |
| pins = "gpio2", "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio2", "gpio3"; | |
| drive-strength = <0x06>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| cci1_suspend { | |
| phandle = <0x1f7>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio30", "gpio29"; | |
| }; | |
| config { | |
| pins = "gpio30", "gpio29"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_mclk3_suspend { | |
| phandle = <0x200>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio28"; | |
| }; | |
| config { | |
| pins = "gpio28"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| rgbl_irq { | |
| phandle = <0x2f7>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| pmx_ts_release { | |
| ts_release { | |
| phandle = <0x216>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio69", "gpio68"; | |
| }; | |
| config { | |
| pins = "gpio69", "gpio68"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear2_reset_active { | |
| phandle = <0x205>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio65"; | |
| }; | |
| config { | |
| pins = "gpio65"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| tb_trig1_on { | |
| phandle = <0x1e5>; | |
| mux { | |
| function = "SDC1_TB"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| input-enable; | |
| }; | |
| }; | |
| cam_sensor_mclk0_active { | |
| phandle = <0x1f9>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_csi_mux_sel_active { | |
| phandle = <0x20b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio67"; | |
| }; | |
| config { | |
| pins = "gpio67"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_front0_reset_suspend { | |
| phandle = <0x208>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio24"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| pmx_sde_te { | |
| sde_te_suspend { | |
| phandle = <0x211>; | |
| mux { | |
| function = "mdp_vsync"; | |
| pins = "gpio81"; | |
| }; | |
| config { | |
| pins = "gpio81"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| sde_te_active { | |
| phandle = <0x210>; | |
| mux { | |
| function = "mdp_vsync"; | |
| pins = "gpio81"; | |
| }; | |
| config { | |
| pins = "gpio81"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| rgbl_activate { | |
| phandle = <0x2f6>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pmx_ts_int_bias_disable { | |
| ts_int_bias_disable { | |
| phandle = <0x318>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio69"; | |
| }; | |
| config { | |
| pins = "gpio69"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk1_active { | |
| phandle = <0x1fb>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| pm8008_interrupt { | |
| phandle = <0x102>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio25"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| bias-disable; | |
| input-enable; | |
| }; | |
| }; | |
| cam_sensor_mclk2_active { | |
| phandle = <0x1fd>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio27"; | |
| }; | |
| config { | |
| pins = "gpio27"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_mclk3_active { | |
| phandle = <0x1ff>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio28"; | |
| }; | |
| config { | |
| pins = "gpio28"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se0_i2c_pins { | |
| phandle = <0x1ec>; | |
| qupv3_se0_i2c_sleep { | |
| phandle = <0xfe>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio0", "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio0", "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se0_i2c_active { | |
| phandle = <0xfd>; | |
| mux { | |
| function = "qup0"; | |
| pins = "gpio0", "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio0", "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sdc2_on { | |
| phandle = <0x1e3>; | |
| clk { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| sd-cd { | |
| pins = "gpio88"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| data { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| cmd { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| wcd937x_reset_sleep { | |
| phandle = <0x1e9>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio92"; | |
| }; | |
| config { | |
| pins = "gpio92"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| pmx_ts_int_active { | |
| ts_int_active { | |
| phandle = <0x212>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio69"; | |
| }; | |
| config { | |
| pins = "gpio69"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk0_suspend { | |
| phandle = <0x1fa>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_rear1_reset_suspend { | |
| phandle = <0x204>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| rgbr_activate { | |
| phandle = <0x2f9>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio37"; | |
| }; | |
| config { | |
| pins = "gpio37"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se5_i2c_pins { | |
| phandle = <0x1f4>; | |
| qupv3_se5_i2c_sleep { | |
| phandle = <0x109>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio14", "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio14", "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se5_i2c_active { | |
| phandle = <0x108>; | |
| mux { | |
| function = "qup5"; | |
| pins = "gpio14", "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio14", "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se0_spi_pins { | |
| phandle = <0x1ef>; | |
| qupv3_se0_spi_sleep { | |
| phandle = <0x10b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se0_spi_active { | |
| phandle = <0x10a>; | |
| mux { | |
| function = "qup0"; | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_csi_mux_sel_suspend { | |
| phandle = <0x20c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio67"; | |
| }; | |
| config { | |
| pins = "gpio67"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| pmx_ts_int_bias_pulldown { | |
| ts_int_bias_pulldown { | |
| phandle = <0x31a>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio69"; | |
| }; | |
| config { | |
| pins = "gpio69"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_sde { | |
| phandle = <0x325>; | |
| sde_dsi_suspend { | |
| phandle = <0x311>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio97"; | |
| }; | |
| config { | |
| pins = "gpio97"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sde_dsi_active { | |
| phandle = <0x310>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio97"; | |
| }; | |
| config { | |
| pins = "gpio97"; | |
| drive-strength = <0x08>; | |
| bias-disable = <0x00>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| mcu_key { | |
| mcu_key_default { | |
| phandle = <0x2f1>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio18", "gpio24", "gpio34", "gpio36"; | |
| }; | |
| config { | |
| pins = "gpio18", "gpio24", "gpio34", "gpio36"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear0_reset_active { | |
| phandle = <0x201>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cci0_suspend { | |
| phandle = <0x1f5>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio23", "gpio22"; | |
| }; | |
| config { | |
| pins = "gpio23", "gpio22"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se5_spi_pins { | |
| phandle = <0x1f3>; | |
| qupv3_se5_spi_sleep { | |
| phandle = <0x113>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio14", "gpio15", "gpio16", "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio14", "gpio15", "gpio16", "gpio17"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se5_spi_active { | |
| phandle = <0x112>; | |
| mux { | |
| function = "qup5"; | |
| pins = "gpio14", "gpio15", "gpio16", "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio14", "gpio15", "gpio16", "gpio17"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_front0_reset_active { | |
| phandle = <0x207>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio24"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_mclk2_suspend { | |
| phandle = <0x1fe>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio27"; | |
| }; | |
| config { | |
| pins = "gpio27"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cci0_active { | |
| phandle = <0x1f6>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio23", "gpio22"; | |
| }; | |
| config { | |
| pins = "gpio23", "gpio22"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se1_i2c_pins { | |
| phandle = <0x1ed>; | |
| qupv3_se1_i2c_active { | |
| phandle = <0xff>; | |
| mux { | |
| function = "qup1"; | |
| pins = "gpio4", "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se1_i2c_sleep { | |
| phandle = <0x100>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio4", "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sdc1_off { | |
| phandle = <0x1e2>; | |
| clk { | |
| pins = "sdc1_clk"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| rclk { | |
| pins = "sdc1_rclk"; | |
| bias-pull-down; | |
| }; | |
| data { | |
| pins = "sdc1_data"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| cmd { | |
| pins = "sdc1_cmd"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pmx_ts_reset_active { | |
| ts_reset_active { | |
| phandle = <0x214>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio68"; | |
| }; | |
| config { | |
| pins = "gpio68"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| cci1_active { | |
| phandle = <0x1f8>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio30", "gpio29"; | |
| }; | |
| config { | |
| pins = "gpio30", "gpio29"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| spkr_1_sd_n { | |
| spkr_1_sd_n_active { | |
| phandle = <0x1e7>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio106"; | |
| }; | |
| config { | |
| pins = "gpio106"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| spkr_1_sd_n_sleep { | |
| phandle = <0x1e6>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio106"; | |
| }; | |
| config { | |
| pins = "gpio106"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se1_spi_pins { | |
| phandle = <0x1f1>; | |
| qupv3_se1_spi_sleep { | |
| phandle = <0x10f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio4", "gpio5", "gpio69", "gpio70"; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5", "gpio69", "gpio70"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se1_spi_active { | |
| phandle = <0x10e>; | |
| mux { | |
| function = "qup1"; | |
| pins = "gpio4", "gpio5", "gpio69", "gpio70"; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5", "gpio69", "gpio70"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| rgbr_irq { | |
| phandle = <0x2fa>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio30"; | |
| }; | |
| config { | |
| pins = "gpio30"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| timer@f120000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv7-timer-mem"; | |
| ranges; | |
| reg = <0xf120000 0x1000>; | |
| frame@f128000 { | |
| interrupts = <0x00 0x0e 0x04>; | |
| frame-number = <0x06>; | |
| status = "disabled"; | |
| reg = <0xf128000 0x1000>; | |
| }; | |
| frame@f125000 { | |
| interrupts = <0x00 0x0b 0x04>; | |
| frame-number = <0x03>; | |
| status = "disabled"; | |
| reg = <0xf125000 0x1000>; | |
| }; | |
| frame@f127000 { | |
| interrupts = <0x00 0x0d 0x04>; | |
| frame-number = <0x05>; | |
| status = "disabled"; | |
| reg = <0xf127000 0x1000>; | |
| }; | |
| frame@f124000 { | |
| interrupts = <0x00 0x0a 0x04>; | |
| frame-number = <0x02>; | |
| status = "disabled"; | |
| reg = <0xf124000 0x1000>; | |
| }; | |
| frame@f121000 { | |
| interrupts = <0x00 0x08 0x04 0x00 0x07 0x04>; | |
| frame-number = <0x00>; | |
| reg = <0xf121000 0x1000 0xf122000 0x1000>; | |
| }; | |
| frame@f126000 { | |
| interrupts = <0x00 0x0c 0x04>; | |
| frame-number = <0x04>; | |
| status = "disabled"; | |
| reg = <0xf126000 0x1000>; | |
| }; | |
| frame@f123000 { | |
| interrupts = <0x00 0x09 0x04>; | |
| frame-number = <0x01>; | |
| status = "disabled"; | |
| reg = <0xf123000 0x1000>; | |
| }; | |
| }; | |
| mailbox@0f111000 { | |
| #mbox-cells = <0x01>; | |
| compatible = "qcom,bengal-apcs-hmss-global"; | |
| reg = <0xf111000 0x1000>; | |
| phandle = <0x31>; | |
| }; | |
| cti@8014000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti4"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8014000 0x1000>; | |
| phandle = <0x1d5>; | |
| }; | |
| tpdm@89d0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-qm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x89d0000 0x1000>; | |
| phandle = <0x19b>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x96>; | |
| phandle = <0xcc>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| rpm-sleep-stats@4690000 { | |
| compatible = "qcom,rpm-sleep-stats"; | |
| reg = <0x4690000 0x400>; | |
| }; | |
| qusb@1613000 { | |
| qcom,vdd-voltage-level = <0x00 0xe1d48 0xecd10>; | |
| clock-names = "ref_clk_src", "cfg_ahb_clk"; | |
| reg-names = "qusb_phy_base", "tcsr_clamp_dig_n_1p8", "tune2_efuse_addr", "eud_enable_reg"; | |
| qcom,tune2-efuse-num-bits = <0x04>; | |
| qcom,qusb-phy-init-seq = <0xf8 0x80 0xb3 0x84 0x81 0x88 0xc0 0x8c 0x30 0x08 0x79 0x0c 0x21 0x10 0x14 0x9c 0x80 0x04 0x9f 0x1c 0x00 0x18>; | |
| qcom,major-rev = <0x01>; | |
| phy_type = "utmi"; | |
| resets = <0x1d 0x00>; | |
| qcom,phy-clk-scheme = "cmos"; | |
| clocks = <0x1c 0x00 0x1d 0x95>; | |
| qcom,tune2-efuse-bit-pos = <0x19>; | |
| vdd-supply = <0x80>; | |
| compatible = "qcom,qusb2phy"; | |
| reg = <0x1613000 0x180 0x3cb250 0x04 0x1b40258 0x04 0x1612000 0x04>; | |
| phandle = <0x7e>; | |
| reset-names = "phy_reset"; | |
| vdda33-supply = <0x82>; | |
| vdda18-supply = <0x81>; | |
| }; | |
| msm_cdc_pinctrl@106 { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x1e7>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x1e6>; | |
| status = "disabled"; | |
| phandle = <0x334>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| etm@9340000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| cpu = <0x0e>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm3"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9340000 0x1000>; | |
| phandle = <0x1a4>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9f>; | |
| phandle = <0xab>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,qupv3_0_geni_se@4ac0000 { | |
| iommus = <0x29 0xe3 0x00>; | |
| #address-cells = <0x01>; | |
| clock-names = "m-ahb", "s-ahb"; | |
| clocks = <0x1d 0x68 0x1d 0x69>; | |
| #size-cells = <0x01>; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| compatible = "qcom,geni-se-qup"; | |
| ranges; | |
| status = "ok"; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| reg = <0x4ac0000 0x2000>; | |
| phandle = <0xf3>; | |
| qcom,iommu-dma = "fastmap"; | |
| i2c@4a80000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0xfd>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| interrupts = <0x00 0x147 0x04>; | |
| clocks = <0x1d 0x5c>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0xf3>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0xfe>; | |
| status = "disabled"; | |
| reg = <0x4a80000 0x4000>; | |
| phandle = <0x219>; | |
| dmas = <0xf4 0x00 0x00 0x03 0x40 0x00 0xf4 0x01 0x00 0x03 0x40 0x00>; | |
| }; | |
| spi@4a94000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x112>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x14c 0x04>; | |
| clocks = <0x1d 0x66>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0xf3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x113>; | |
| status = "disabled"; | |
| reg = <0x4a94000 0x4000>; | |
| phandle = <0x22d>; | |
| dmas = <0xf4 0x00 0x05 0x01 0x40 0x00 0xf4 0x01 0x05 0x01 0x40 0x00>; | |
| }; | |
| qcom,qup_uart@4a8c000 { | |
| pinctrl-names = "default", "active", "sleep", "shutdown"; | |
| pinctrl-2 = <0xf9 0xfa 0xfb 0xf8>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0xf5 0xf6 0xf7 0xf8>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| reg-names = "se_phys"; | |
| clocks = <0x1d 0x62>; | |
| qcom,wrapper-core = <0xf3>; | |
| dma-names = "tx", "rx"; | |
| interrupts-extended = <0x01 0x00 0x14a 0x04 0x1f 0x0b 0x04>; | |
| pinctrl-3 = <0xf5 0xf6 0xf7 0xf8>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-1 = <0xf9 0xfa 0xfb 0xfc>; | |
| status = "ok"; | |
| reg = <0x4a8c000 0x4000>; | |
| phandle = <0x218>; | |
| dmas = <0xf4 0x00 0x01 0x02 0x40 0x00 0xf4 0x01 0x01 0x02 0x40 0x00>; | |
| qcom,wakeup-byte = <0xfd>; | |
| }; | |
| spi@4a80000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x10a>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x147 0x04>; | |
| clocks = <0x1d 0x5c>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0xf3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x10b>; | |
| status = "disabled"; | |
| reg = <0x4a80000 0x4000>; | |
| phandle = <0x229>; | |
| dmas = <0xf4 0x00 0x00 0x01 0x40 0x00 0xf4 0x01 0x00 0x01 0x40 0x00>; | |
| }; | |
| i2c@4a88000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x106>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| interrupts = <0x00 0x149 0x04>; | |
| clocks = <0x1d 0x60>; | |
| #size-cells = <0x00>; | |
| qcom,i2c-touch-active = "synaptics,tcm-i2c"; | |
| qcom,wrapper-core = <0xf3>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x107>; | |
| status = "disabled"; | |
| reg = <0x4a88000 0x4000>; | |
| phandle = <0x227>; | |
| dmas = <0xf4 0x00 0x02 0x03 0x40 0x00 0xf4 0x01 0x02 0x03 0x40 0x00>; | |
| novatek@62 { | |
| pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; | |
| pinctrl-2 = <0x216>; | |
| novatek,reset-gpio = <0x1f 0x47 0x00>; | |
| pinctrl-0 = <0x212 0x214>; | |
| interrupts = <0x50 0x2008>; | |
| novatek,irq-gpio = <0x1f 0x50 0x2008>; | |
| interrupt-parent = <0x1f>; | |
| pinctrl-1 = <0x213 0x215>; | |
| status = "disabled"; | |
| reg = <0x62>; | |
| }; | |
| focaltech@38 { | |
| focaltech,reset-gpio = <0x1f 0x47 0x00>; | |
| pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; | |
| pinctrl-2 = <0x216>; | |
| pinctrl-0 = <0x212 0x214>; | |
| focaltech,max-touch-number = <0x05>; | |
| interrupts = <0x50 0x2008>; | |
| interrupt-parent = <0x1f>; | |
| compatible = "focaltech,fts_ts"; | |
| focaltech,display-coords = <0x00 0x00 0x438 0x924>; | |
| pinctrl-1 = <0x213 0x215>; | |
| status = "disabled"; | |
| focaltech,irq-gpio = <0x1f 0x50 0x2008>; | |
| reg = <0x38>; | |
| panel = <0x314 0x315>; | |
| }; | |
| synaptics_tcm@20 { | |
| pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; | |
| pinctrl-2 = <0x216>; | |
| synaptics,extend_report; | |
| pinctrl-0 = <0x212 0x214>; | |
| interrupts = <0x50 0x2008>; | |
| synaptics,ubl-i2c-addr = <0x20>; | |
| synaptics,power-delay-ms = <0xc8>; | |
| synaptics,irq-gpio = <0x1f 0x50 0x2008>; | |
| interrupt-parent = <0x1f>; | |
| synaptics,reset-on-state = <0x00>; | |
| compatible = "synaptics,tcm-i2c"; | |
| synaptics,firmware-name = "synaptics_firmware_k.img"; | |
| pinctrl-1 = <0x213 0x215>; | |
| status = "disabled"; | |
| synaptics,reset-gpio = <0x1f 0x47 0x00>; | |
| synaptics,irq-on-state = <0x00>; | |
| reg = <0x20>; | |
| panel = <0x316 0x317>; | |
| synaptics,reset-active-ms = <0x14>; | |
| synaptics,reset-delay-ms = <0xc8>; | |
| }; | |
| }; | |
| qcom,qup_uart@4a80000 { | |
| pinctrl-names = "default", "sleep"; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x10c>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x147 0x04>; | |
| clocks = <0x1d 0x5c>; | |
| uart_keyboard_enable; | |
| qcom,wrapper-core = <0xf3>; | |
| dma-names = "tx", "rx"; | |
| qcom,auto-suspend-disable; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-1 = <0x10d>; | |
| status = "ok"; | |
| reg = <0x4a80000 0x4000>; | |
| phandle = <0x22a>; | |
| dmas = <0xf4 0x00 0x00 0x02 0x40 0x00 0xf4 0x01 0x00 0x02 0x40 0x00>; | |
| }; | |
| spi@4a88000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x110>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x149 0x04>; | |
| clocks = <0x1d 0x60>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0xf3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x111>; | |
| status = "ok"; | |
| reg = <0x4a88000 0x4000>; | |
| phandle = <0x22c>; | |
| dmas = <0xf4 0x00 0x02 0x01 0x40 0x00 0xf4 0x01 0x02 0x01 0x40 0x00>; | |
| himax_ts@0 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x318>; | |
| interrupts = <0x19 0x2008>; | |
| spi-max-frequency = <0x989680>; | |
| interrupt-parent = <0x1f>; | |
| himax,panel-coords = <0x00 0x438 0x00 0x780>; | |
| compatible = "himax,hxcommon"; | |
| status = "ok"; | |
| himax,rst-gpio = <0x1f 0x44 0x00>; | |
| reg = <0x00>; | |
| report_type = <0x01>; | |
| panel = <0x312>; | |
| himax,display-coords = <0x00 0x438 0x00 0x780>; | |
| himax,irq-gpio = <0x1f 0x45 0x2008>; | |
| }; | |
| jadard_ts@0 { | |
| pinctrl-names = "pmx_ts_active", "pmx_ts_release"; | |
| pinctrl-0 = <0x318>; | |
| jadard,rst-gpio = <0x1f 0x44 0x00>; | |
| jadard,int-is-edge = <0x01>; | |
| interrupts = <0x45 0x2008>; | |
| spi-max-frequency = <0x5b8d80>; | |
| interrupt-parent = <0x1f>; | |
| jadard,panel-coords = <0x00 0x438 0x00 0x780>; | |
| jadard,irq-gpio = <0x1f 0x45 0x2008>; | |
| jadard,panel-sense-nums = <0x12 0x1e>; | |
| compatible = "jadard,jdcommon"; | |
| pinctrl-1 = <0x31a>; | |
| status = "disabled"; | |
| reg = <0x00>; | |
| jadard,panel-max-points = <0x05>; | |
| panel = <0x319>; | |
| }; | |
| }; | |
| i2c@4a84000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0xff>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| interrupts = <0x00 0x148 0x04>; | |
| clocks = <0x1d 0x5e>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0xf3>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x100>; | |
| status = "okay"; | |
| reg = <0x4a84000 0x4000>; | |
| phandle = <0x21a>; | |
| dmas = <0xf4 0x00 0x01 0x03 0x40 0x00 0xf4 0x01 0x01 0x03 0x40 0x00>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| aw882xx_smartpa@34 { | |
| irq-gpio = <0x1f 0x6a 0x2008>; | |
| aw-rx-port-id = <0x1006>; | |
| aw-tx-topo-id = <0x1000ff00>; | |
| dc-flag = <0x00>; | |
| aw-re-min = <0xfa0>; | |
| aw-re-max = <0x7530>; | |
| compatible = "awinic,aw882xx_smartpa"; | |
| sound-channel = <0x00>; | |
| aw-tx-port-id = <0x1007>; | |
| status = "okay"; | |
| reg = <0x34>; | |
| aw-rx-topo-id = <0x1000ff01>; | |
| }; | |
| wsa881x-i2c-codec@e { | |
| clock-names = "wsa_mclk"; | |
| clocks = <0x333 0x00>; | |
| compatible = "qcom,wsa881x-i2c-codec"; | |
| status = "disabled"; | |
| reg = <0x0e>; | |
| phandle = <0x33d>; | |
| qcom,wsa-analog-clk-gpio = <0x2dc>; | |
| qcom,wsa-analog-reset-gpio = <0x334>; | |
| qcom,wsa-prefix = "SpkrMono"; | |
| }; | |
| codec@18 { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| power_3v3-gpio = <0x1f 0x42 0x00>; | |
| irq-gpio = <0x1f 0x41 0x00>; | |
| pinctrl-0 = <0x275>; | |
| everest,jack-detect-inverted; | |
| compatible = "everest,es8326"; | |
| pinctrl-1 = <0x274>; | |
| status = "ok"; | |
| reg = <0x18>; | |
| phandle = <0x330>; | |
| }; | |
| wsa881x-i2c-codec@44 { | |
| compatible = "qcom,wsa881x-i2c-codec"; | |
| status = "disabled"; | |
| reg = <0x44>; | |
| phandle = <0x33e>; | |
| }; | |
| qcom,smb1355@8 { | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0xd1 0x00 0x08>; | |
| interrupt_names = "smb1355_0"; | |
| #size-cells = <0x00>; | |
| interrupt-parent = <0x177>; | |
| compatible = "qcom,i2c-pmic"; | |
| #interrupt-cells = <0x03>; | |
| status = "disabled"; | |
| reg = <0x08>; | |
| qcom,periph-map = <0x10 0x12 0x13 0x16>; | |
| phandle = <0x2e9>; | |
| interrupt-controller; | |
| qcom,smb1355-charger@1000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| interrupt-parent = <0x2e9>; | |
| compatible = "qcom,smb1355"; | |
| status = "disabled"; | |
| reg = <0x1000>; | |
| phandle = <0x2fd>; | |
| qcom,chgr@1000 { | |
| interrupts = <0x10 0x01 0x01>; | |
| interrupt-names = "chg-state-change"; | |
| reg = <0x1000>; | |
| }; | |
| qcom,chgr-misc@1600 { | |
| interrupts = <0x16 0x01 0x01 0x16 0x06 0x01>; | |
| interrupt-names = "wdog-bark", "temperature-change"; | |
| reg = <0x1600>; | |
| }; | |
| }; | |
| }; | |
| qcom,pm8008@9 { | |
| pinctrl-names = "default"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x103>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-pmic"; | |
| reg = <0x09>; | |
| phandle = <0x21e>; | |
| qcom,pm8008-regulator { | |
| qcom,enable-ocp-broadcast; | |
| compatible = "qcom,pm8008-regulator"; | |
| pm8008_en-supply = <0x104>; | |
| phandle = <0x21f>; | |
| vdd_l1_l2-supply = <0x105>; | |
| qcom,pm8008-l4@4300 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,min-dropout-voltage = <0x30d40>; | |
| qcom,hpm-min-load = <0x00>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8008_l4"; | |
| reg = <0x4300>; | |
| phandle = <0x223>; | |
| }; | |
| qcom,pm8008-l7@4400 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,min-dropout-voltage = <0x493e0>; | |
| qcom,hpm-min-load = <0x00>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8008_l7"; | |
| reg = <0x4600>; | |
| phandle = <0x226>; | |
| }; | |
| qcom,pm8008-l1@4000 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,min-dropout-voltage = <0x186a0>; | |
| qcom,hpm-min-load = <0x00>; | |
| regulator-min-microvolt = <0x80e80>; | |
| regulator-name = "pm8008_l1"; | |
| reg = <0x4000>; | |
| phandle = <0x220>; | |
| }; | |
| qcom,pm8008-l6@4400 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,min-dropout-voltage = <0x493e0>; | |
| qcom,hpm-min-load = <0x00>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8008_l6"; | |
| reg = <0x4500>; | |
| phandle = <0x225>; | |
| }; | |
| qcom,pm8008-l3@4200 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,min-dropout-voltage = <0x30d40>; | |
| qcom,hpm-min-load = <0x00>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8008_l3"; | |
| reg = <0x4200>; | |
| phandle = <0x222>; | |
| }; | |
| qcom,pm8008-l5@4400 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,min-dropout-voltage = <0x493e0>; | |
| qcom,hpm-min-load = <0x00>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8008_l5"; | |
| reg = <0x4400>; | |
| phandle = <0x224>; | |
| }; | |
| qcom,pm8008-l2@4100 { | |
| regulator-max-microvolt = <0x101d00>; | |
| qcom,min-dropout-voltage = <0x186a0>; | |
| qcom,hpm-min-load = <0x00>; | |
| regulator-min-microvolt = <0x80e80>; | |
| regulator-name = "pm8008_l2"; | |
| reg = <0x4100>; | |
| phandle = <0x221>; | |
| }; | |
| }; | |
| }; | |
| aw882xx_smartpa@35 { | |
| irq-gpio = <0x1f 0x6b 0x2008>; | |
| aw-rx-port-id = <0x1006>; | |
| aw-tx-topo-id = <0x1000ff00>; | |
| dc-flag = <0x00>; | |
| aw-re-min = <0xfa0>; | |
| aw-re-max = <0x7530>; | |
| compatible = "awinic,aw882xx_smartpa"; | |
| sound-channel = <0x01>; | |
| aw-tx-port-id = <0x1007>; | |
| status = "okay"; | |
| reg = <0x35>; | |
| aw-rx-topo-id = <0x1000ff01>; | |
| }; | |
| sgm3804@3e { | |
| compatible = "sgmicro,sgm3804"; | |
| reg = <0x3e>; | |
| }; | |
| qcom,pm8008@8 { | |
| pinctrl-names = "default"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x101 0x102>; | |
| interrupts = <0x19 0x01>; | |
| #size-cells = <0x00>; | |
| interrupt-parent = <0x1f>; | |
| compatible = "qcom,i2c-pmic"; | |
| status = "disabled"; | |
| interrupt-names = "pm8008"; | |
| reg = <0x08>; | |
| qcom,periph-map = <0x09 0x24 0xc0 0xc1>; | |
| phandle = <0x21b>; | |
| qcom,pm8008-chip@900 { | |
| compatible = "qcom,pm8008-chip"; | |
| reg = <0x900>; | |
| phandle = <0x21c>; | |
| qcom,pm8008-chip-en { | |
| regulator-name = "pm8008-chip-en"; | |
| phandle = <0x104>; | |
| }; | |
| }; | |
| pinctrl@c000 { | |
| gpio-controller; | |
| compatible = "qcom,pm8008-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0xc000>; | |
| phandle = <0x21d>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| pm8008_gpio1_active { | |
| input-disable; | |
| function = "func1"; | |
| pins = "gpio1"; | |
| bias-disable; | |
| phandle = <0x103>; | |
| output-enable; | |
| power-source = <0x01>; | |
| }; | |
| }; | |
| }; | |
| qcom,smb1355@c { | |
| #address-cells = <0x01>; | |
| interrupts = <0x02 0xc5 0x00 0x08>; | |
| interrupt_names = "smb1355"; | |
| #size-cells = <0x00>; | |
| interrupt-parent = <0x177>; | |
| compatible = "qcom,i2c-pmic"; | |
| #interrupt-cells = <0x03>; | |
| status = "disabled"; | |
| reg = <0x0c>; | |
| qcom,periph-map = <0x10 0x12 0x13 0x16>; | |
| phandle = <0x2e8>; | |
| interrupt-controller; | |
| qcom,smb1355-charger@1000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| interrupt-parent = <0x2e8>; | |
| compatible = "qcom,smb1355"; | |
| status = "disabled"; | |
| reg = <0x1000>; | |
| phandle = <0x2fc>; | |
| qcom,chgr@1000 { | |
| interrupts = <0x10 0x01 0x01>; | |
| interrupt-names = "chg-state-change"; | |
| reg = <0x1000>; | |
| }; | |
| qcom,chgr-misc@1600 { | |
| interrupts = <0x16 0x01 0x01 0x16 0x06 0x01>; | |
| interrupt-names = "wdog-bark", "temperature-change"; | |
| reg = <0x1600>; | |
| }; | |
| }; | |
| }; | |
| cw221X@64 { | |
| compatible = "cellwise,cw221X"; | |
| status = "ok"; | |
| cw,batt-profile = <0x5a000000 0x00 0xadbdb3ba 0xa6a2d1b3 0x9effe5b7 0x8b75665e 0x5c5c5ca8 0x7cdc03cf 0xc8cfd0d1 0xcecdcacc 0xc7cac1a5 0x958a8177 0x6b687d90 0x8e848a63 0x2000ab10 0xb04d00 0x641f 0xd3370000 0x00 0x18>; | |
| reg = <0x64>; | |
| phandle = <0x301>; | |
| }; | |
| }; | |
| qcom,qup_uart@4a90000 { | |
| pinctrl-names = "default", "sleep"; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0xf1>; | |
| clock-names = "se"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x14b 0x04>; | |
| clocks = <0x1d 0x64>; | |
| qcom,wrapper-core = <0xf3>; | |
| compatible = "qcom,geni-debug-uart"; | |
| pinctrl-1 = <0xf2>; | |
| status = "ok"; | |
| reg = <0x4a90000 0x4000>; | |
| phandle = <0x217>; | |
| }; | |
| i2c@4a94000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x108>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| interrupts = <0x00 0x14c 0x04>; | |
| clocks = <0x1d 0x66>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0xf3>; | |
| clock-frequency = <0x61a80>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x109>; | |
| status = "okay"; | |
| reg = <0x4a94000 0x4000>; | |
| phandle = <0x228>; | |
| dmas = <0xf4 0x00 0x05 0x03 0x40 0x00 0xf4 0x01 0x05 0x03 0x40 0x00>; | |
| sgm41600A@6E { | |
| sgm,sgm41600A,ac-ovp-threshold = <0x0c>; | |
| sgm,sgm41600A,vdrop-ovp-disable; | |
| interrupts = <0x53 0x00>; | |
| sgm,sgm41600A,bat-ocp-threshold = <0x1b58>; | |
| interrupt-parent = <0x1f>; | |
| sgm,sgm41600A,bus-ocp-threshold = <0xdac>; | |
| compatible = "sgm,sgm41600A-slave"; | |
| sgm,irq-gpio = <0x1f 0x53 0x00>; | |
| status = "disabled"; | |
| sgm,sgm41600A,bat-ovp-threshold = <0x432380>; | |
| reg = <0x6e>; | |
| phandle = <0x300>; | |
| sgm,sgm41600A,bus-ovp-threshold = <0xaf79e0>; | |
| sgm,sgm41600A,bat-ocp-disable; | |
| }; | |
| sgm41511@1a { | |
| jeita_temp_t3_to_t4_cc_current = <0xf4240>; | |
| temp_t3_thres_minus_x_degree = <0x2d>; | |
| temp_t2_thres = <0x14>; | |
| jeita_temp_t0_to_t1_cv = <0x00>; | |
| jeita_temp_below_t0_cc_current = <0x00>; | |
| jeita_temp_t2_to_t3_cc_current = <0x1312d0>; | |
| jeita_temp_above_t4_cv = <0x00>; | |
| temp_t2_thres_plus_x_degree = <0x0f>; | |
| jeita_temp_t1_to_t2_cc_current = <0xf4240>; | |
| usb-role-switch; | |
| jeita_temp_above_t4_cc_current = <0x00>; | |
| temp_t3_thres = <0x2d>; | |
| enable_sw_jeita; | |
| interrupts = <0x46 0x00>; | |
| io-channels = <0x2ee 0x00>; | |
| dpdm-supply = <0x7e>; | |
| interrupt-parent = <0x1f>; | |
| temp_t0_thres = <0x00>; | |
| sgm,chg-en-gpio = <0x1f 0x55 0x00>; | |
| temp_t1_thres_plus_x_degree = <0x00>; | |
| compatible = "sgm,sgm41511"; | |
| temp_t4_thres = <0x32>; | |
| sgm,irq-gpio = <0x1f 0x46 0x00>; | |
| status = "okay"; | |
| jeita_temp_t3_to_t4_cv = <0x3e8fa0>; | |
| reg = <0x1a>; | |
| phandle = <0x2f0>; | |
| temp_neg_10_thres = <0x00>; | |
| temp_t1_thres = <0x00>; | |
| temp_t4_thres_minus_x_degree = <0x30>; | |
| jeita_temp_t2_to_t3_cv = <0x426030>; | |
| jeita_temp_t1_to_t2_cv = <0x426030>; | |
| jeita_temp_below_t0_cv = <0x00>; | |
| io-channel-names = "iio_orientation"; | |
| temp_t0_thres_plus_x_degree = <0x02>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x2ef>; | |
| phandle = <0x2ed>; | |
| }; | |
| }; | |
| usb-otg-vbus { | |
| regulator-name = "usb-otg-vbus"; | |
| phandle = <0x2ec>; | |
| }; | |
| }; | |
| aw20036_led@3b { | |
| pinctrl-names = "activate", "suspend"; | |
| irq-gpio = <0x1f 0x1e 0x00>; | |
| pinctrl-0 = <0x2f9 0x2fa>; | |
| interrupts = <0x1e 0x00>; | |
| interrupt-parent = <0x1f>; | |
| reset-gpio = <0x1f 0x25 0x00>; | |
| compatible = "awinic,aw20036_led"; | |
| pinctrl-1 = <0x2fb>; | |
| status = "okay"; | |
| reg = <0x3b>; | |
| phandle = <0x305>; | |
| aw20036,led { | |
| aw20036,name = "aw20036_led_r"; | |
| aw20036,max_brightness = <0xff>; | |
| aw20036,brightness = <0x80>; | |
| aw20036,imax = <0x01>; | |
| }; | |
| }; | |
| aw35615@22 { | |
| #io-channel-cells = <0x01>; | |
| usb-otg-vbus-supply = <0x2ec>; | |
| compatible = "awinic,aw35615"; | |
| status = "okay"; | |
| awinic,int_n = <0x1f 0x27 0x00>; | |
| reg = <0x22>; | |
| phandle = <0x2ee>; | |
| connector { | |
| sink-pdos = <0x401912c 0xc0dc323c>; | |
| power-role = "dual"; | |
| source-pdos = <0x401912c>; | |
| data-role = "dual"; | |
| label = "USB-C"; | |
| try-power-role = "sink"; | |
| compatible = "usb-c-connector"; | |
| op-sink-microwatt = <0x989680>; | |
| phandle = <0x2ff>; | |
| }; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x2ed>; | |
| phandle = <0x2ef>; | |
| }; | |
| }; | |
| }; | |
| aw20036_led@3a { | |
| pinctrl-names = "activate", "suspend"; | |
| irq-gpio = <0x1f 0x14 0x00>; | |
| pinctrl-0 = <0x2f6 0x2f7>; | |
| interrupts = <0x14 0x00>; | |
| en-gpio = <0x1f 0x17 0x00>; | |
| interrupt-parent = <0x1f>; | |
| reset-gpio = <0x1f 0x15 0x00>; | |
| compatible = "awinic,aw20036_led"; | |
| pinctrl-1 = <0x2f8>; | |
| status = "okay"; | |
| reg = <0x3a>; | |
| phandle = <0x304>; | |
| aw20036,led { | |
| aw20036,name = "aw20036_led_l"; | |
| aw20036,max_brightness = <0xff>; | |
| aw20036,brightness = <0x80>; | |
| aw20036,imax = <0x01>; | |
| }; | |
| }; | |
| }; | |
| spi@4a84000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x10e>; | |
| clock-names = "se-clk"; | |
| interconnects = <0xf0 0x06 0xf0 0x202 0x26 0x00 0x27 0x226 0x28 0x17 0x26 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x148 0x04>; | |
| clocks = <0x1d 0x5e>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0xf3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x10f>; | |
| status = "disabled"; | |
| reg = <0x4a84000 0x4000>; | |
| phandle = <0x22b>; | |
| dmas = <0xf4 0x00 0x01 0x01 0x40 0x00 0xf4 0x01 0x01 0x01 0x40 0x00>; | |
| }; | |
| }; | |
| jtagmm@9440000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x0f>; | |
| reg = <0x9440000 0x1000>; | |
| phandle = <0x13f>; | |
| }; | |
| snoc { | |
| qcom,dummy-source; | |
| coresight-name = "coresight-snoc"; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x196>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8f>; | |
| phandle = <0xd7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,ipa@0x5800000 { | |
| qcom,use-ipa-tethering-bridge; | |
| qcom,ipa-hw-mode = <0x00>; | |
| qcom,svs2 = <0x13880 0x71868 0x13880 0x10bda 0x13880 0x1e>; | |
| qcom,turbo = <0x324b0 0x556eb4 0x324b0 0x15eb41 0x324b0 0x78000>; | |
| qcom,ipa-hw-ver = <0x10>; | |
| firmware-names = "ipa_fws"; | |
| qcom,nominal = <0x324b0 0x3d0900 0x324b0 0xae101 0x324b0 0x78000>; | |
| qcom,smmu-fast-map; | |
| interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa"; | |
| pas-ids = <0x0f>; | |
| qcom,skip-ieob-mask-wa; | |
| qcom,svs = <0x13880 0x1e8480 0x13880 0x414c5 0x13880 0x1ad42>; | |
| clock-names = "core_clk"; | |
| interconnects = <0x28 0x18 0x26 0x200 0x28 0x18 0x28 0x237 0x26 0x00 0x27 0x218>; | |
| reg-names = "ipa-base", "gsi-base"; | |
| qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; | |
| qcom,no-vote = <0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,throughput-threshold = <0x136 0x258 0x3e8>; | |
| interrupts = <0x00 0x101 0x04 0x00 0x103 0x04>; | |
| clocks = <0x1c 0x44>; | |
| qcom,platform-type = <0x01>; | |
| qcom,use-ipa-pm; | |
| qcom,ipa-wdi2_over_gsi; | |
| compatible = "qcom,ipa"; | |
| qcom,interconnect,num-paths = <0x03>; | |
| qcom,interconnect,num-cases = <0x05>; | |
| memory-regions = <0x76>; | |
| qcom,arm-smmu; | |
| status = "disabled"; | |
| interrupt-names = "ipa-irq", "gsi-irq"; | |
| qcom,use-64-bit-dma-mask; | |
| reg = <0x5800000 0x34000 0x5804000 0x28000>; | |
| qcom,ipa-fltrt-not-hashable; | |
| phandle = <0x183>; | |
| qcom,ee = <0x00>; | |
| qcom,modem-cfg-emb-pipe-flt; | |
| qcom,scaling-exceptions; | |
| qcom,max_num_smmu_cb = <0x03>; | |
| qcom,ipa-wdi2; | |
| qcom,ipa-endp-delay-wa; | |
| qcom,smp2p_map_ipa_1_in { | |
| interrupts-extended = <0x78 0x00 0x00>; | |
| compatible = "qcom,smp2p-map-ipa-1-in"; | |
| interrupt-names = "ipa-smp2p-in"; | |
| }; | |
| qcom,smp2p_map_ipa_1_out { | |
| qcom,smem-state-names = "ipa-smp2p-out"; | |
| compatible = "qcom,smp2p-map-ipa-1-out"; | |
| qcom,smem-states = <0x77 0x00>; | |
| }; | |
| }; | |
| cti@8867000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-turing-q6"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8867000 0x1000>; | |
| phandle = <0x1c4>; | |
| }; | |
| cti@8B5C000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-dlct-cti3"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8b5c000 0x1000>; | |
| phandle = <0x1cb>; | |
| }; | |
| syscon@f11101c { | |
| compatible = "syscon"; | |
| reg = <0xf11101c 0x04>; | |
| phandle = <0x5f>; | |
| }; | |
| cti@8011000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti1"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8011000 0x1000>; | |
| phandle = <0x1cc>; | |
| }; | |
| dcc_v2@1be2000 { | |
| dcc-ram-offset = <0x2000>; | |
| reg-names = "dcc-base", "dcc-ram-base"; | |
| compatible = "qcom,dcc-v2"; | |
| reg = <0x1be2000 0x1000 0x1bee000 0x2000>; | |
| phandle = <0x146>; | |
| }; | |
| qcom,gdsc@5f03000 { | |
| regulator-name = "mdss_core_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| qcom,proxy-consumer-enable; | |
| reg = <0x5f03000 0x04>; | |
| phandle = <0x79>; | |
| proxy-supply = <0x79>; | |
| }; | |
| qcom,smmu_sde_unsec_cb { | |
| iommus = <0x29 0x420 0x02>; | |
| compatible = "qcom,smmu_sde_unsec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x308>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-earlymap; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_5_out { | |
| qcom,smem-state-names = "rdbg-smp2p-out"; | |
| compatible = "qcom,smp2p-interrupt-rdbg-5-out"; | |
| qcom,smem-states = <0x116 0x00>; | |
| }; | |
| qcom,devfreq-cdev { | |
| qcom,devfreq = <0x43>; | |
| compatible = "qcom,devfreq-cdev"; | |
| }; | |
| cluster-device1 { | |
| power-domains = <0x14>; | |
| compatible = "qcom,lpm-cluster-dev"; | |
| }; | |
| tpda@9862000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpda-apss"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x42>; | |
| reg = <0x9862000 0x1000>; | |
| phandle = <0x1ae>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb3>; | |
| phandle = <0xa6>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb2>; | |
| phandle = <0xba>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_pll_codes { | |
| label = "dsi_pll_codes"; | |
| reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x30c>; | |
| }; | |
| msm_cdc_pinctrl@92 { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x1e8>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x1e9>; | |
| status = "disabled"; | |
| phandle = <0x32d>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| funnel@8041000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-funnel-in0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8041000 0x1000>; | |
| phandle = <0x1b7>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0xd9>; | |
| phandle = <0x8a>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0xd7>; | |
| phandle = <0x8f>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xd8>; | |
| phandle = <0xd2>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xd6>; | |
| phandle = <0xe1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@f200000 { | |
| #redistributor-regions = <0x01>; | |
| interrupts = <0x01 0x09 0x04>; | |
| interrupt-parent = <0x01>; | |
| redistributor-stride = <0x00 0x20000>; | |
| compatible = "arm,gic-v3"; | |
| #interrupt-cells = <0x03>; | |
| reg = <0xf200000 0x10000 0xf300000 0x100000>; | |
| phandle = <0x01>; | |
| interrupt-controller; | |
| }; | |
| ipa_smmu_uc { | |
| iommus = <0x29 0x142 0x00>; | |
| compatible = "qcom,ipa-smmu-uc-cb"; | |
| qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>; | |
| phandle = <0x186>; | |
| }; | |
| qcom,mdss_dsi_ctrl0@5e94000 { | |
| clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; | |
| reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; | |
| cell-index = <0x00>; | |
| interrupts = <0x04 0x00>; | |
| clocks = <0x5c 0x04 0x5c 0x05 0x5c 0x07 0x5c 0x0e 0x5c 0x0f 0x5c 0x08>; | |
| interrupt-parent = <0x30b>; | |
| label = "dsi-ctrl-0"; | |
| vdda-1p2-supply = <0x161>; | |
| compatible = "qcom,dsi-ctrl-hw-v2.4"; | |
| frame-threshold-time-us = <0x3e8>; | |
| reg = <0x5e94000 0x400 0x5f08000 0x04 0x5e6b800 0x300>; | |
| phandle = <0x30e>; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x5528>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| }; | |
| }; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,core-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "refgen"; | |
| qcom,supply-max-voltage = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,chd_gold { | |
| qcom,config-arr = <0xf0880b8 0xf0980b8 0xf0a80b8 0xf0b80b8>; | |
| label = "gold"; | |
| qcom,threshold-arr = <0xf0880b0 0xf0980b0 0xf0a80b0 0xf0b80b0>; | |
| compatible = "qcom,core-hang-detect"; | |
| }; | |
| dload_mode { | |
| compatible = "qcom,dload-mode"; | |
| }; | |
| cti@89A6000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-wcss-cti2"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x89a6000 0x1000>; | |
| phandle = <0x1c2>; | |
| }; | |
| qcom,msm-adsp-notify { | |
| compatible = "qcom,adsp-notify"; | |
| status = "ok"; | |
| phandle = <0x267>; | |
| qcom,rproc-handle = <0x167>; | |
| }; | |
| vote_lpass_audio_hw { | |
| qcom,codec-ext-clk-src = <0x0b>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x24d>; | |
| }; | |
| qcom,ipa_fws { | |
| qcom,pil-force-shutdown; | |
| memory-region = <0x76>; | |
| qcom,pas-id = <0x0f>; | |
| compatible = "qcom,pil-tz-generic"; | |
| status = "disabled"; | |
| qcom,firmware-name = "ipa_fws"; | |
| }; | |
| qcom,audio-pkt-core-platform { | |
| compatible = "qcom,audio-pkt-core-platform"; | |
| phandle = <0x265>; | |
| }; | |
| interrupt-controller@45f01b8 { | |
| qcom,num-mpm-irqs = <0x60>; | |
| reg-names = "vmpm", "ipc", "timer"; | |
| interrupts = <0x00 0xc5 0x01>; | |
| interrupt-parent = <0x01>; | |
| compatible = "qcom,mpm-bengal", "qcom,mpm"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x45f01b8 0x1000 0xf111008 0x04 0xf121000 0x1000>; | |
| phandle = <0x59>; | |
| interrupt-controller; | |
| }; | |
| remoteproc-cdsp@b300000 { | |
| qcom,smem-state-names = "stop"; | |
| clock-names = "xo"; | |
| reg-names = "cx"; | |
| memory-region = <0x33>; | |
| clocks = <0x1c 0x00>; | |
| interrupts-extended = <0x01 0x00 0x109 0x01 0x34 0x00 0x00 0x34 0x02 0x00 0x34 0x01 0x00 0x34 0x03 0x00>; | |
| cx-supply = <0x32>; | |
| compatible = "qcom,bengal-cdsp-pas"; | |
| interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; | |
| reg = <0xb300000 0x100000>; | |
| phandle = <0x67>; | |
| qcom,smem-states = <0x35 0x00>; | |
| cx-uV-uA = <0x180 0x186a0>; | |
| glink-edge { | |
| transport = "smem"; | |
| interrupts = <0x00 0x105 0x01>; | |
| qcom,glink-label = "cdsp"; | |
| label = "cdsp"; | |
| qcom,remote-pid = <0x05>; | |
| mboxes = <0x31 0x1c>; | |
| mbox-names = "cdsp_smem"; | |
| qcom,cdsp_qrtr { | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| qcom,msm_fastrpc_rpmsg { | |
| qcom,intents = <0x64 0x40>; | |
| compatible = "qcom,msm-fastrpc-rpmsg"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| }; | |
| qcom,msm_cdsprm_rpmsg { | |
| qcom,intents = <0x20 0x0c>; | |
| compatible = "qcom,msm-cdsprm-rpmsg"; | |
| qcom,glink-channels = "cdsprmglink-apps-dsp"; | |
| qcom,msm_cdsp_rm { | |
| qcom,qos-maxhold-ms = <0x14>; | |
| compatible = "qcom,msm-cdsp-rm"; | |
| phandle = <0x169>; | |
| qcom,qos-latency-us = <0x64>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qseecom@61800000 { | |
| qcom,hlos-num-ce-hw-instances = <0x01>; | |
| qseecom_mem = <0x24>; | |
| clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
| reg-names = "secapp-region"; | |
| qseecom_ta_mem = <0x25>; | |
| qcom,msm-bus,name = "qseecom-noc"; | |
| memory-region = <0x24>; | |
| clocks = <0x1c 0x46 0x1c 0x46 0x1c 0x46 0x1c 0x46>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| qcom,qsee-reentrancy-support = <0x02>; | |
| qcom,ce-opp-freq = <0xb71b000>; | |
| compatible = "qcom,qseecom"; | |
| qcom,disk-encrypt-pipe-pair = <0x02>; | |
| qcom,support-fde; | |
| qcom,appsbl-qseecom-support; | |
| qcom,qsee-ce-hw-instance = <0x00>; | |
| reg = <0x61800000 0x2100000>; | |
| phandle = <0x148>; | |
| qcom,commonlib64-loaded-by-uefi; | |
| qcom,no-user-contig-mem-support; | |
| qcom,hlos-ce-hw-instance = <0x00>; | |
| qcom,fde-key-size; | |
| }; | |
| qcom,mdss_mdp { | |
| qcom,sde-safe-lut-macrotile-qseed = <0x00 0xff00>; | |
| qcom,sde-dither-off = <0x30e0>; | |
| qcom,sde-max-per-pipe-bw-kbps = <0x27ac40 0x27ac40>; | |
| qcom,sde-smart-dma-rev = "smart_dma_v2p5"; | |
| qcom,sde-qos-cpu-irq-latency = <0x12c>; | |
| qcom,sde-vbif-off = <0x00>; | |
| qcom,sde-panic-per-pipe; | |
| qcom,sde-danger-lut = <0xff 0xffff 0x00 0x00 0xffff>; | |
| qcom,sde-sspp-smart-dma-priority = <0x02 0x01>; | |
| qcom,sde-sspp-qseed-off = <0xa00>; | |
| qcom,sde-ctl-display-pref = "primary"; | |
| qcom,sde-ubwc-swizzle = <0x07>; | |
| qcom,sde-dspp-size = <0xfe4>; | |
| qcom,sde-sspp-src-size = <0x1f8>; | |
| clock-max-rate = <0x00 0x00 0x00 0x00 0x16e36000 0x124f800 0x16e36000>; | |
| qcom,sde-intf-tear-irq-off = <0x00 0x6e800>; | |
| qcom,sde-sspp-excl-rect = <0x01 0x01>; | |
| qcom,sde-safe-lut-macrotile = <0x00 0xff00>; | |
| interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; | |
| qcom,sde-qos-lut-nrt = <0x00 0x00 0x00>; | |
| qcom,sde-axi-bus-width = <0x10>; | |
| connectors = <0x306 0x307 0x308>; | |
| qcom,sde-ib-bw-vote = <0x249f00 0x00 0x186a00>; | |
| qcom,sde-pp-size = <0xd4>; | |
| clock-names = "gcc_bus", "throttle_clk", "div_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; | |
| interconnects = <0xeb 0x0e 0x26 0x200 0x26 0x00 0x27 0x212>; | |
| reg-names = "mdp_phys", "vbif_phys", "sid_phys", "sde_imem_phys"; | |
| qcom,sde-qos-lut-macrotile-qseed = <0x00 0x112233 0x66777777>; | |
| qcom,sde-sspp-off = <0x5000 0x25000>; | |
| qcom,sde-qos-cpu-mask = <0x03>; | |
| qcom,sde-ctl-off = <0x2000>; | |
| qcom,sde-vbif-qos-nrt-remap = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-num-mnoc-ports = <0x01>; | |
| qcom,sde-cdp-setting = <0x01 0x01 0x01 0x00>; | |
| qcom,sde-dram-channels = <0x01>; | |
| qcom,sde-ctl-size = <0x1dc>; | |
| qcom,sde-csc-type = "csc-10bit"; | |
| interrupts = <0x00 0xba 0x04>; | |
| clocks = <0x1d 0x3f 0x1d 0x40 0x1d 0x3e 0x5c 0x02 0x5c 0x0a 0x5c 0x12 0x5c 0x0c>; | |
| qcom,sde-mixer-pair-mask = <0x00>; | |
| qcom,sde-dither-version = <0x10000>; | |
| qcom,sde-min-core-ib-kbps = <0x249f00>; | |
| qcom,sde-off = <0x1000>; | |
| qcom,sde-vbif-memtype-0 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| sde-vdd-supply = <0x79>; | |
| qcom,sde-sspp-clk-ctrl = <0x2ac 0x00 0x2ac 0x08>; | |
| qcom,sde-dspp-top-off = <0x1300>; | |
| #power-domain-cells = <0x00>; | |
| qcom,sde-dspp-top-size = <0x80>; | |
| qcom,sde-qos-cpu-dma-latency = <0x12c>; | |
| qcom,sde-mixer-blendstages = <0x04>; | |
| qcom,sde-safe-lut-linear = <0x00 0xfff0>; | |
| qcom,sde-qos-lut-linear = <0x00 0x112222 0x22335777>; | |
| qcom,sde-dither-size = <0x20>; | |
| qcom,sde-intf-type = "none", "dsi"; | |
| qcom,sde-safe-lut-nrt = <0x00 0xffff>; | |
| qcom,sde-mixer-linewidth = <0x800>; | |
| qcom,sde-max-per-pipe-bw-high-kbps = <0x27ac40 0x27ac40>; | |
| qcom,sde-qos-lut-macrotile = <0x00 0x112233 0x44556677>; | |
| qcom,sde-min-llcc-ib-kbps = "", "\f5"; | |
| qcom,sde-sspp-csc-off = <0x1a00>; | |
| compatible = "qcom,sde-kms"; | |
| qcom,sde-pp-off = <0x71000>; | |
| qcom,sde-ubwc-version = <0x10000000>; | |
| #interrupt-cells = <0x01>; | |
| clock-rate = <0x00 0x00 0x00 0x00 0xf424000 0x124f800 0xb71b000>; | |
| qcom,sde-intf-size = <0x2b8>; | |
| qcom,sde-intf-off = <0x00 0x6b800>; | |
| qcom,sde-mixer-size = <0x320>; | |
| qcom,sde-mixer-display-pref = "primary"; | |
| qcom,sde-has-idle-pc; | |
| qcom,sde-min-dram-ib-kbps = "", "\f5"; | |
| reg = <0x5e00000 0x8f030 0x5eb0000 0x2008 0x5e8f000 0x2c 0xc125ba4 0x20>; | |
| qcom,sde-mixer-off = <0x45000>; | |
| qcom,sde-max-bw-low-kbps = <0x2f4d60>; | |
| #list-cells = <0x01>; | |
| qcom,sde-highest-bank-bit = <0x01>; | |
| qcom,sde-vbif-id = <0x00>; | |
| phandle = <0x30b>; | |
| qcom,sde-vbif-qos-rt-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>; | |
| qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; | |
| qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; | |
| qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x249f0 0x00 0x493e0>; | |
| qcom,sde-num-nrt-paths = <0x00>; | |
| qcom,sde-mixer-stage-base-layer; | |
| qcom,sde-vbif-memtype-1 = <0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-has-cdp; | |
| qcom,sde-sspp-xin-id = <0x00 0x01>; | |
| qcom,sde-vbif-size = <0x2008>; | |
| qcom,sde-ubwc-static = <0x11f>; | |
| qcom,sde-sspp-linewidth = <0x870>; | |
| qcom,sde-qseed-scalar-version = <0x3000>; | |
| qcom,sde-secure-sid-mask = <0x421>; | |
| interrupt-controller; | |
| qcom,sde-dspp-off = <0x55000>; | |
| qcom,sde-sspp-type = "vig", "dma"; | |
| #cooling-cells = <0x02>; | |
| qcom,sde-len = <0x494>; | |
| qcom,sde-has-dim-layer; | |
| qcom,sde-max-bw-high-kbps = "", "=\t"; | |
| qcom,mdss_dsi_gh7005_960p_video { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "gh7005 video mode dsi truly panel"; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-t-clk-post = <0x0a>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,dsi-display-active; | |
| qcom,platform-en-gpio = <0x1f 0x61 0x00>; | |
| qcom,platform-reset-gpio = <0x1f 0x52 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,bl-pmic-pwm-period-usecs = <0x32>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x21>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| phandle = <0x31b>; | |
| qcom,platform-enp-gpio = <0x1f 0x2c 0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x30a>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| pwms = <0x17c 0x00 0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,platform-enn-gpio = <0x1f 0x2d 0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,platform-te-gpio = <0x1f 0x51 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xfff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-height = <0x3c0>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ee 01 39 01 00 00 00 00 02 ea 07 39 01 00 00 00 00 02 eb 12 39 01 00 00 00 00 02 05 19 39 01 00 00 00 00 02 0a 85 39 01 00 00 00 00 02 14 58 39 01 00 00 00 00 02 15 58 39 01 00 00 00 00 02 17 32 39 01 00 00 00 00 02 28 1f 39 01 00 00 00 00 02 29 29 39 01 00 00 00 00 02 2a 63 39 01 00 00 00 00 02 2f f3 39 01 00 00 00 00 02 ee 02 39 01 00 00 00 00 02 39 6f 39 01 00 00 00 00 02 00 00 39 01 00 00 00 00 02 01 10 39 01 00 00 00 00 02 02 18 39 01 00 00 00 00 02 03 09 39 01 00 00 00 00 02 04 10 39 01 00 00 00 00 02 05 42 39 01 00 00 00 00 02 06 0b 39 01 00 00 00 00 02 07 0c 39 01 00 00 00 00 02 08 0c 39 01 00 00 00 00 02 09 0b 39 01 00 00 00 00 02 0a 0f 39 01 00 00 00 00 02 0b 5f 39 01 00 00 00 00 02 0c 16 39 01 00 00 00 00 02 0d 1e 39 01 00 00 00 00 02 0e 3a 39 01 00 00 00 00 02 0f 3d 39 01 00 00 00 00 02 10 3f 39 01 00 00 00 00 02 20 00 39 01 00 00 00 00 02 21 10 39 01 00 00 00 00 02 22 18 39 01 00 00 00 00 02 23 09 39 01 00 00 00 00 02 24 10 39 01 00 00 00 00 02 25 42 39 01 00 00 00 00 02 26 0b 39 01 00 00 00 00 02 27 0c 39 01 00 00 00 00 02 28 0c 39 01 00 00 00 00 02 29 0b 39 01 00 00 00 00 02 2a 0f 39 01 00 00 00 00 02 2b 5f 39 01 00 00 00 00 02 2c 16 39 01 00 00 00 00 02 2d 1e 39 01 00 00 00 00 02 2e 3a 39 01 00 00 00 00 02 2f 3d 39 01 00 00 00 00 02 30 3f 39 01 00 00 00 00 02 ee 04 39 01 00 00 00 00 02 00 01 39 01 00 00 00 00 02 01 01 39 01 00 00 00 00 02 02 e0 39 01 00 00 00 00 02 03 05 39 01 00 00 00 00 02 04 00 39 01 00 00 00 00 02 06 14 39 01 00 00 00 00 02 07 05 39 01 00 00 00 00 02 08 12 39 01 00 00 00 00 02 09 20 39 01 00 00 00 00 02 0a 0f 39 01 00 00 00 00 02 0b 00 39 01 00 00 00 00 02 20 40 39 01 00 00 00 00 02 2a 00 39 01 00 00 00 00 02 40 80 39 01 00 00 00 00 02 41 60 39 01 00 00 00 00 02 ee 05 39 01 00 00 00 00 02 00 05 39 01 00 00 00 00 02 01 09 39 01 00 00 00 00 02 02 05 39 01 00 00 00 00 02 03 05 39 01 00 00 00 00 02 07 01 39 01 00 00 00 00 02 08 05 39 01 00 00 00 00 02 09 00 39 01 00 00 00 00 02 10 08 39 01 00 00 00 00 02 11 0c 39 01 00 00 00 00 02 12 25 39 01 00 00 00 00 02 13 05 39 01 00 00 00 00 02 19 90 39 01 00 00 00 00 02 1a 77 39 01 00 00 00 00 02 23 00 39 01 00 00 00 00 02 30 01 39 01 00 00 00 00 02 31 01 39 01 00 00 00 00 02 32 00 39 01 00 00 00 00 02 33 14 39 01 00 00 00 00 02 34 14 39 01 00 00 00 00 02 35 b4 39 01 00 00 00 00 02 36 01 39 01 00 00 00 00 02 37 01 39 01 00 00 00 00 02 38 00 39 01 00 00 00 00 02 39 14 39 01 00 00 00 00 02 3a 14 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 41 00 39 01 00 00 00 00 02 43 11 39 01 00 00 00 00 02 44 01 39 01 00 00 00 00 02 45 81 39 01 00 00 00 00 02 46 06 39 01 00 00 00 00 02 47 03 39 01 00 00 00 00 02 ee 06 39 01 00 00 00 00 02 00 23 39 01 00 00 00 00 02 01 01 39 01 00 00 00 00 02 02 04 39 01 00 00 00 00 02 06 cd 39 01 00 00 00 00 02 08 67 39 01 00 00 00 00 02 09 45 39 01 00 00 00 00 02 0a 23 39 01 00 00 00 00 02 0b 01 39 01 00 00 00 00 02 ee 07 39 01 00 00 00 00 02 00 14 39 01 00 00 00 00 02 01 14 39 01 00 00 00 00 02 02 16 39 01 00 00 00 00 02 03 16 39 01 00 00 00 00 02 04 10 39 01 00 00 00 00 02 05 10 39 01 00 00 00 00 02 06 12 39 01 00 00 00 00 02 07 12 39 01 00 00 00 00 02 08 0d 39 01 00 00 00 00 02 09 0d 39 01 00 00 00 00 02 0a 00 39 01 00 00 00 00 02 0b 00 39 01 00 00 00 00 02 0c 0c 39 01 00 00 00 00 02 0d 0c 39 01 00 00 00 00 02 0e 04 39 01 00 00 00 00 02 0f 04 39 01 00 00 00 00 02 10 3c 39 01 00 00 00 00 02 11 3c 39 01 00 00 00 00 02 12 20 39 01 00 00 00 00 02 13 20 39 01 00 00 00 00 02 14 21 39 01 00 00 00 00 02 15 21 39 01 00 00 00 00 02 20 15 39 01 00 00 00 00 02 21 15 39 01 00 00 00 00 02 22 17 39 01 00 00 00 00 02 23 17 39 01 00 00 00 00 02 24 11 39 01 00 00 00 00 02 25 11 39 01 00 00 00 00 02 26 13 39 01 00 00 00 00 02 27 13 39 01 00 00 00 00 02 28 0d 39 01 00 00 00 00 02 29 0d 39 01 00 00 00 00 02 2a 01 39 01 00 00 00 00 02 2b 01 39 01 00 00 00 00 02 2c 0c 39 01 00 00 00 00 02 2d 0c 39 01 00 00 00 00 02 2e 04 39 01 00 00 00 00 02 2f 04 39 01 00 00 00 00 02 30 3c 39 01 00 00 00 00 02 31 3c 39 01 00 00 00 00 02 32 20 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 21 39 01 00 00 00 00 02 35 21 39 01 00 00 00 00 02 ee 08 39 01 00 00 00 00 02 12 da 39 01 00 00 00 00 02 13 9b 39 01 00 00 00 00 02 18 00 39 01 00 00 00 00 02 20 00 39 01 00 00 00 00 02 2c 20 39 01 00 00 00 00 02 4b a0 39 01 00 00 00 00 02 61 20 39 01 00 00 00 00 02 ee 0f 39 01 00 00 00 00 02 00 01 39 01 00 00 00 00 02 ee 00 39 01 00 00 00 00 02 ea 00 39 01 00 00 00 00 02 eb 00 39 01 00 00 00 00 02 36 00 05 01 00 00 c8 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x3c>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x08>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1f1b0506 0x302040a 0x1f1b0506 0x302040a 0x1f1b0506 0x302040a 0x1f1b0506 0x302040a 0x1f100406 0x302040a>; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_bm5460bb1_1080p_video { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "bm5460bb1 video mode dsi truly panel"; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,dsi-display-active; | |
| qcom,platform-en-gpio = <0x1f 0x61 0x00>; | |
| qcom,platform-reset-gpio = <0x1f 0x52 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,bl-pmic-pwm-period-usecs = <0x32>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| phandle = <0x319>; | |
| qcom,platform-enp-gpio = <0x1f 0x2c 0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x30a>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| pwms = <0x17c 0x00 0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,platform-enn-gpio = <0x1f 0x2d 0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,platform-te-gpio = <0x1f 0x51 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xfff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 df 95 26 bb 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 06 b2 01 23 60 88 24 39 01 00 00 00 00 08 bb 02 11 43 32 15 11 11 39 01 00 00 00 00 03 bd 00 27 39 01 00 00 00 00 04 bc 2e 80 d3 39 01 00 00 00 00 05 bf 3a 21 3f c3 39 01 00 00 00 00 06 c0 00 ae 01 ae 01 39 01 00 00 00 00 04 c1 00 11 00 39 01 00 00 00 00 41 c3 3b 01 06 00 02 02 02 01 01 01 01 01 01 01 01 01 03 3a 40 7a 80 ba 01 c0 ff ff 00 05 03 7f 00 08 00 08 00 08 02 13 ff ff 02 13 03 00 03 02 03 03 00 03 ff ff 00 07 ff ff 03 0d 03 0d 03 0d 03 0d 39 01 00 00 00 00 40 c4 01 06 00 02 02 02 01 01 01 01 01 01 01 01 01 03 3a 40 7a 80 ba 01 c0 ff ff 00 05 03 7f 00 08 00 08 00 08 02 13 ff ff 02 13 03 00 03 02 03 03 00 03 ff ff 00 07 ff ff 03 0d 03 0d 03 0d 03 0d 39 01 00 00 00 00 18 c6 01 b8 00 36 00 07 08 82 01 00 00 01 00 01 00 00 00 00 00 39 00 00 01 39 01 00 00 00 00 02 c7 40 39 01 00 00 00 00 08 c8 35 c0 87 00 00 00 00 39 01 00 00 00 00 1d ce 00 0c 0c 0c 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 35 cf 00 3f 3f 3f 00 00 00 00 0c 00 00 00 33 33 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 ff ff 00 ff ff 00 00 00 39 01 00 00 00 00 20 d0 00 34 35 36 1f 1e 1e 1f 1f 1f 1f 1f 1f 01 1f 05 07 09 0b 1f 1e 1e 1f 1f 1f 00 00 00 00 00 00 39 01 00 00 00 00 20 d1 00 34 35 36 1f 1e 1e 1f 1f 1f 1f 1f 1f 00 1f 04 06 08 0a 1f 1e 1e 1f 1f 1f 00 00 00 00 00 00 39 01 00 00 00 00 1d d2 00 34 35 36 1f 1e 1e 1f 1f 1f 1f 1f 1f 00 1f 06 04 0a 08 1f 1f 1f 1f 1e 1e 00 00 00 39 01 00 00 00 00 1d d3 00 34 35 36 1f 1e 1e 1f 1f 1f 1f 1f 1f 01 1f 07 05 0b 09 1f 1f 1f 1f 1e 1e 00 00 00 39 01 00 00 00 00 3e d4 10 10 00 04 00 05 00 00 00 00 00 00 02 00 11 e0 01 00 04 01 01 11 e0 03 00 05 01 01 00 00 08 00 0a 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 39 01 00 00 00 00 5d d5 01 38 01 00 00 00 00 00 00 00 00 e0 00 01 00 07 32 5a 10 00 05 00 01 00 30 70 00 06 06 00 71 00 04 10 04 06 00 00 00 00 05 05 02 04 00 1b 00 00 01 00 01 00 01 00 01 00 03 00 3a 00 43 00 7a 00 83 00 ba 00 42 00 ff ff ff 3f 3f 00 00 1f ff 00 00 00 1f ff 00 ff ff ff ff ff ff 00 39 01 00 00 00 00 14 d7 00 03 c0 00 00 00 00 00 00 00 00 00 00 03 c0 00 00 00 00 39 01 00 00 00 00 02 de 01 39 01 00 00 00 00 30 c1 00 00 00 01 55 55 5a aa aa a0 00 02 0d 1e 2e 3e 4c 59 65 7c 8e 9f ae e0 07 27 43 5c 74 75 8e a5 be d9 f6 16 28 32 3c 41 46 4c 51 57 5e 63 67 39 01 00 00 00 00 30 c2 00 00 00 01 55 55 5a aa aa a0 00 02 0d 1e 2e 3e 4c 59 65 7c 8e 9f ae e0 07 27 43 5c 74 75 8e a5 be d9 f6 16 28 32 3c 41 46 4c 51 57 5e 63 67 39 01 00 00 00 00 30 c3 00 00 00 01 55 55 5a aa aa a0 00 02 0d 1e 2e 3e 4c 59 65 7c 8e 9f ae e0 07 27 43 5c 74 75 8e a5 be d9 f6 16 28 32 3c 41 46 4c 51 57 5e 63 67 39 01 00 00 00 00 30 c4 00 00 00 01 55 55 5a aa aa a0 00 02 0d 1e 2e 3e 4c 59 65 7c 8e 9f ae e0 07 27 43 5c 74 75 8e a5 be d9 f6 16 28 32 3c 41 46 4c 51 57 5e 63 67 39 01 00 00 00 00 30 c5 00 00 00 01 55 55 5a aa aa a0 00 02 0d 1e 2e 3e 4c 59 65 7c 8e 9f ae e0 07 27 43 5c 74 75 8e a5 be d9 f6 16 28 32 3c 41 46 4c 51 57 5e 63 67 39 01 00 00 00 00 30 c6 00 00 00 01 55 55 5a aa aa a0 00 02 0d 1e 2e 3e 4c 59 65 7c 8e 9f ae e0 07 27 43 5c 74 75 8e a5 be d9 f6 16 28 32 3c 41 46 4c 51 57 5e 63 67 39 01 00 00 00 00 02 de 02 39 01 00 00 00 00 06 bb 00 00 00 c0 68 39 01 00 00 00 00 02 bd 1b 39 01 00 00 00 00 02 c1 20 39 01 00 00 00 00 0e c0 20 00 00 00 00 99 99 99 99 99 99 99 99 39 01 00 00 00 00 0a c2 02 42 d0 02 00 c0 41 72 fb 39 01 00 00 00 00 02 c6 47 39 01 00 00 00 00 08 c4 00 11 0f 80 12 01 08 39 01 00 00 00 00 17 e5 10 b0 b0 c4 24 30 24 30 09 04 40 40 00 20 00 00 00 f8 28 00 00 00 39 01 00 00 00 00 02 de 00 05 01 00 00 1e 00 01 35 05 01 00 00 78 00 01 11 05 01 00 00 32 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x40>; | |
| qcom,mdss-dsi-h-back-porch = <0x24>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x231e0709 0x502040a 0x231e0709 0x502040a 0x231e0709 0x502040a 0x231e0709 0x502040a 0x23190708 0x502040a>; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_hd_plus_90hz_cmd { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox 90HZ panel without DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-t-clk-post = <0x0c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-en-gpio = <0x1f 0x53 0x00>; | |
| qcom,platform-reset-gpio = <0x1f 0x52 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x0a 0x01 0x14>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2a>; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x315>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x30a>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,platform-te-gpio = <0x1f 0x51 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-panel-height = <0x618>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 d9 09 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 04 04 04 04 04 05 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 02 f7 00 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 02 cf 39 01 00 00 00 00 05 2b 00 00 06 17 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x221e0708 0x40204a0 0x221e0708 0x40204a0 0x221e0708 0x40204a0 0x221e0708 0x40204a0 0x22170607 0x40204a0>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_td4310_1080p_video { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "td4310 video mode dsi video panel"; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,dsi-display-active; | |
| qcom,platform-en-gpio = <0x1f 0x61 0x00>; | |
| qcom,platform-reset-gpio = <0x1f 0x52 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,bl-pmic-pwm-period-usecs = <0x32>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2e>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| phandle = <0x31c>; | |
| qcom,platform-enp-gpio = <0x1f 0x2c 0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x30a>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| pwms = <0x17c 0x00 0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,platform-enn-gpio = <0x1f 0x2d 0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,platform-te-gpio = <0x1f 0x51 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xfff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = [05 01 00 00 78 00 02 11 00 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x32>; | |
| qcom,mdss-dsi-h-back-porch = <0x32>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x231f0709 0x502040a 0x231f0709 0x502040a 0x231f0709 0x502040a 0x231f0709 0x502040a 0x231a0708 0x502040a>; | |
| qcom,mdss-dsi-v-back-porch = <0x20>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0f>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_panda_1080p_video { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x57>; | |
| qcom,mdss-dsi-panel-name = "panda 1080p video mode dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x9b>; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,skip-panel-power; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2f>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| phandle = <0x31d>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x30a>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x18>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command; | |
| qcom,mdss-dsi-h-front-porch = <0x48>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x231e0809 0x50204a0 0x231e0809 0x50204a0 0x231e0809 0x50204a0 0x231e0809 0x50204a0 0x231a0809 0x50204a0>; | |
| qcom,mdss-dsi-v-back-porch = <0x0a>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command; | |
| qcom,mdss-dsi-v-front-porch = <0x28>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "sde-vdd"; | |
| qcom,supply-max-voltage = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| }; | |
| }; | |
| qcom,sde-limits { | |
| qcom,sde-bw-limits { | |
| qcom,sde-limit-ids = <0x01 0x02 0x04 0x08>; | |
| qcom,sde-limit-cases = "per_vig_pipe", "per_dma_pipe", "total_max_bw", "camera_concurrency"; | |
| qcom,sde-limit-name = "sde_bwlimit_usecases"; | |
| qcom,sde-limit-values = <0x01 0x27ac40 0x09 0x27ac40 0x02 0x27ac40 0x0a 0x27ac40 0x04 0x3d0900 0x0c 0x2f4d60>; | |
| }; | |
| qcom,sde-linewidth-limits { | |
| qcom,sde-limit-ids = <0x01 0x02 0x04>; | |
| qcom,sde-limit-cases = "vig", "dma", "scale"; | |
| qcom,sde-limit-name = "sspp_linewidth_usecases"; | |
| qcom,sde-limit-values = <0x01 0x1000 0x05 0xa00 0x02 0x870>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_td4330_truly_v2_video { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x41>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "td4330 v2 video mode dsi truly panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x81>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-t-clk-post = <0x0e>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-reset-gpio = <0x1f 0x52 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,dsi-dyn-clk-enable; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,dsi-dyn-clk-list = <0x3a2f7bc0 0x3ae9ad50 0x3aab9cc8 0x3a6d8c48>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x3c 0x37 0x30>; | |
| qcom,bl-pmic-pwm-period-usecs = <0x64>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x35>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x1c>; | |
| phandle = <0x316>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x309>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| pwms = <0x17c 0x00 0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,mdss-dsi-panel-height = <0x8e8>; | |
| qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 0d b6 30 6b 00 06 03 0a 13 1a 6c 18 19 02 29 01 00 00 00 00 05 b7 51 00 00 00 29 01 00 00 00 00 08 b8 57 3d 19 be 1e 0a 0a 29 01 00 00 00 00 08 b9 6f 3d 28 be 3c 14 0a 29 01 00 00 00 00 08 ba b5 33 41 be 64 23 0a 29 01 00 00 00 00 0c bb 44 26 c3 1f 19 06 03 c0 00 00 10 29 01 00 00 00 00 0c bc 32 4c c3 52 32 1f 03 f2 00 00 13 29 01 00 00 00 00 0c bd 24 68 c3 aa 3f 32 03 ff 00 00 25 29 01 00 00 00 00 0d be 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 0d c0 00 dc 00 dc 04 08 e8 00 04 00 03 78 29 01 00 00 00 00 24 c1 30 00 00 11 11 00 00 00 22 00 05 20 fa 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 79 c2 06 e0 6e 01 03 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 04 a0 c9 00 00 00 00 00 00 48 eb 00 00 01 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 00 00 dc 00 00 00 00 04 00 08 ef 00 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 6d c3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa aa aa 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 62 c4 00 4c 00 3f 00 83 00 00 87 86 85 84 00 00 00 00 00 61 5d 5f 00 5e 60 62 00 00 00 02 00 83 00 00 87 86 85 84 00 00 00 00 00 61 5d 5f 00 5e 60 62 ff ff ff ff ff ff 00 0f 0e 00 0f 0e 00 00 00 00 00 00 00 0f ee 00 0f ee 00 00 e0 00 00 e0 0e 00 00 00 0e 00 00 00 00 00 ff 57 00 00 00 00 00 00 00 29 01 00 00 00 00 06 c5 08 00 00 00 00 29 01 00 00 00 00 3a c6 02 0a 08 fc ff ff ff 00 00 13 01 f0 0c 06 01 43 43 43 00 00 00 01 77 09 28 28 06 01 43 43 43 00 00 00 01 61 00 00 00 1c 01 00 00 00 00 00 00 00 00 00 00 00 00 20 20 00 00 29 01 00 00 00 00 4d c7 00 00 00 e0 01 e9 02 7e 02 05 02 90 02 f6 02 40 02 5c 02 77 02 c8 02 1b 02 5b 02 bd 02 27 02 c3 03 54 03 d8 03 ff 00 00 00 e0 01 e9 02 7e 02 05 02 90 02 f6 02 40 02 5c 02 77 02 c8 02 1b 02 5b 02 bd 02 27 02 c3 03 54 03 d8 03 ff 29 01 00 00 00 00 42 c8 41 00 ff fa 00 ff 00 00 fe f6 fe e9 00 00 ff f7 fb e1 00 00 00 00 00 ff 00 00 ff fa 00 ff 00 fe f6 fe e9 00 ff f7 fb e1 00 00 00 00 ff 00 ff fa 00 ff 00 fe f6 fe e9 00 ff f7 fb e1 00 00 00 00 ff 29 01 00 00 00 00 19 c9 00 ff fa 00 ff 00 00 fe f6 fe e9 00 00 ff f7 fb e1 00 00 00 00 00 ff 00 29 01 00 00 00 00 42 ca 1c fc fc fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 0b cc 00 00 4d 8b 55 4d 8b aa 4d 8b 29 01 00 00 00 00 02 cd 00 29 01 00 00 00 00 24 ce 5d 40 49 53 59 5e 63 68 6e 74 7e 8a 98 a8 bb d0 e7 ff 04 00 04 04 42 04 69 5a 40 11 f4 00 00 84 fa 00 00 29 01 00 00 00 00 07 cf 00 00 80 46 61 00 29 01 00 00 00 00 12 d0 f6 95 11 b1 55 cf 00 f6 d3 11 f0 01 12 cf 02 20 11 29 01 00 00 00 00 23 d1 d3 d3 33 33 07 03 3b 33 77 37 77 37 35 77 07 77 f7 33 73 07 33 33 03 33 1b 03 32 3d 0a 30 13 13 20 00 29 01 00 00 00 00 05 d2 00 00 07 00 29 01 00 00 00 00 9a d3 03 00 00 00 00 00 00 0f 00 57 00 00 32 00 00 1a 70 01 19 80 01 01 f0 02 00 e0 06 ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff 29 01 00 00 00 00 05 e5 03 00 00 00 29 01 00 00 00 00 09 d5 02 42 02 42 02 dc 02 dc 29 01 00 00 00 00 02 d6 c0 29 01 00 00 00 00 32 d7 21 10 52 52 00 b6 04 fd 00 b6 04 fd 00 82 80 83 84 85 83 80 84 45 85 85 85 87 04 06 02 04 04 07 10 0c 0b 0a 0a 07 06 00 08 00 00 00 00 00 00 00 00 29 01 00 00 00 00 05 dd 30 06 23 65 29 01 00 00 00 00 0d de 00 00 00 0f ff 00 00 00 00 00 00 10 29 01 00 00 00 00 02 e3 ff 29 01 00 00 00 00 07 e6 00 00 00 00 00 00 29 01 00 00 00 00 0b e7 50 04 00 00 00 00 00 00 00 00 29 01 00 00 00 00 05 e8 00 01 23 00 29 01 00 00 00 00 1e ea 01 02 47 80 47 00 00 00 05 00 12 60 02 47 80 47 00 00 00 00 13 60 00 11 00 30 10 21 02 29 01 00 00 00 00 08 eb 00 00 00 00 01 00 11 29 01 00 00 00 00 04 ec 00 00 00 29 01 00 00 00 00 21 ed 01 01 02 02 02 02 00 00 00 00 00 00 0a 00 00 00 00 10 00 18 00 18 00 b0 00 00 00 00 00 da 10 00 29 01 00 00 00 00 61 ee 03 0f 00 00 00 00 40 1f 00 00 0f f2 3f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 01 00 09 01 8c d8 ef 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 8c ef 00 70 4a 08 d0 00 00 00 00 3c 3c 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 4a 08 d0 00 00 00 00 3c 3c 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 08 ec 50 10 00 10 00 0a 0a 00 00 00 00 10 0f 00 03 51 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 08 ec 29 01 00 00 00 00 02 b0 03 29 01 00 00 00 00 02 b0 04 29 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 03 51 ff f0 39 01 00 00 00 00 02 53 0c 39 01 00 00 00 00 02 55 00 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 08 e7 05 01 00 00 ff 00 02 29 00 05 01 00 00 ff 00 02 11 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x28>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,dsi-dyn-clk-list = <0x3a2f7bc0 0x3ae9ad50 0x3aab9cc8 0x3a6d8c48>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x2520090a 0x60304a0 0x2520090a 0x60304a0 0x2520090a 0x60304a0 0x2520090a 0x60304a0 0x251f090a 0x60304a0>; | |
| qcom,mdss-dsi-v-back-porch = <0x06>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_hx83112a_1080p_video { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "hx83112a video mode dsi truly panel"; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xcc>; | |
| qcom,dsi-display-active; | |
| qcom,platform-en-gpio = <0x1f 0x61 0x00>; | |
| qcom,platform-reset-gpio = <0x1f 0x52 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,bl-pmic-pwm-period-usecs = <0x32>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| phandle = <0x312>; | |
| qcom,platform-enp-gpio = <0x1f 0x2c 0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x30a>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| pwms = <0x17c 0x00 0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,platform-enn-gpio = <0x1f 0x2d 0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,platform-te-gpio = <0x1f 0x51 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xfff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 b9 83 11 2a 39 01 00 00 00 00 05 cf 00 14 00 c0 15 01 00 00 00 00 02 cc 08 39 01 00 00 00 00 05 c9 04 0a 8c 01 39 01 00 00 00 00 09 b1 08 29 29 80 80 4f 4a aa 39 01 00 00 00 00 10 b2 00 02 00 70 80 00 08 2a 1a 11 15 00 10 a3 87 39 01 00 00 00 00 03 d2 2c 2c 39 01 00 00 00 00 1c b4 02 d4 02 d4 02 ba 04 d4 00 00 04 d4 00 ff 00 ff 00 00 0c 12 00 2d 0e 0e 13 00 8e 39 01 00 00 00 00 09 c7 00 00 04 e0 33 00 20 40 39 01 00 00 00 00 04 b6 7b 7b e3 39 01 00 00 00 00 2b d3 c0 00 00 00 00 00 00 05 05 04 04 00 1f 0b 0b 0b 0b 32 10 0a 00 0a 32 16 23 06 23 32 10 06 00 06 00 00 00 00 00 00 00 0a 07 8b 15 01 00 00 00 00 02 bd 01 39 01 00 00 00 00 04 cb 25 11 00 39 01 00 00 00 00 02 bd 00 39 01 00 00 00 00 31 d5 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 40 40 19 19 18 18 20 20 04 04 03 03 02 02 01 01 00 00 31 31 30 30 2f 2f 39 01 00 00 00 00 31 d6 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 40 40 19 19 18 18 20 20 00 00 01 01 02 02 03 03 04 04 31 31 30 30 2f 2f 39 01 00 00 00 00 19 d8 aa aa aa ba ff ea aa aa aa ba ff ea aa aa aa ba aa aa aa aa aa ba aa aa 15 01 00 00 00 00 02 bd 01 39 01 00 00 00 00 19 d8 aa aa aa ea ff ff aa aa aa ea ff ff aa aa aa ea ff ff aa aa aa ea ff ff 15 01 00 00 00 00 02 bd 02 39 01 00 00 00 00 0d d8 aa aa aa ea ff ff aa aa aa ea ff ff 15 01 00 00 00 00 02 bd 03 39 01 00 00 00 00 19 d8 aa aa aa ba ff ea aa aa aa ba ff ea aa aa aa eb ff ff aa aa aa eb ff ff 15 01 00 00 00 00 02 bd 00 39 01 00 00 00 00 18 e7 0f 0f 1e 74 1e 72 00 50 02 02 00 00 02 02 02 05 14 14 32 b9 23 b9 08 15 01 00 00 00 00 02 bd 01 39 01 00 00 00 00 09 e7 02 00 80 01 80 0e 85 0f 15 01 00 00 00 00 02 bd 02 39 01 00 00 00 00 1e e7 00 00 08 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 00 02 00 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 e9 c3 15 01 00 00 00 00 03 cb d2 35 15 01 00 00 00 00 02 e9 3f 15 01 00 00 00 00 02 c1 01 15 01 00 00 00 00 02 bd 01 15 01 00 00 00 00 02 e9 c8 15 01 00 00 00 00 02 d3 81 15 01 00 00 00 00 02 e9 3f 15 01 00 00 00 00 02 bd 00 39 01 00 00 00 00 03 c1 01 00 15 01 00 00 00 00 02 bd 01 39 01 00 00 00 00 3a c1 ff f9 f4 ee e9 e3 df d5 d0 ca c4 bf ba b5 b0 ab a6 a2 9d 94 8c 84 7c 75 6d 65 5e 57 50 49 43 3d 36 2f 28 21 1b 15 0e 08 06 05 02 01 00 31 71 cb e7 ca 4c 7f 5c 0b 5b 1b 40 15 01 00 00 00 00 02 bd 02 39 01 00 00 00 00 3a c1 ff fa f4 ef ea e5 e1 d7 d2 cc c7 c2 bd b9 b4 af ab a6 a2 99 91 89 82 7b 73 6c 65 5e 58 51 4a 45 3f 38 31 2b 25 1e 19 12 0f 0d 0c 0a 0a 09 a1 b6 c5 21 60 eb 18 2c 32 77 40 39 01 00 00 00 00 02 bd 03 39 01 00 00 00 00 3a c1 ff fa f6 f1 ec e7 e3 d9 d4 ce c9 c4 bf bb b6 b2 ad a9 a5 9c 94 8c 85 7e 77 71 6a 63 5d 56 50 49 44 3e 38 31 2b 25 1f 18 16 14 13 11 11 30 71 79 d8 51 7b c6 72 a6 13 9a 00 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 51 07 ff 15 01 00 00 00 00 02 53 24 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x30>; | |
| qcom,mdss-dsi-h-back-porch = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x05>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x231e0709 0x502040a 0x231e0709 0x502040a 0x231e0709 0x502040a 0x231e0709 0x502040a 0x23190708 0x502040a>; | |
| qcom,mdss-dsi-v-back-porch = <0x05>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x2c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_hd_plus_90hz_video { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled video mode dsi visionox 90HZ panel without DSC"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-t-clk-post = <0x0c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-en-gpio = <0x1f 0x53 0x00>; | |
| qcom,platform-reset-gpio = <0x1f 0x52 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x0a 0x01 0x14>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2a>; | |
| phandle = <0x314>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x30a>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x618>; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2b0 0x390100 0x02 0xb3013901 0x00 0x2b08039 0x1000000 0x2e600 0x39010000 0x2d9 0x9390100 0x02 0xb0003901 0x00 0x19cf640b 0x00 0x800 0xb770101 0x1010101 0x4040404 0x4053901 0x00 0x2b00439 0x1000000 0x3eb00 0x390100 0x02 0xf7003901 0x00 0x3df5040 0x39010000 0x6f3 0x50000000 0x390100 0x02 0xf2113901 0x00 0x6f30100 0x139 0x1000000 0x3f400 0x2390100 0x02 0xf2193901 0x00 0x3df5042 0x39010000 0x52a 0x2cf 0x39010000 0x52b 0x617 0x5010000 0x78000111 0x5010000 0x129>; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x221e0708 0x40204a0 0x221e0708 0x40204a0 0x221e0708 0x40204a0 0x221e0708 0x40204a0 0x22170607 0x40204a0>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_td4330_truly_v2_cmd { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "td4330 v2 cmd mode dsi truly panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-t-clk-post = <0x0e>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-reset-gpio = <0x1f 0x52 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,dsi-dyn-clk-enable; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,dsi-dyn-clk-list = <0x38491ab0 0x3758f3d0 0x3794fd88 0x37d10740 0x380d10f0>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,bl-pmic-pwm-period-usecs = <0x64>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x36>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x1c>; | |
| phandle = <0x317>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x309>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| pwms = <0x17c 0x00 0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,platform-te-gpio = <0x1f 0x51 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,video-mode-switch-in-commands = [15 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 05 b7 51 00 00 00]; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,vid-on-commands = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 0d b6 30 6b 00 06 03 0a 13 1a 6c 18 19 02 29 01 00 00 00 00 05 b7 51 00 00 00 29 01 00 00 00 00 08 b8 57 3d 19 be 1e 0a 0a 29 01 00 00 00 00 08 b9 6f 3d 28 be 3c 14 0a 29 01 00 00 00 00 08 ba b5 33 41 be 64 23 0a 29 01 00 00 00 00 0c bb 44 26 c3 1f 19 06 03 c0 00 00 10 29 01 00 00 00 00 0c bc 32 4c c3 52 32 1f 03 f2 00 00 13 29 01 00 00 00 00 0c bd 24 68 c3 aa 3f 32 03 ff 00 00 25 29 01 00 00 00 00 0d be 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 0d c0 00 dc 00 dc 04 08 e8 00 04 00 03 78 29 01 00 00 00 00 24 c1 30 00 00 11 11 00 00 00 22 00 05 20 fa 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 79 c2 06 e0 6e 01 03 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 04 a0 c9 00 00 00 00 00 00 48 eb 00 00 01 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 00 00 dc 00 00 00 00 04 00 08 ef 00 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 6d c3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa aa aa 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 62 c4 00 4c 00 3f 00 83 00 00 87 86 85 84 00 00 00 00 00 61 5d 5f 00 5e 60 62 00 00 00 02 00 83 00 00 87 86 85 84 00 00 00 00 00 61 5d 5f 00 5e 60 62 ff ff ff ff ff ff 00 0f 0e 00 0f 0e 00 00 00 00 00 00 00 0f ee 00 0f ee 00 00 e0 00 00 e0 0e 00 00 00 0e 00 00 00 00 00 ff 57 00 00 00 00 00 00 00 29 01 00 00 00 00 06 c5 08 00 00 00 00 29 01 00 00 00 00 3a c6 02 0a 08 fc ff ff ff 00 00 13 01 f0 0c 06 01 43 43 43 00 00 00 01 77 09 28 28 06 01 43 43 43 00 00 00 01 61 00 00 00 1c 01 00 00 00 00 00 00 00 00 00 00 00 00 20 20 00 00 29 01 00 00 00 00 4d c7 00 00 00 e0 01 e9 02 7e 02 05 02 90 02 f6 02 40 02 5c 02 77 02 c8 02 1b 02 5b 02 bd 02 27 02 c3 03 54 03 d8 03 ff 00 00 00 e0 01 e9 02 7e 02 05 02 90 02 f6 02 40 02 5c 02 77 02 c8 02 1b 02 5b 02 bd 02 27 02 c3 03 54 03 d8 03 ff 29 01 00 00 00 00 42 c8 41 00 ff fa 00 ff 00 00 fe f6 fe e9 00 00 ff f7 fb e1 00 00 00 00 00 ff 00 00 ff fa 00 ff 00 fe f6 fe e9 00 ff f7 fb e1 00 00 00 00 ff 00 ff fa 00 ff 00 fe f6 fe e9 00 ff f7 fb e1 00 00 00 00 ff 29 01 00 00 00 00 19 c9 00 ff fa 00 ff 00 00 fe f6 fe e9 00 00 ff f7 fb e1 00 00 00 00 00 ff 00 29 01 00 00 00 00 42 ca 1c fc fc fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 0b cc 00 00 4d 8b 55 4d 8b aa 4d 8b 29 01 00 00 00 00 02 cd 00 29 01 00 00 00 00 24 ce 5d 40 49 53 59 5e 63 68 6e 74 7e 8a 98 a8 bb d0 e7 ff 04 00 04 04 42 04 69 5a 40 11 f4 00 00 84 fa 00 00 29 01 00 00 00 00 07 cf 00 00 80 46 61 00 29 01 00 00 00 00 12 d0 f6 95 11 b1 55 cf 00 f6 d3 11 f0 01 12 cf 02 20 11 29 01 00 00 00 00 23 d1 d3 d3 33 33 07 03 3b 33 77 37 77 37 35 77 07 77 f7 33 73 07 33 33 03 33 1b 03 32 3d 0a 30 13 13 20 00 29 01 00 00 00 00 05 d2 00 00 07 00 29 01 00 00 00 00 9a d3 03 00 00 00 00 00 00 0f 00 57 00 00 32 00 00 1a 70 01 19 80 01 01 f0 02 00 e0 06 ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff 29 01 00 00 00 00 05 e5 03 00 00 00 29 01 00 00 00 00 09 d5 02 42 02 42 02 dc 02 dc 29 01 00 00 00 00 02 d6 c0 29 01 00 00 00 00 32 d7 21 10 52 52 00 b6 04 fd 00 b6 04 fd 00 82 80 83 84 85 83 80 84 45 85 85 85 87 04 06 02 04 04 07 10 0c 0b 0a 0a 07 06 00 08 00 00 00 00 00 00 00 00 29 01 00 00 00 00 05 dd 30 06 23 65 29 01 00 00 00 00 0d de 00 00 00 0f ff 00 00 00 00 00 00 10 29 01 00 00 00 00 02 e3 ff 29 01 00 00 00 00 07 e6 00 00 00 00 00 00 29 01 00 00 00 00 0b e7 50 04 00 00 00 00 00 00 00 00 29 01 00 00 00 00 05 e8 00 01 23 00 29 01 00 00 00 00 1e ea 01 02 47 80 47 00 00 00 05 00 12 60 02 47 80 47 00 00 00 00 13 60 00 11 00 30 10 21 02 29 01 00 00 00 00 08 eb 00 00 00 00 01 00 11 29 01 00 00 00 00 04 ec 00 00 00 29 01 00 00 00 00 21 ed 01 01 02 02 02 02 00 00 00 00 00 00 0a 00 00 00 00 10 00 18 00 18 00 b0 00 00 00 00 00 da 10 00 29 01 00 00 00 00 61 ee 03 0f 00 00 00 00 40 1f 00 00 0f f2 3f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 01 00 09 01 8c d8 ef 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 8c ef 00 70 4a 08 d0 00 00 00 00 3c 3c 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 4a 08 d0 00 00 00 00 3c 3c 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 08 ec 50 10 00 10 00 0a 0a 00 00 00 00 10 0f 00 03 51 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 08 ec 29 01 00 00 00 00 02 b0 03 29 01 00 00 00 00 02 b0 04 29 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 03 51 ff f0 39 01 00 00 00 00 02 53 0c 39 01 00 00 00 00 02 55 00 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 08 e7 05 01 00 00 ff 00 02 29 00 05 01 00 00 ff 00 02 11 00]; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-video-mode; | |
| qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x8e8>; | |
| qcom,mdss-dsi-h-front-porch = <0x50>; | |
| qcom,mdss-dsi-h-back-porch = <0x50>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,dsi-dyn-clk-list = <0x38491ab0 0x3758f3d0 0x3794fd88 0x37d10740 0x380d10f0>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,cmd-on-commands = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 0d b6 30 6b 00 06 03 0a 13 1a 6c 18 19 02 29 01 00 00 00 00 05 b7 40 00 00 00 29 01 00 00 00 00 08 b8 57 3d 19 be 1e 0a 0a 29 01 00 00 00 00 08 b9 6f 3d 28 be 3c 14 0a 29 01 00 00 00 00 08 ba b5 33 41 be 64 23 0a 29 01 00 00 00 00 0c bb 44 26 c3 1f 19 06 03 c0 00 00 10 29 01 00 00 00 00 0c bc 32 4c c3 52 32 1f 03 f2 00 00 13 29 01 00 00 00 00 0c bd 24 68 c3 aa 3f 32 03 ff 00 00 25 29 01 00 00 00 00 0d be 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 0d c0 00 dc 00 dc 04 08 e8 00 04 00 03 78 29 01 00 00 00 00 24 c1 30 00 00 11 11 00 00 00 22 00 05 20 fa 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 79 c2 06 e0 6e 01 03 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 04 a0 c9 00 00 00 00 00 00 48 eb 00 00 01 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 00 00 dc 00 00 00 00 04 00 08 ef 00 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 6d c3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa aa aa 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 62 c4 00 4c 00 3f 00 83 00 00 87 86 85 84 00 00 00 00 00 61 5d 5f 00 5e 60 62 00 00 00 02 00 83 00 00 87 86 85 84 00 00 00 00 00 61 5d 5f 00 5e 60 62 ff ff ff ff ff ff 00 0f 0e 00 0f 0e 00 00 00 00 00 00 00 0f ee 00 0f ee 00 00 e0 00 00 e0 0e 00 00 00 0e 00 00 00 00 00 ff 57 00 00 00 00 00 00 00 29 01 00 00 00 00 06 c5 08 00 00 00 00 29 01 00 00 00 00 3a c6 02 0a 08 fc ff ff ff 00 00 13 01 f0 0c 06 01 43 43 43 00 00 00 01 77 09 28 28 06 01 43 43 43 00 00 00 01 61 00 00 00 1c 01 00 00 00 00 00 00 00 00 00 00 00 00 20 20 00 00 29 01 00 00 00 00 4d c7 00 00 00 e0 01 e9 02 7e 02 05 02 90 02 f6 02 40 02 5c 02 77 02 c8 02 1b 02 5b 02 bd 02 27 02 c3 03 54 03 d8 03 ff 00 00 00 e0 01 e9 02 7e 02 05 02 90 02 f6 02 40 02 5c 02 77 02 c8 02 1b 02 5b 02 bd 02 27 02 c3 03 54 03 d8 03 ff 29 01 00 00 00 00 42 c8 41 00 ff fa 00 ff 00 00 fe f6 fe e9 00 00 ff f7 fb e1 00 00 00 00 00 ff 00 00 ff fa 00 ff 00 fe f6 fe e9 00 ff f7 fb e1 00 00 00 00 ff 00 ff fa 00 ff 00 fe f6 fe e9 00 ff f7 fb e1 00 00 00 00 ff 29 01 00 00 00 00 19 c9 00 ff fa 00 ff 00 00 fe f6 fe e9 00 00 ff f7 fb e1 00 00 00 00 00 ff 00 29 01 00 00 00 00 42 ca 1c fc fc fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 0b cc 00 00 4d 8b 55 4d 8b aa 4d 8b 29 01 00 00 00 00 02 cd 00 29 01 00 00 00 00 24 ce 5d 40 49 53 59 5e 63 68 6e 74 7e 8a 98 a8 bb d0 e7 ff 04 00 04 04 42 04 69 5a 40 11 f4 00 00 84 fa 00 00 29 01 00 00 00 00 07 cf 00 00 80 46 61 00 29 01 00 00 00 00 12 d0 f6 95 11 b1 55 cf 00 f6 d3 11 f0 01 12 cf 02 20 11 29 01 00 00 00 00 23 d1 d3 d3 33 33 07 03 3b 33 77 37 77 37 35 77 07 77 f7 33 73 07 33 33 03 33 1b 03 32 3d 0a 30 13 13 20 00 29 01 00 00 00 00 05 d2 00 00 07 00 29 01 00 00 00 00 9a d3 03 00 00 00 00 00 00 0f 00 57 00 00 32 00 00 1a 70 01 19 80 01 01 f0 02 00 e0 06 ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff ff f7 ff 29 01 00 00 00 00 05 e5 03 00 00 00 29 01 00 00 00 00 09 d5 02 42 02 42 02 dc 02 dc 29 01 00 00 00 00 02 d6 c0 29 01 00 00 00 00 32 d7 21 10 52 52 00 b6 04 fd 00 b6 04 fd 00 82 80 83 84 85 83 80 84 45 85 85 85 87 04 06 02 04 04 07 10 0c 0b 0a 0a 07 06 00 08 00 00 00 00 00 00 00 00 29 01 00 00 00 00 05 dd 30 06 23 65 29 01 00 00 00 00 0d de 00 00 00 0f ff 00 00 00 00 00 00 10 29 01 00 00 00 00 02 e3 ff 29 01 00 00 00 00 07 e6 00 00 00 00 00 00 29 01 00 00 00 00 0b e7 50 04 00 00 00 00 00 00 00 00 29 01 00 00 00 00 05 e8 00 01 23 00 29 01 00 00 00 00 1e ea 01 02 47 80 47 00 00 00 05 00 13 60 02 47 80 47 00 00 00 00 13 60 00 11 00 30 10 21 02 29 01 00 00 00 00 08 eb 00 00 00 00 01 00 11 29 01 00 00 00 00 04 ec 00 00 00 29 01 00 00 00 00 21 ed 01 01 02 02 02 02 00 00 00 00 00 00 0a 00 00 00 00 10 00 18 00 18 00 b0 00 00 00 00 00 da 10 00 29 01 00 00 00 00 61 ee 03 0f 00 00 00 00 40 1f 00 00 0f f2 3f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 01 00 09 01 8c d8 ef 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 8c ef 00 70 4a 08 d0 00 00 00 00 3c 3c 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 4a 08 d0 00 00 00 00 3c 3c 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 08 ec 50 10 00 10 00 0a 0a 00 00 00 00 10 0f 00 03 51 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 08 ec 29 01 00 00 00 00 02 b0 03 29 01 00 00 00 00 02 b0 04 29 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 03 51 ff f0 39 01 00 00 00 00 02 53 0c 39 01 00 00 00 00 02 55 00 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 08 e7 05 01 00 00 ff 00 02 29 00 05 01 00 00 ff 00 02 11 00]; | |
| qcom,mdss-dsi-panel-phy-timings = <0x2620090b 0x60204a0 0x2620090b 0x60204a0 0x2620090b 0x60204a0 0x2620090b 0x60204a0 0x261f090b 0x60204a0>; | |
| qcom,mdss-dsi-v-back-porch = <0x0d>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x28 0x28 0x28 0x28 0x28 0x28>; | |
| qcom,mdss-dsi-cmd-mode; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,cmd-mode-switch-in-commands = [15 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 05 b7 40 00 00 00]; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-sspp-vig-blocks { | |
| qcom,sde-vig-qseed-size = <0xa0>; | |
| qcom,sde-vig-csc-off = <0x1a00>; | |
| qcom,sde-vig-inverse-pma; | |
| qcom,sde-vig-qseed-off = <0xa00>; | |
| }; | |
| qcom,sde-dspp-blocks { | |
| qcom,sde-dspp-memcolor = <0x880 0x10007>; | |
| qcom,sde-dspp-gc = <0x17c0 0x10008>; | |
| qcom,sde-dspp-pcc = <0x1700 0x40000>; | |
| qcom,sde-dspp-igc = <0x00 0x30001>; | |
| qcom,sde-dspp-hist = <0x800 0x10007>; | |
| qcom,sde-dspp-vlut = <0xa00 0x10008>; | |
| qcom,sde-dspp-dither = <0x82c 0x10007>; | |
| qcom,sde-dspp-sixzone = <0x900 0x10007>; | |
| qcom,sde-dspp-hsic = <0x800 0x10007>; | |
| }; | |
| }; | |
| tgu@9900000 { | |
| arm,primecell-periphid = <0x3b999>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tgu-base"; | |
| interrupts = <0x00 0x35 0x01 0x00 0x36 0x01 0x00 0x37 0x01 0x00 0x38 0x01>; | |
| clocks = <0x1c 0x08>; | |
| tgu-regs = <0x08>; | |
| tgu-steps = <0x03>; | |
| coresight-name = "coresight-tgu-apss"; | |
| tgu-conditions = <0x04>; | |
| compatible = "arm,primecell"; | |
| reg = <0x9900000 0x1000>; | |
| phandle = <0x18f>; | |
| tgu-timer-counters = <0x08>; | |
| }; | |
| qcom,cpu-vendor-hooks { | |
| compatible = "qcom,cpu-vendor-hooks"; | |
| phandle = <0x147>; | |
| }; | |
| qcom,gdsc@147d074 { | |
| qcom,no-status-check-on-disable; | |
| regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x147d074 0x04>; | |
| phandle = <0xea>; | |
| }; | |
| etm@9240000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| cpu = <0x0d>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9240000 0x1000>; | |
| phandle = <0x1a3>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9e>; | |
| phandle = <0xaa>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,memshare { | |
| compatible = "qcom,memshare"; | |
| qcom,client_2 { | |
| qcom,peripheral-size = <0x00>; | |
| qcom,client-id = <0x02>; | |
| label = "modem"; | |
| compatible = "qcom,memshare-peripheral"; | |
| }; | |
| qcom,client_3 { | |
| qcom,peripheral-size = <0x500000>; | |
| qcom,client-id = <0x01>; | |
| qcom,allocate-on-request; | |
| label = "modem"; | |
| compatible = "qcom,memshare-peripheral"; | |
| phandle = <0x143>; | |
| }; | |
| qcom,client_1 { | |
| qcom,peripheral-size = <0x00>; | |
| qcom,client-id = <0x00>; | |
| label = "modem"; | |
| qcom,allocate-boot-time; | |
| compatible = "qcom,memshare-peripheral"; | |
| }; | |
| }; | |
| disp_rdump_region@5c000000 { | |
| label = "disp_rdump_region"; | |
| reg = <0x00 0x5c000000 0x00 0xf00000>; | |
| phandle = <0x323>; | |
| }; | |
| csr@8001000 { | |
| qcom,set-byte-cntr-support; | |
| qcom,blk-size = <0x01>; | |
| qcom,hwctrl-set-support; | |
| reg-names = "csr-base"; | |
| coresight-name = "coresight-csr"; | |
| qcom,usb-bam-support; | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0x8001000 0x1000>; | |
| phandle = <0x88>; | |
| }; | |
| qcom,gdsc@1458098 { | |
| qcom,support-hw-trigger; | |
| regulator-name = "gcc_vcodec0_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x1458098 0x04>; | |
| phandle = <0x189>; | |
| }; | |
| jtagmm@9340000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x0e>; | |
| reg = <0x9340000 0x1000>; | |
| phandle = <0x13e>; | |
| }; | |
| cti@801f000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti15"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x801f000 0x1000>; | |
| phandle = <0x1d2>; | |
| }; | |
| remoteproc-adsp@ab00000 { | |
| qcom,smem-state-names = "stop"; | |
| mx-supply = <0x2d>; | |
| clock-names = "xo"; | |
| reg-names = "cx", "mx"; | |
| memory-region = <0x2e>; | |
| clocks = <0x1c 0x00>; | |
| mx-uV-uA = <0x180 0x00>; | |
| interrupts-extended = <0x01 0x00 0x11a 0x01 0x2f 0x00 0x00 0x2f 0x02 0x00 0x2f 0x01 0x00 0x2f 0x03 0x00>; | |
| cx-supply = <0x2c>; | |
| compatible = "qcom,bengal-adsp-pas"; | |
| interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; | |
| reg = <0xab00000 0x100>; | |
| phandle = <0x167>; | |
| qcom,smem-states = <0x30 0x00>; | |
| cx-uV-uA = <0x180 0x00>; | |
| glink-edge { | |
| transport = "smem"; | |
| interrupts = <0x00 0x115 0x01>; | |
| qcom,glink-label = "lpass"; | |
| label = "adsp"; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x168>; | |
| mboxes = <0x31 0x08>; | |
| mbox-names = "adsp_smem"; | |
| qcom,msm_fastrpc_rpmsg { | |
| qcom,intents = <0x64 0x40>; | |
| compatible = "qcom,msm-fastrpc-rpmsg"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| }; | |
| qcom,gpr { | |
| qcom,intents = <0x200 0x14>; | |
| compatible = "qcom,gpr"; | |
| reg = <0x02>; | |
| phandle = <0x2e3>; | |
| qcom,glink-channels = "adsp_apps"; | |
| audio-pkt { | |
| qcom,audiopkt-ch-name = "apr_audio_svc"; | |
| compatible = "qcom,audio-pkt"; | |
| reg = <0x17>; | |
| }; | |
| q6prm { | |
| compatible = "qcom,audio_prm"; | |
| reg = <0x07>; | |
| phandle = <0x2e4>; | |
| }; | |
| spf_core { | |
| compatible = "qcom,spf_core"; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| qcom,apr_tal_rpmsg { | |
| qcom,intents = <0x200 0x14>; | |
| qcom,glink-channels = "apr_audio_svc"; | |
| }; | |
| qcom,adsp_qrtr { | |
| qcom,no-wake-svc = <0x190>; | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2p_sleepstate { | |
| interrupts = <0x00 0x00>; | |
| interrupt-parent = <0x6b>; | |
| compatible = "qcom,smp2p-sleepstate"; | |
| interrupt-names = "smp2p-sleepstate-in"; | |
| qcom,smem-states = <0x6a 0x00>; | |
| }; | |
| tmc@8048000 { | |
| iommus = <0x29 0x180 0x00 0x29 0x160 0x00>; | |
| arm,buffer-size = <0x400000>; | |
| arm,primecell-periphid = <0xbb961>; | |
| coresight-ctis = <0xe3>; | |
| #address-cells = <0x01>; | |
| arm,scatter-gather; | |
| csr-irqctrl-offset = <0x6c>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tmc-base", "bam-base"; | |
| qcom,sw-usb; | |
| byte-cntr-class-name = "coresight-tmc-etr-stream"; | |
| interrupts = <0x00 0x1ad 0x01>; | |
| clocks = <0x1c 0x08>; | |
| byte-cntr-name = "byte-cntr"; | |
| #size-cells = <0x01>; | |
| coresight-name = "coresight-tmc-etr"; | |
| compatible = "arm,primecell"; | |
| ranges; | |
| interrupt-names = "byte-cntr-irq"; | |
| qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; | |
| reg = <0x8048000 0x1000 0x8064000 0x15000>; | |
| phandle = <0x1bc>; | |
| coresight-csr = <0x88>; | |
| qcom,mem_support; | |
| qcom,iommu-dma = "bypass"; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe8>; | |
| phandle = <0xe6>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@8b58000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-center"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8b58000 0x1000>; | |
| phandle = <0x192>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8b>; | |
| phandle = <0xc6>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,limits-1-dcvs@f550800 { | |
| qcom,affinity = <0x01>; | |
| interrupts = <0x00 0x25 0x04>; | |
| compatible = "qcom,msm-hw-limits"; | |
| reg = <0xf550800 0x1000 0xf523000 0x1000>; | |
| phandle = <0x0a>; | |
| }; | |
| sdhc1-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x38>; | |
| opp-100000000 { | |
| opp-peak-kBps = <0x3d090 0x208c8>; | |
| opp-hz = <0x00 0x5f5e100>; | |
| opp-avg-kBps = <0x19640 0x00>; | |
| }; | |
| opp-384000000 { | |
| opp-peak-kBps = <0xc3500 0x493e0>; | |
| opp-hz = <0x00 0x16e36000>; | |
| opp-avg-kBps = <0x61a80 0x00>; | |
| }; | |
| }; | |
| smcinvoke@61800000 { | |
| reg-names = "secapp-region"; | |
| qcom,support-legacy_smc; | |
| compatible = "qcom,smcinvoke"; | |
| reg = <0x61800000 0x2100000>; | |
| phandle = <0x149>; | |
| }; | |
| syscon@0x003C0000 { | |
| compatible = "syscon"; | |
| reg = <0x3c0000 0x40000>; | |
| phandle = <0x1b>; | |
| }; | |
| qcom,mdss_rotator { | |
| power-domains = <0x30b>; | |
| qcom,mdss-rot-mode = <0x01>; | |
| rot-vdd-supply = <0x79>; | |
| qcom,mdss-rot-safe-lut = <0xffff 0xffff>; | |
| interconnect-names = "qcom,rot-data-bus0", "qcom,sde-reg-bus"; | |
| clock-names = "gcc_iface", "iface_clk", "rot_clk"; | |
| interconnects = <0xeb 0x0e 0x26 0x200 0x26 0x00 0x27 0x212>; | |
| reg-names = "mdp_phys", "rot_vbif_phys"; | |
| qcom,msm-bus,name = "mdss_rotator"; | |
| interrupts = <0x02 0x00>; | |
| clocks = <0x1d 0x3d 0x5c 0x02 0x5c 0x10>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| interrupt-parent = <0x30b>; | |
| qcom,mdss-sbuf-headroom = <0x14>; | |
| qcom,mdss-rot-xin-id = <0x0a 0x0b>; | |
| qcom,mdss-rot-vbif-qos-setting = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| compatible = "qcom,sde_rotator"; | |
| qcom,mdss-rot-cdp-setting = <0x01 0x01>; | |
| qcom,mdss-rot-danger-lut = <0x00 0x00>; | |
| qcom,mdss-default-ot-rd-limit = <0x20>; | |
| qcom,supply-names = "rot-vdd"; | |
| qcom,mdss-rot-qos-lut = <0x00 0x00 0x00 0x00>; | |
| qcom,mdss-default-ot-wr-limit = <0x20>; | |
| reg = <0x5e00000 0xac000 0x5eb0000 0x2008>; | |
| #list-cells = <0x01>; | |
| qcom,mdss-rot-parent = <0x30b 0x00>; | |
| phandle = <0x31e>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800>; | |
| qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x12c00>; | |
| qcom,smmu_rot_unsec_cb { | |
| iommus = <0x29 0x43c 0x00>; | |
| compatible = "qcom,smmu_sde_rot_unsec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x31f>; | |
| qcom,iommu-faults = "non-fatal"; | |
| }; | |
| qcom,smmu_rot_sec_cb { | |
| iommus = <0x29 0x43d 0x00>; | |
| compatible = "qcom,smmu_sde_rot_sec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x320>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| }; | |
| cti@801c000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti12"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x801c000 0x1000>; | |
| phandle = <0x1cf>; | |
| }; | |
| qcom,rmtfs_sharedmem@0 { | |
| reg-names = "rmtfs"; | |
| qcom,client-id = <0x01>; | |
| qcom,guard-memory; | |
| compatible = "qcom,sharedmem-uio"; | |
| reg = <0x00 0x200000>; | |
| qcom,vm-nav-path; | |
| }; | |
| va_core_clk { | |
| qcom,codec-ext-clk-src = <0x02>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x32b>; | |
| qcom,codec-lpass-clk-id = <0x307>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| ufsphy_mem@4807000 { | |
| clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; | |
| reg-names = "phy_mem"; | |
| lanes-per-direction = <0x01>; | |
| resets = <0x3a 0x00>; | |
| clocks = <0x1c 0x00 0x1d 0xa5 0x1d 0x7a>; | |
| vdda-phy-supply = <0x80>; | |
| #phy-cells = <0x00>; | |
| vdda-pll-supply = <0x81>; | |
| compatible = "qcom,ufs-phy-qmp-v3-660"; | |
| status = "disabled"; | |
| vdda-phy-max-microamp = <0xc8c8>; | |
| reg = <0x4807000 0xdb8>; | |
| phandle = <0x3b>; | |
| vdda-pll-max-microamp = <0x3778>; | |
| }; | |
| tpdm@8860000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-turing"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8860000 0x1000>; | |
| phandle = <0xc0>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x91>; | |
| phandle = <0xc3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cpu-pmu { | |
| interrupts = <0x01 0x06 0x04>; | |
| qcom,irq-is-percpu; | |
| compatible = "arm,armv8-pmuv3"; | |
| phandle = <0x14e>; | |
| }; | |
| qcom,msm-eud@1610000 { | |
| clock-names = "eud_ahb2phy_clk"; | |
| reg-names = "eud_base", "eud_mode_mgr2", "eud_tcsr_check_reg"; | |
| interrupts = <0x00 0xbd 0x04>; | |
| clocks = <0x1d 0x95>; | |
| qcom,eud-tcsr-check-enable; | |
| qcom,secure-eud-en; | |
| compatible = "qcom,msm-eud"; | |
| status = "ok"; | |
| interrupt-names = "eud_irq"; | |
| reg = <0x1610000 0x2000 0x1612000 0x1000 0x3e5018 0x04>; | |
| phandle = <0x14f>; | |
| qcom,eud-clock-vote-req; | |
| }; | |
| qcom,smp2p-adsp { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x00 0x117 0x01>; | |
| qcom,remote-pid = <0x02>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x31 0x0a>; | |
| qcom,smem = <0x1bb 0x1ad>; | |
| qcom,smp2p-rdbg2-out { | |
| qcom,entry-name = "rdbg"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x114>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x2f>; | |
| interrupt-controller; | |
| }; | |
| qcom,sleepstate-in { | |
| qcom,entry-name = "sleepstate_see"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x6b>; | |
| interrupt-controller; | |
| }; | |
| sleepstate-out { | |
| qcom,entry-name = "sleepstate"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x6a>; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x30>; | |
| }; | |
| qcom,smp2p-rdbg2-in { | |
| qcom,entry-name = "rdbg"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x115>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| cti@8B30000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-cortex_M3"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8b30000 0x1000>; | |
| phandle = <0x1bd>; | |
| }; | |
| qcom,smmu_sde_sec_cb { | |
| iommus = <0x29 0x421 0x00>; | |
| compatible = "qcom,smmu_sde_sec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x307>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| hwevent { | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-hwevent"; | |
| compatible = "qcom,coresight-hwevent"; | |
| coresight-csr = <0x88>; | |
| }; | |
| tsens@c222000 { | |
| reg-names = "tsens_srot_physical", "tsens_tm_physical"; | |
| interrupts = <0x00 0x113 0x04 0x00 0xbe 0x04>; | |
| interrupts-extended = <0x01 0x00 0x113 0x04 0x59 0x02 0x04>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,tsens24xx"; | |
| interrupt-names = "tsens-upper-lower", "tsens-critical"; | |
| reg = <0x4410000 0x08 0x4411000 0x1ff>; | |
| phandle = <0x3d>; | |
| tsens-reinit-wa; | |
| }; | |
| syscon@5991508 { | |
| compatible = "syscon"; | |
| reg = <0x5991508 0x04>; | |
| phandle = <0x7c>; | |
| }; | |
| usb_audio_qmi_dev { | |
| iommus = <0x29 0x1cf 0x00>; | |
| qcom,usb-audio-intr-num = <0x02>; | |
| compatible = "qcom,usb-audio-qmi-dev"; | |
| qcom,usb-audio-stream-id = <0x0f>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| qcom,msm-adsprpc-mem { | |
| restrict-access; | |
| memory-region = <0x68>; | |
| compatible = "qcom,msm-adsprpc-mem-region"; | |
| }; | |
| interconnect@4480000 { | |
| clock-names = "bus", "bus_a"; | |
| clocks = <0x1c 0x06 0x1c 0x07>; | |
| #interconnect-cells = <0x01>; | |
| compatible = "qcom,bengal-bimc"; | |
| qcom,util-factor = <0x99>; | |
| reg = <0x4480000 0x80000>; | |
| phandle = <0x26>; | |
| qcom,keepalive; | |
| }; | |
| qcom,cpu-pause { | |
| compatible = "qcom,thermal-pause"; | |
| pause-cpu3 { | |
| qcom,cpus = <0x0e>; | |
| qcom,cdev-alias = "pause-cpu3"; | |
| }; | |
| cpu6-pause { | |
| qcom,cpus = <0x11>; | |
| qcom,cdev-alias = "thermal-pause-40"; | |
| phandle = <0x4c>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu1 { | |
| qcom,cpus = <0x0c>; | |
| qcom,cdev-alias = "pause-cpu1"; | |
| }; | |
| cpu3-pause { | |
| qcom,cpus = <0x0e>; | |
| qcom,cdev-alias = "thermal-pause-8"; | |
| phandle = <0x53>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu7-pause { | |
| qcom,cpus = <0x12>; | |
| qcom,cdev-alias = "thermal-pause-80"; | |
| phandle = <0x4f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu6 { | |
| qcom,cpus = <0x11>; | |
| qcom,cdev-alias = "pause-cpu6"; | |
| }; | |
| pause-cpu4 { | |
| qcom,cpus = <0x0f>; | |
| qcom,cdev-alias = "pause-cpu4"; | |
| }; | |
| cpu4-pause { | |
| qcom,cpus = <0x0f>; | |
| qcom,cdev-alias = "thermal-pause-10"; | |
| phandle = <0x48>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu2 { | |
| qcom,cpus = <0x0d>; | |
| qcom,cdev-alias = "pause-cpu2"; | |
| }; | |
| pause-cpu0 { | |
| qcom,cpus = <0x0b>; | |
| qcom,cdev-alias = "pause-cpu0"; | |
| }; | |
| cpu1-pause { | |
| qcom,cpus = <0x0c>; | |
| qcom,cdev-alias = "thermal-pause-2"; | |
| phandle = <0x51>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu5-pause { | |
| qcom,cpus = <0x10>; | |
| qcom,cdev-alias = "thermal-pause-20"; | |
| phandle = <0x4a>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu7 { | |
| qcom,cpus = <0x12>; | |
| qcom,cdev-alias = "pause-cpu7"; | |
| }; | |
| pause-cpu5 { | |
| qcom,cpus = <0x10>; | |
| qcom,cdev-alias = "pause-cpu5"; | |
| }; | |
| cpu2-pause { | |
| qcom,cpus = <0x0d>; | |
| qcom,cdev-alias = "thermal-pause-4"; | |
| phandle = <0x52>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_2_out { | |
| qcom,smem-state-names = "rdbg-smp2p-out"; | |
| compatible = "qcom,smp2p-interrupt-rdbg-2-out"; | |
| qcom,smem-states = <0x114 0x00>; | |
| }; | |
| tpdm@8a26000 { | |
| qcom,dummy-source; | |
| coresight-name = "coresight-tpdm-lpass"; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x197>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x90>; | |
| phandle = <0xd0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@9832000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpda-actpm"; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x4d>; | |
| reg = <0x9832000 0x1000>; | |
| phandle = <0x1ad>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb1>; | |
| phandle = <0xa4>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb0>; | |
| phandle = <0xb8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,dsi-display-primary { | |
| pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; | |
| pinctrl-2 = <0x313>; | |
| qcom,panel-te-source = <0x00>; | |
| pinctrl-0 = <0x310 0x210 0x214>; | |
| clock-names = "pll_byte_clk0", "pll_dsi_clk0", "mdp_core_clk"; | |
| clocks = <0x30f 0x00 0x30f 0x01 0x5c 0x0a>; | |
| label = "primary"; | |
| qcom,dsi-phy = <0x30f>; | |
| compatible = "qcom,dsi-display"; | |
| vddio-supply = <0x20>; | |
| pinctrl-1 = <0x311 0x211 0x215>; | |
| phandle = <0x306>; | |
| qcom,dsi-ctrl = <0x30e>; | |
| qcom,dsi-default-panel = <0x312>; | |
| qcom,mdp = <0x30b>; | |
| qcom,platform-te-gpio = <0x1f 0x51 0x00>; | |
| }; | |
| qcom,dcvs { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,dcvs"; | |
| ranges; | |
| phandle = <0x180>; | |
| ddr { | |
| qcom,bus-width = <0x08>; | |
| qcom,dcvs-hw-type = <0x00>; | |
| qcom,freq-tbl = <0x73>; | |
| compatible = "qcom,dcvs-hw"; | |
| phandle = <0x74>; | |
| sp { | |
| interconnects = <0x26 0x00 0x26 0x200>; | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x75>; | |
| qcom,dcvs-path-type = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,logbuf-vendor-hooks { | |
| compatible = "qcom,logbuf-vendor-hooks"; | |
| phandle = <0x16f>; | |
| }; | |
| qcom,glinkpkt { | |
| compatible = "qcom,glinkpkt"; | |
| qcom,glinkpkt-apr-apps2 { | |
| qcom,glinkpkt-edge = "adsp"; | |
| qcom,glinkpkt-dev-name = "apr_apps2"; | |
| qcom,glinkpkt-ch-name = "apr_apps2"; | |
| }; | |
| qcom,glinkpkt-data11 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd11"; | |
| qcom,glinkpkt-ch-name = "DATA11"; | |
| }; | |
| qcom,glinkpkt-data1 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd7"; | |
| qcom,glinkpkt-ch-name = "DATA1"; | |
| }; | |
| qcom,glinkpkt-data40-cntl { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smdcntl8"; | |
| qcom,glinkpkt-ch-name = "DATA40_CNTL"; | |
| }; | |
| qcom,glinkpkt-data4 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd8"; | |
| qcom,glinkpkt-ch-name = "DATA4"; | |
| }; | |
| qcom,glinkpkt-at-mdm0 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "at_mdm0"; | |
| qcom,glinkpkt-ch-name = "DS"; | |
| }; | |
| }; | |
| qcom,rpm-master-stats@45f0150 { | |
| qcom,master-offset = <0x1000>; | |
| qcom,master-stats-version = <0x02>; | |
| compatible = "qcom,rpm-master-stats"; | |
| reg = <0x45f0150 0x5000>; | |
| qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; | |
| }; | |
| thermal-zones { | |
| phandle = <0x16c>; | |
| cdsp-hvx { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0x3d 0x01>; | |
| trips { | |
| cdsp-cx-mon { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x42>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cdsp-trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x4e20>; | |
| type = "passive"; | |
| phandle = <0x3e>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cdsp-trip1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x40>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cdsp-cdev0 { | |
| trip = <0x40>; | |
| cooling-device = <0x41 0xffffffff 0xffffffff>; | |
| }; | |
| cxip-cdev { | |
| trip = <0x3e>; | |
| cooling-device = <0x3f 0x01 0x01>; | |
| }; | |
| cdsp-cx-cdev2 { | |
| trip = <0x42>; | |
| cooling-device = <0x45 0x03 0x03>; | |
| }; | |
| cdsp-cx-cdev0 { | |
| trip = <0x42>; | |
| cooling-device = <0x43 0x04 0xffffffff>; | |
| }; | |
| cdsp-cx-cdev3 { | |
| trip = <0x42>; | |
| cooling-device = <0x41 0x04 0x04>; | |
| }; | |
| cdsp-cx-cdev1 { | |
| trip = <0x42>; | |
| cooling-device = <0x44 0x03 0x03>; | |
| }; | |
| }; | |
| }; | |
| video { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x04>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpu { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0x3d 0x0f>; | |
| trips { | |
| gpu-cx-mon { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x56>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| gpu-trip { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x55>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu-cx-cdev3 { | |
| trip = <0x56>; | |
| cooling-device = <0x41 0x04 0x04>; | |
| }; | |
| gpu-cx-cdev1 { | |
| trip = <0x56>; | |
| cooling-device = <0x44 0x03 0x03>; | |
| }; | |
| gpu_cdev { | |
| trip = <0x55>; | |
| cooling-device = <0x43 0xffffffff 0xffffffff>; | |
| }; | |
| gpu-cx-cdev2 { | |
| trip = <0x56>; | |
| cooling-device = <0x45 0x03 0x03>; | |
| }; | |
| gpu-cx-cdev0 { | |
| trip = <0x56>; | |
| cooling-device = <0x43 0x04 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| quiet-therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x57 0x01>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm6125-tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x3c>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x16d>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x16e>; | |
| }; | |
| }; | |
| cooling-maps { | |
| trip1_cpu6 { | |
| trip = <0x16e>; | |
| cooling-device = <0x4c 0x01 0x01>; | |
| }; | |
| trip1_cpu4 { | |
| trip = <0x16e>; | |
| cooling-device = <0x48 0x01 0x01>; | |
| }; | |
| trip0_cpu6 { | |
| trip = <0x16d>; | |
| cooling-device = <0x11 0x06 0xffffffff>; | |
| }; | |
| trip1_cpu2 { | |
| trip = <0x16e>; | |
| cooling-device = <0x52 0x01 0x01>; | |
| }; | |
| trip0_cpu4 { | |
| trip = <0x16d>; | |
| cooling-device = <0x0f 0x06 0xffffffff>; | |
| }; | |
| trip0_cpu2 { | |
| trip = <0x16d>; | |
| cooling-device = <0x0d 0x07 0x07>; | |
| }; | |
| trip0_cpu0 { | |
| trip = <0x16d>; | |
| cooling-device = <0x0b 0x07 0x07>; | |
| }; | |
| trip1_cpu7 { | |
| trip = <0x16e>; | |
| cooling-device = <0x4f 0x01 0x01>; | |
| }; | |
| trip1_cpu5 { | |
| trip = <0x16e>; | |
| cooling-device = <0x4a 0x01 0x01>; | |
| }; | |
| trip0_cpu7 { | |
| trip = <0x16d>; | |
| cooling-device = <0x12 0x06 0xffffffff>; | |
| }; | |
| trip1_cpu3 { | |
| trip = <0x16e>; | |
| cooling-device = <0x53 0x01 0x01>; | |
| }; | |
| trip0_cpu5 { | |
| trip = <0x16d>; | |
| cooling-device = <0x10 0x06 0xffffffff>; | |
| }; | |
| trip1_cpu1 { | |
| trip = <0x16e>; | |
| cooling-device = <0x51 0x01 0x01>; | |
| }; | |
| trip0_cpu3 { | |
| trip = <0x16d>; | |
| cooling-device = <0x0e 0x07 0x07>; | |
| }; | |
| trip0_cpu1 { | |
| trip = <0x16d>; | |
| cooling-device = <0x0c 0x07 0x07>; | |
| }; | |
| }; | |
| }; | |
| mdm-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x05>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| mdm1-cx-mon { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x46>; | |
| }; | |
| }; | |
| cooling-maps { | |
| mdm1-cx-cdev3 { | |
| trip = <0x46>; | |
| cooling-device = <0x41 0x04 0x04>; | |
| }; | |
| mdm1-cx-cdev1 { | |
| trip = <0x46>; | |
| cooling-device = <0x44 0x03 0x03>; | |
| }; | |
| mdm1-cx-cdev2 { | |
| trip = <0x46>; | |
| cooling-device = <0x45 0x03 0x03>; | |
| }; | |
| mdm1-cx-cdev0 { | |
| trip = <0x46>; | |
| cooling-device = <0x43 0x04 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| camera { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x03>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| xo-therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x57 0x02>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpuss-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x0c>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| silv-cpus-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x50>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu2_cdev { | |
| trip = <0x50>; | |
| cooling-device = <0x52 0x01 0x01>; | |
| }; | |
| cpu1_cdev { | |
| trip = <0x50>; | |
| cooling-device = <0x51 0x01 0x01>; | |
| }; | |
| cpu3_cdev { | |
| trip = <0x50>; | |
| cooling-device = <0x53 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x08>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu6-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x4b>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu6_cdev { | |
| trip = <0x4b>; | |
| cooling-device = <0x4c 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| display { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x0e>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpuss-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x0a>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu-4-5-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x4d>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu5_cdev { | |
| trip = <0x4d>; | |
| cooling-device = <0x4a 0x01 0x01>; | |
| }; | |
| cpu4_cdev { | |
| trip = <0x4d>; | |
| cooling-device = <0x48 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x06>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu4-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x47>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu4_cdev { | |
| trip = <0x47>; | |
| cooling-device = <0x48 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| camera-therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x58 0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| wlan { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x02>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| emmc-ufs-therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x58 0x01>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mdm-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x0d>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| mdm0-cx-mon { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x54>; | |
| }; | |
| }; | |
| cooling-maps { | |
| mdm0-cx-cdev2 { | |
| trip = <0x54>; | |
| cooling-device = <0x45 0x03 0x03>; | |
| }; | |
| mdm0-cx-cdev0 { | |
| trip = <0x54>; | |
| cooling-device = <0x43 0x04 0xffffffff>; | |
| }; | |
| mdm0-cx-cdev3 { | |
| trip = <0x54>; | |
| cooling-device = <0x41 0x04 0x04>; | |
| }; | |
| mdm0-cx-cdev1 { | |
| trip = <0x54>; | |
| cooling-device = <0x44 0x03 0x03>; | |
| }; | |
| }; | |
| }; | |
| cpuss-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x0b>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu-6-7-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x4e>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu7_cdev { | |
| trip = <0x4e>; | |
| cooling-device = <0x4f 0x01 0x01>; | |
| }; | |
| cpu6_cdev { | |
| trip = <0x4e>; | |
| cooling-device = <0x4c 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| rf-pa1-therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x57 0x03>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mapss { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x00>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x3d 0x07>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu5-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x49>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu5_cdev { | |
| trip = <0x49>; | |
| cooling-device = <0x4a 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pa-therm0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x57 0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_phy0@5e94400 { | |
| pll-label = "dsi_pll_14nm"; | |
| qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; | |
| reg-names = "dsi_phy", "pll_base", "phy_clamp_base", "dyn_refresh_base"; | |
| cell-index = <0x00>; | |
| memory-region = <0x30d>; | |
| #clock-cells = <0x01>; | |
| label = "dsi-phy-0"; | |
| qcom,platform-lane-config = <0x100f 0x100f 0x100f 0x100f 0x108f>; | |
| compatible = "qcom,dsi-phy-v2.0"; | |
| vdda-0p9-supply = <0x2b>; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| reg = <0x5e94400 0x588 0x5e94800 0x188 0x5e01400 0x100 0x5e94200 0x100>; | |
| phandle = <0x30f>; | |
| pll_codes_region = <0x30c>; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-off-min-voltage = <0x10>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-max-voltage = <0x1a0>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x100>; | |
| }; | |
| }; | |
| }; | |
| qcom,kgsl-3d0@5900000 { | |
| qcom,enable-ca-jump; | |
| qcom,ubwc-mode = <0x01>; | |
| nvmem-cells = <0x175 0x176>; | |
| interconnect-names = "gpu_icc_path"; | |
| vddcx-supply = <0xe9>; | |
| qcom,bus-table-cnoc = <0x00 0x64>; | |
| clock-names = "core_clk", "rbbmtimer_clk", "iface_clk", "ahb_clk", "mem_clk", "gmu_clk", "smmu_vote", "apb_pclk", "gpu_cc_ahb", "gcc_gpu_memnoc_gfx", "gpu_cc_hlos1_vote_gpu_smmu", "gcc_gpu_snoc_dvm_gfx"; | |
| interconnects = <0x26 0x04 0x26 0x200>; | |
| reg-names = "kgsl_3d0_reg_memory", "cx_dbgc"; | |
| qcom,initial-pwrlevel = <0x06>; | |
| interrupts = <0x00 0xb1 0x04>; | |
| clocks = <0x5d 0x0d 0x5d 0x0a 0x1d 0x96 0x5d 0x04 0x1d 0x4c 0x5d 0x07 0x5d 0x10 0x1c 0x08 0x5d 0x04 0x1d 0x4c 0x5d 0x10 0x1d 0x4d>; | |
| qcom,bus-table-ddr = <0x00 0xbebc2 0x17d784 0x23c346 0x35c36d 0x41351d 0x512e78 0x5b8d80 0x793c60 0xa14a48 0xb95ed5 0xd70db6 0xf962c6>; | |
| qcom,chipid = <0x6010000>; | |
| label = "kgsl-3d0"; | |
| qcom,gpu-model = "Adreno610v1"; | |
| qcom,ca-target-pwrlevel = <0x05>; | |
| vdd-supply = <0x18c>; | |
| compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; | |
| status = "ok"; | |
| qcom,gpu-qdss-stm = <0xe1c0000 0x40000>; | |
| interrupt-names = "kgsl_3d0_irq"; | |
| nvmem-cell-names = "speed_bin", "gaming_bin"; | |
| reg = <0x5900000 0x90000 0x5961000 0x800>; | |
| regulator-names = "vddcx", "vdd"; | |
| phandle = <0x43>; | |
| qcom,min-access-length = <0x40>; | |
| #cooling-cells = <0x02>; | |
| qcom,ca-busy-penalty = <0x2ee0>; | |
| qcom,gpu-mempools { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,gpu-mempools"; | |
| qcom,gpu-mempool@2 { | |
| reg = <0x02>; | |
| qcom,mempool-reserved = <0x100>; | |
| qcom,mempool-page-size = <0x10000>; | |
| }; | |
| qcom,gpu-mempool@0 { | |
| qcom,mempool-allocate; | |
| reg = <0x00>; | |
| qcom,mempool-page-size = <0x1000>; | |
| }; | |
| qcom,gpu-mempool@3 { | |
| reg = <0x03>; | |
| qcom,mempool-reserved = <0x20>; | |
| qcom,mempool-page-size = <0x100000>; | |
| }; | |
| qcom,gpu-mempool@1 { | |
| qcom,mempool-allocate; | |
| reg = <0x01>; | |
| qcom,mempool-page-size = <0x2000>; | |
| }; | |
| }; | |
| qcom,gpu-mempools-lowmem { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,gpu-mempools-lowmem"; | |
| qcom,gpu-mempool@2 { | |
| qcom,mempool-allocate; | |
| qcom,mempool-max-pages = <0x100>; | |
| reg = <0x02>; | |
| qcom,mempool-page-size = <0x10000>; | |
| }; | |
| qcom,gpu-mempool@0 { | |
| qcom,mempool-allocate; | |
| reg = <0x00>; | |
| qcom,mempool-page-size = <0x1000>; | |
| }; | |
| qcom,gpu-mempool@3 { | |
| qcom,mempool-allocate; | |
| qcom,mempool-max-pages = <0x20>; | |
| reg = <0x03>; | |
| qcom,mempool-page-size = <0x100000>; | |
| }; | |
| qcom,gpu-mempool@1 { | |
| qcom,mempool-allocate; | |
| reg = <0x01>; | |
| qcom,mempool-page-size = <0x2000>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevel-bins { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,gpu-pwrlevel-bins"; | |
| qcom,gpu-pwrlevels-4 { | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x03>; | |
| #size-cells = <0x00>; | |
| qcom,ca-target-pwrlevel = <0x02>; | |
| qcom,speed-bin = <0x9d>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0xc0>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x08>; | |
| qcom,bus-max = <0x0a>; | |
| qcom,gpu-freq = <0x23c34600>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x80>; | |
| qcom,bus-min = <0x05>; | |
| qcom,bus-freq = <0x07>; | |
| qcom,bus-max = <0x08>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x100>; | |
| qcom,bus-min = <0x09>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x2c67cc40>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x03>; | |
| qcom,bus-freq = <0x04>; | |
| qcom,bus-max = <0x05>; | |
| qcom,gpu-freq = <0x1312d000>; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-2 { | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x06>; | |
| #size-cells = <0x00>; | |
| qcom,ca-target-pwrlevel = <0x05>; | |
| qcom,speed-bin = <0xce>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x180>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x35a4e900>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x03>; | |
| qcom,bus-freq = <0x04>; | |
| qcom,bus-max = <0x05>; | |
| qcom,gpu-freq = <0x1312d000>; | |
| reg = <0x06>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0xc0>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x08>; | |
| qcom,bus-max = <0x09>; | |
| qcom,gpu-freq = <0x23c34600>; | |
| reg = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x140>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0a>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x30e03500>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x1a0>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x3a699d00>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,level = <0x80>; | |
| qcom,bus-min = <0x05>; | |
| qcom,bus-freq = <0x07>; | |
| qcom,bus-max = <0x08>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| reg = <0x05>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x100>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x09>; | |
| qcom,bus-max = <0x0a>; | |
| qcom,gpu-freq = <0x2c67cc40>; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-0 { | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x07>; | |
| #size-cells = <0x00>; | |
| qcom,ca-target-pwrlevel = <0x06>; | |
| qcom,speed-bin = <0x00>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x1a0>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x3a699d00>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@8 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,level = <0x80>; | |
| qcom,bus-min = <0x05>; | |
| qcom,bus-freq = <0x07>; | |
| qcom,bus-max = <0x08>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| reg = <0x06>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0x100>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x09>; | |
| qcom,bus-max = <0x0a>; | |
| qcom,gpu-freq = <0x2c67cc40>; | |
| reg = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x180>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x35a4e900>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x1d0>; | |
| qcom,bus-min = <0x0b>; | |
| qcom,bus-freq = <0x0c>; | |
| qcom,bus-max = <0x0c>; | |
| qcom,gpu-freq = <0x3e95ba80>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x03>; | |
| qcom,bus-freq = <0x04>; | |
| qcom,bus-max = <0x05>; | |
| qcom,gpu-freq = <0x1312d000>; | |
| reg = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,level = <0xc0>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x08>; | |
| qcom,bus-max = <0x09>; | |
| qcom,gpu-freq = <0x23c34600>; | |
| reg = <0x05>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x140>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0a>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x30e03500>; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-5 { | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,ca-target-pwrlevel = <0x01>; | |
| qcom,speed-bin = <0x7f>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x80>; | |
| qcom,bus-min = <0x05>; | |
| qcom,bus-freq = <0x07>; | |
| qcom,bus-max = <0x09>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x03>; | |
| qcom,bus-freq = <0x04>; | |
| qcom,bus-max = <0x05>; | |
| qcom,gpu-freq = <0x1312d000>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0xc0>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x23c34600>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-3 { | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x06>; | |
| #size-cells = <0x00>; | |
| qcom,ca-target-pwrlevel = <0x05>; | |
| qcom,speed-bin = <0xc8>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x180>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x35a4e900>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x03>; | |
| qcom,bus-freq = <0x04>; | |
| qcom,bus-max = <0x05>; | |
| qcom,gpu-freq = <0x1312d000>; | |
| reg = <0x06>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0xc0>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x08>; | |
| qcom,bus-max = <0x09>; | |
| qcom,gpu-freq = <0x23c34600>; | |
| reg = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x140>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0a>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x30e03500>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x1a0>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x389fd980>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,level = <0x80>; | |
| qcom,bus-min = <0x05>; | |
| qcom,bus-freq = <0x07>; | |
| qcom,bus-max = <0x08>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| reg = <0x05>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x100>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x09>; | |
| qcom,bus-max = <0x0a>; | |
| qcom,gpu-freq = <0x2c67cc40>; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-1 { | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x07>; | |
| #size-cells = <0x00>; | |
| qcom,ca-target-pwrlevel = <0x06>; | |
| qcom,speed-bin = <0xdd>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x1a0>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x3a699d00>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@8 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,level = <0x80>; | |
| qcom,bus-min = <0x05>; | |
| qcom,bus-freq = <0x07>; | |
| qcom,bus-max = <0x08>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| reg = <0x06>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0x100>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x09>; | |
| qcom,bus-max = <0x0a>; | |
| qcom,gpu-freq = <0x2c67cc40>; | |
| reg = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x180>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0b>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x35a4e900>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x1d0>; | |
| qcom,bus-min = <0x0b>; | |
| qcom,bus-freq = <0x0c>; | |
| qcom,bus-max = <0x0c>; | |
| qcom,gpu-freq = <0x3e95ba80>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x03>; | |
| qcom,bus-freq = <0x04>; | |
| qcom,bus-max = <0x05>; | |
| qcom,gpu-freq = <0x1312d000>; | |
| reg = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,level = <0xc0>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x08>; | |
| qcom,bus-max = <0x09>; | |
| qcom,gpu-freq = <0x23c34600>; | |
| reg = <0x05>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x140>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0a>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,gpu-freq = <0x30e03500>; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| }; | |
| zap-shader { | |
| memory-region = <0x137>; | |
| }; | |
| }; | |
| wcn3990 { | |
| qcom,bt-vdd-xtal-config = <0x19f0a0 0x1cfde0 0x01 0x00>; | |
| qcom,bt-vdd-io-config = <0x19f0a0 0x1cfde0 0x01 0x00>; | |
| qcom,bt-vdd-core-supply = <0x21>; | |
| qcom,bt-vdd-pa-supply = <0x22>; | |
| qcom,bt-vdd-xtal-supply = <0x23>; | |
| compatible = "qcom,wcn3990"; | |
| qcom,bt-vdd-io-supply = <0x20>; | |
| qcom,bt-vdd-core-config = <0x13e5c0 0x13e5c0 0x01 0x00>; | |
| phandle = <0x24a>; | |
| qcom,bt-sw-ctrl-gpio = <0x1f 0x57 0x00>; | |
| qcom,bt-vdd-pa-config = <0x2dc6c0 0x328980 0x01 0x00>; | |
| }; | |
| clock-controller@5990000 { | |
| #reset-cells = <0x01>; | |
| clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; | |
| reg-names = "cc_base"; | |
| clocks = <0x1c 0x00 0x1d 0x49 0x1d 0x4a>; | |
| #clock-cells = <0x01>; | |
| vdd_mx-supply = <0x2b>; | |
| compatible = "qcom,sm6115-gpucc", "syscon"; | |
| reg = <0x5990000 0x9000>; | |
| phandle = <0x5d>; | |
| vdd_cx-supply = <0x32>; | |
| }; | |
| rpm-glink { | |
| interrupts = <0x00 0xc2 0x01>; | |
| compatible = "qcom,glink-rpm"; | |
| qcom,rpm-msg-ram = <0x69>; | |
| mboxes = <0x31 0x00>; | |
| }; | |
| qcom,dma-heaps { | |
| compatible = "qcom,dma-heaps"; | |
| qcom,display { | |
| memory-region = <0x86>; | |
| qcom,dma-heap-name = "qcom,display"; | |
| qcom,max-align = <0x09>; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,audio_ml { | |
| memory-region = <0x87>; | |
| qcom,dma-heap-name = "qcom,audio-ml"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,qseecom_ta { | |
| memory-region = <0x25>; | |
| qcom,dma-heap-name = "qcom,qseecom-ta"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,qseecom { | |
| memory-region = <0x24>; | |
| qcom,dma-heap-name = "qcom,qseecom"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,secure_cdsp { | |
| qcom,token = <0x20000000>; | |
| memory-region = <0x83>; | |
| qcom,dma-heap-name = "qcom,secure-cdsp"; | |
| qcom,dma-heap-type = <0x00>; | |
| }; | |
| qcom,secure_display { | |
| memory-region = <0x84>; | |
| qcom,dma-heap-name = "qcom,secure-display"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,user_contig { | |
| memory-region = <0x85>; | |
| qcom,dma-heap-name = "qcom,user-contig"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| }; | |
| cti@8019000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti9"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8019000 0x1000>; | |
| phandle = <0x1da>; | |
| }; | |
| qcom,msm-cdsp-loader { | |
| compatible = "qcom,cdsp-loader"; | |
| qcom,proc-img-to-load = "cdsp"; | |
| qcom,rproc-handle = <0x67>; | |
| }; | |
| dma_dev { | |
| memory-region = <0xef>; | |
| compatible = "qcom,iommu-dma"; | |
| }; | |
| qcom,vidc@5a00000 { | |
| qcom,allowed-clock-rates = <0x16e36000 0x16e36000 0x16e36000 0x16e36000>; | |
| #address-cells = <0x01>; | |
| pas-id = <0x09>; | |
| interconnect-names = "venus-cnoc", "venus-ddr"; | |
| clock-names = "core_clk", "iface_clk", "bus_clk", "core0_clk", "core0_bus_clk", "throttle_clk"; | |
| vidc,firmware-name = "venus"; | |
| interconnects = <0x26 0x00 0x27 0x22f 0xed 0x0b 0x26 0x200>; | |
| venus-supply = <0x18a>; | |
| clock-ids = <0x92 0x8d 0x8c 0x90 0x8a 0x8f>; | |
| memory-region = <0x138>; | |
| interrupts = <0x00 0xe1 0x04>; | |
| clocks = <0x1d 0x92 0x1d 0x8d 0x1d 0x8c 0x1d 0x90 0x1d 0x8a 0x1d 0x8f>; | |
| #size-cells = <0x01>; | |
| qcom,reg-presets = <0xb0080 0x00 0x03>; | |
| com,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", "core0_clk", "core0_bus_clk", "throttle_clk"; | |
| compatible = "qcom,msm-vidc", "qcom,msm-vidc-khaje", "qcom,msm-vidc-bengal", "qcom,msm-vidc-ar50lt"; | |
| status = "okay"; | |
| reg = <0x5a00000 0x200000>; | |
| phandle = <0x23d>; | |
| qcom,clock-configs = <0x01 0x00 0x00 0x01 0x00 0x00>; | |
| venus-core0-supply = <0x189>; | |
| qcom,bus-range-kbps = <0x3e8 0x3e8 0x3e8 0x632ea0>; | |
| non_secure_cb { | |
| iommus = <0x29 0x860 0x00 0x29 0x880 0x00>; | |
| virtual-addr-pool = <0x70800000 0x6f800000>; | |
| label = "venus_ns"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>; | |
| qcom,iommu-faults = "non-fatal", "stall-disable"; | |
| }; | |
| secure_non_pixel_cb { | |
| iommus = <0x29 0x804 0xe0>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x1000000 0x24800000>; | |
| label = "venus_sec_non_pixel"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; | |
| qcom,iommu-faults = "non-fatal", "stall-disable"; | |
| qcom,iommu-vmid = <0x0b>; | |
| }; | |
| secure_bitstream_cb { | |
| iommus = <0x29 0x861 0x04>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x4b000000 0x25800000>; | |
| label = "venus_sec_bitstream"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>; | |
| qcom,iommu-faults = "non-fatal", "stall-disable"; | |
| qcom,iommu-vmid = <0x09>; | |
| }; | |
| secure_pixel_cb { | |
| iommus = <0x29 0x863 0x00>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x25800000 0x25800000>; | |
| label = "venus_sec_pixel"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>; | |
| qcom,iommu-faults = "non-fatal", "stall-disable"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| }; | |
| vibrator { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x2f5>; | |
| clock-names = "gpio-pwm-clk"; | |
| clocks = <0x1d 0x42>; | |
| compatible = "pwm-gpio-vibrator"; | |
| vcc-supply = <0x2f4>; | |
| }; | |
| funnel@8861000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-funnel-turing"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8861000 0x1000>; | |
| phandle = <0x1b3>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xc3>; | |
| phandle = <0x91>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xc4>; | |
| phandle = <0x92>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| source = <0xc0>; | |
| remote-endpoint = <0xbf>; | |
| phandle = <0xc8>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| source = <0xc2>; | |
| remote-endpoint = <0xc1>; | |
| phandle = <0xd4>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply_no_labibb { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x30a>; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-enable-load = <0xf230>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| }; | |
| }; | |
| clocks { | |
| xo_board { | |
| clock-output-names = "xo_board"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x170>; | |
| }; | |
| sleep_clk { | |
| clock-output-names = "sleep_clk"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x7ffc>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x5b>; | |
| }; | |
| }; | |
| memory@045f0000 { | |
| compatible = "qcom,rpm-msg-ram"; | |
| reg = <0x45f0000 0x7000>; | |
| phandle = <0x69>; | |
| }; | |
| etm@9140000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| cpu = <0x0c>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9140000 0x1000>; | |
| phandle = <0x1a2>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9d>; | |
| phandle = <0xa9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@8016000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti6"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8016000 0x1000>; | |
| phandle = <0x1d7>; | |
| }; | |
| tx_core_clk { | |
| qcom,codec-ext-clk-src = <0x07>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x327>; | |
| qcom,codec-lpass-clk-id = <0x30c>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| qcom,sps { | |
| qcom,pipe-attr-ee; | |
| compatible = "qcom,msm-sps-4k"; | |
| }; | |
| qrng@1b53000 { | |
| interconnect-names = "data_path"; | |
| qcom,msm-rng-iface-clk; | |
| clock-names = "km_clk_src"; | |
| interconnects = <0x26 0x00 0x27 0x23f>; | |
| qcom,no-qrng-config; | |
| clocks = <0x1d 0x54>; | |
| compatible = "qcom,msm-rng"; | |
| reg = <0x1b53000 0x1000>; | |
| phandle = <0x14a>; | |
| }; | |
| jtagmm@9240000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x0d>; | |
| reg = <0x9240000 0x1000>; | |
| phandle = <0x13d>; | |
| }; | |
| interconnect@0 { | |
| clock-names = "bus", "bus_a"; | |
| clocks = <0x1c 0x6e 0x1c 0x6f>; | |
| #interconnect-cells = <0x01>; | |
| compatible = "qcom,bengal-mmnrt_virt"; | |
| qcom,util-factor = <0x8e>; | |
| phandle = <0xed>; | |
| qcom,keepalive; | |
| }; | |
| cti@8013000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti3"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8013000 0x1000>; | |
| phandle = <0x1d4>; | |
| }; | |
| csr@8a03000 { | |
| qcom,blk-size = <0x01>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "csr-base"; | |
| qcom,aodbg-csr-support; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-swao-csr"; | |
| qcom,timestamp-support; | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0x8a03000 0x1000>; | |
| phandle = <0x190>; | |
| }; | |
| tpdm@8a58000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-west"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8a58000 0x1000>; | |
| phandle = <0x19c>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x97>; | |
| phandle = <0xcd>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ufshc@4804000 { | |
| iommus = <0x29 0x100 0x00>; | |
| vcc-max-microamp = <0x927c0>; | |
| #reset-cells = <0x01>; | |
| freq-table-hz = <0x2faf080 0xbebc200 0x00 0x00 0x00 0x00 0x23c3460 0x8f0d180 0x47868c0 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,ufs-bus-bw,name = "ufshc_mem"; | |
| nvmem-cells = <0x37>; | |
| interconnect-names = "ufs-ddr", "cpu-ufs"; | |
| phy-names = "ufsphy"; | |
| clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk"; | |
| interconnects = <0x28 0x1d 0x26 0x200 0x26 0x00 0x27 0x23e>; | |
| reg-names = "ufs_mem", "ufs_ice"; | |
| qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "MAX"; | |
| non-removable; | |
| lanes-per-direction = <0x01>; | |
| qcom,vddp-ref-clk-max-microamp = <0x64>; | |
| resets = <0x1d 0x03>; | |
| interrupts = <0x00 0x164 0x04>; | |
| clocks = <0x1d 0x76 0x1d 0x73 0x1d 0x75 0x1d 0x7e 0x1d 0x78 0x1c 0x00 0x1d 0x7d 0x1d 0x7c>; | |
| vccq2-supply = <0x15e>; | |
| vdd-hba-fixed-regulator; | |
| limit-phy-submode = <0x00>; | |
| reset-gpios = <0x1f 0x71 0x01>; | |
| compatible = "qcom,ufshc"; | |
| qcom,ufs-bus-bw,num-paths = <0x02>; | |
| qcom,ufs-bus-bw,num-cases = <0x0c>; | |
| status = "disabled"; | |
| phys = <0x3b>; | |
| nvmem-cell-names = "boot_conf"; | |
| vdd-hba-supply = <0x188>; | |
| reg = <0x4804000 0x3000 0x4810000 0x8000>; | |
| phandle = <0x3a>; | |
| vccq2-max-microamp = <0x927c0>; | |
| reset-names = "rst"; | |
| vcc-supply = <0x166>; | |
| qcom,ufs-bus-bw,vectors-KBps = <0x7b 0x200 0x00 0x00 0x01 0x2f5 0x00 0x00 0x7b 0x200 0x39a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1f334 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x247ae 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x74a000 0x00 0x01 0x2f5 0x4b000 0x00>; | |
| qcom,vddp-ref-clk-supply = <0x161>; | |
| qcom,iommu-dma = "fastmap"; | |
| qos0 { | |
| perf; | |
| vote = <0x2c>; | |
| }; | |
| qos1 { | |
| vote = <0x2c>; | |
| }; | |
| }; | |
| cti@8B5B000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-dlct-cti2"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8b5b000 0x1000>; | |
| phandle = <0x1ca>; | |
| }; | |
| cti@8010000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti0"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8010000 0x1000>; | |
| phandle = <0xe3>; | |
| }; | |
| syscon@447d200 { | |
| compatible = "syscon"; | |
| reg = <0x447d200 0x100>; | |
| phandle = <0x5e>; | |
| }; | |
| funnel@8a24000 { | |
| coresight-name = "coresight-funnel-lpass-lpi"; | |
| compatible = "arm,coresight-static-funnel"; | |
| phandle = <0x1b5>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xcf>; | |
| phandle = <0x8e>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0xd0>; | |
| phandle = <0x90>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xd1>; | |
| phandle = <0xd5>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@1445004 { | |
| regulator-name = "gcc_ufs_phy_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x1445004 0x04>; | |
| phandle = <0x188>; | |
| }; | |
| qcom,gdsc@147d060 { | |
| qcom,no-status-check-on-disable; | |
| regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x147d060 0x04>; | |
| phandle = <0x18b>; | |
| }; | |
| qcom,gpi-dma@4a00000 { | |
| iommus = <0x29 0xf6 0x00>; | |
| qcom,gpi-ee-offset = <0x10000>; | |
| qcom,gpii-mask = <0x0f>; | |
| reg-names = "gpi-top"; | |
| interrupts = <0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x158 0x04>; | |
| qcom,ev-factor = <0x02>; | |
| compatible = "qcom,gpi-dma"; | |
| status = "ok"; | |
| qcom,iommu-dma-addr-pool = <0x100000 0x100000>; | |
| qcom,max-num-gpii = <0x0a>; | |
| reg = <0x4a00000 0x60000>; | |
| phandle = <0xf4>; | |
| #dma-cells = <0x05>; | |
| }; | |
| funnel@9800000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-funnel-apss0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9800000 0x1000>; | |
| phandle = <0x1ac>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xa8>; | |
| phandle = <0x9c>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0xaf>; | |
| phandle = <0xa3>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0xad>; | |
| phandle = <0xa1>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0xab>; | |
| phandle = <0x9f>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xa9>; | |
| phandle = <0x9d>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xae>; | |
| phandle = <0xa2>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xac>; | |
| phandle = <0xa0>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xaa>; | |
| phandle = <0x9e>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xa7>; | |
| phandle = <0xb7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@9740000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| cpu = <0x12>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm7"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9740000 0x1000>; | |
| phandle = <0x1a8>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa3>; | |
| phandle = <0xaf>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ssphy@1615000 { | |
| qcom,vdd-voltage-level = <0x00 0xe1d48 0xecd10>; | |
| clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "cfg_ahb_clk"; | |
| reg-names = "qmp_phy_base", "vls_clamp_reg"; | |
| qcom,core-voltage-level = <0x00 0x1b7740 0x1b7740>; | |
| resets = <0x1d 0x0a 0x1d 0x09>; | |
| clocks = <0x1d 0x88 0x1d 0x89 0x1c 0x00 0x1d 0x95>; | |
| vdd-supply = <0x80>; | |
| qcom,qmp-phy-reg-offset = <0xd74 0xcd8 0xcdc 0xc04 0xc00 0xc08 0xa00>; | |
| compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; | |
| reg = <0x1615000 0x1000 0x3cb244 0x04>; | |
| phandle = <0x7f>; | |
| reset-names = "phy_reset", "phy_phy_reset"; | |
| qcom,qmp-phy-init-seq = <0xac 0x14 0x34 0x08 0x174 0x30 0x3c 0x06 0xb4 0x00 0xb8 0x08 0x70 0x0f 0x19c 0x01 0x178 0x00 0xd0 0x82 0xdc 0x55 0xe0 0x55 0xe4 0x03 0x78 0x0b 0x84 0x16 0x90 0x28 0x108 0x80 0x10c 0x00 0x184 0x0a 0x4c 0x15 0x50 0x34 0x54 0x00 0xc8 0x00 0x18c 0x00 0xcc 0x00 0x128 0x00 0x0c 0x0a 0x10 0x01 0x1c 0x31 0x20 0x01 0x14 0x00 0x18 0x00 0x24 0xde 0x28 0x07 0x48 0x0f 0x194 0x06 0x100 0x80 0xa8 0x01 0x430 0x0b 0x830 0x0b 0x444 0x00 0x844 0x00 0x43c 0x00 0x83c 0x00 0x440 0x00 0x840 0x00 0x408 0x0a 0x808 0x0a 0x414 0x06 0x814 0x06 0x434 0x75 0x834 0x75 0x4d4 0x02 0x8d4 0x02 0x4d8 0x4e 0x8d8 0x4e 0x4dc 0x18 0x8dc 0x18 0x4f8 0x77 0x8f8 0x77 0x4fc 0x80 0x8fc 0x80 0x4c0 0x0a 0x8c0 0x0a 0x504 0x03 0x904 0x03 0x50c 0x16 0x90c 0x16 0x500 0x00 0x900 0x00 0x564 0x00 0x964 0x00 0x260 0x10 0x660 0x10 0x2a4 0x12 0x6a4 0x12 0x28c 0xc6 0x68c 0xc6 0x244 0x00 0x644 0x00 0x248 0x00 0x648 0x00 0xc0c 0x9f 0xc24 0x17 0xc28 0x0f 0xcc8 0x83 0xcc4 0x02 0xccc 0x09 0xcd0 0xa2 0xcd4 0x85 0xc80 0xd1 0xc84 0x1f 0xc88 0x47 0xcb8 0x75 0xcbc 0x13 0xcb0 0x86 0xca0 0x04 0xc8c 0x44 0xc70 0xe7 0xc74 0x03 0xc78 0x40 0xc7c 0x00 0xdd8 0x88>; | |
| core-supply = <0x81>; | |
| }; | |
| cti@8941000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-isdb-gpu"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x8941000 0x1000>; | |
| phandle = <0x1c6>; | |
| }; | |
| tpda@98c0000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpda-llm-silver"; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x48>; | |
| reg = <0x98c0000 0x1000>; | |
| phandle = <0x1af>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb5>; | |
| phandle = <0xa5>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb4>; | |
| phandle = <0xb9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| mem_dump { | |
| memory-region = <0x36>; | |
| compatible = "qcom,mem-dump"; | |
| c102_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x06>; | |
| }; | |
| l1_icache101 { | |
| qcom,dump-size = <0x12000>; | |
| qcom,dump-id = <0x65>; | |
| }; | |
| l1_dcache103 { | |
| qcom,dump-size = <0x12000>; | |
| qcom,dump-id = <0x87>; | |
| }; | |
| l1_icache3 { | |
| qcom,dump-size = <0x9040>; | |
| qcom,dump-id = <0x63>; | |
| }; | |
| l1_dcache101 { | |
| qcom,dump-size = <0x12000>; | |
| qcom,dump-id = <0x85>; | |
| }; | |
| c0_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x00>; | |
| }; | |
| l1_icache1 { | |
| qcom,dump-size = <0x9040>; | |
| qcom,dump-id = <0x61>; | |
| }; | |
| l1_dcache2 { | |
| qcom,dump-size = <0x9040>; | |
| qcom,dump-id = <0x82>; | |
| }; | |
| tmc_etf { | |
| qcom,dump-size = <0x8000>; | |
| qcom,dump-id = <0xf0>; | |
| }; | |
| c2_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x02>; | |
| }; | |
| l2_tlb103 { | |
| qcom,dump-size = <0x4800>; | |
| qcom,dump-id = <0x127>; | |
| }; | |
| l2_tlb2 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x122>; | |
| }; | |
| fcm { | |
| qcom,dump-size = <0x8400>; | |
| qcom,dump-id = <0xee>; | |
| }; | |
| etf_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x101>; | |
| }; | |
| rpm_sw { | |
| qcom,dump-size = <0x28000>; | |
| qcom,dump-id = <0xea>; | |
| }; | |
| l1_dcache0 { | |
| qcom,dump-size = <0x9040>; | |
| qcom,dump-id = <0x80>; | |
| }; | |
| c101_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x05>; | |
| }; | |
| l2_tlb101 { | |
| qcom,dump-size = <0x4800>; | |
| qcom,dump-id = <0x125>; | |
| }; | |
| l2_tlb0 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x120>; | |
| }; | |
| l1_icache102 { | |
| qcom,dump-size = <0x12000>; | |
| qcom,dump-id = <0x66>; | |
| }; | |
| etr_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x100>; | |
| }; | |
| pmic { | |
| qcom,dump-size = <0x40000>; | |
| qcom,dump-id = <0xe4>; | |
| }; | |
| l1_icache100 { | |
| qcom,dump-size = <0x12000>; | |
| qcom,dump-id = <0x64>; | |
| }; | |
| c103_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x07>; | |
| }; | |
| l1_dcache102 { | |
| qcom,dump-size = <0x12000>; | |
| qcom,dump-id = <0x86>; | |
| }; | |
| l1_icache2 { | |
| qcom,dump-size = <0x9040>; | |
| qcom,dump-id = <0x62>; | |
| }; | |
| l1_dcache100 { | |
| qcom,dump-size = <0x12000>; | |
| qcom,dump-id = <0x84>; | |
| }; | |
| l1_dcache3 { | |
| qcom,dump-size = <0x9040>; | |
| qcom,dump-id = <0x83>; | |
| }; | |
| c1_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x01>; | |
| }; | |
| c_scandump { | |
| qcom,dump-size = <0x40000>; | |
| qcom,dump-id = <0xeb>; | |
| }; | |
| l1_icache0 { | |
| qcom,dump-size = <0x9040>; | |
| qcom,dump-id = <0x60>; | |
| }; | |
| misc_data { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0xe8>; | |
| }; | |
| l2_tlb3 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x123>; | |
| }; | |
| l1_dcache1 { | |
| qcom,dump-size = <0x9040>; | |
| qcom,dump-id = <0x81>; | |
| }; | |
| c100_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x04>; | |
| }; | |
| l2_tlb102 { | |
| qcom,dump-size = <0x4800>; | |
| qcom,dump-id = <0x126>; | |
| }; | |
| l2_tlb1 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x121>; | |
| }; | |
| c3_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x03>; | |
| }; | |
| l1_icache103 { | |
| qcom,dump-size = <0x12000>; | |
| qcom,dump-id = <0x67>; | |
| }; | |
| l2_tlb100 { | |
| qcom,dump-size = <0x4800>; | |
| qcom,dump-id = <0x124>; | |
| }; | |
| }; | |
| qcom,secure-buffer { | |
| compatible = "qcom,secure-buffer"; | |
| }; | |
| cti@89A5000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-wcss-cti1"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x89a5000 0x1000>; | |
| phandle = <0x1c1>; | |
| }; | |
| vibra_vcc { | |
| regulator-max-microvolt = <0x325aa0>; | |
| pinctrl-names = "default"; | |
| gpio = <0x1f 0x60 0x00>; | |
| pinctrl-0 = <0x2f3>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-name = "vibra_vcc"; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x2f4>; | |
| }; | |
| gpio_keys { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x2eb 0x2f1>; | |
| label = "gpio-keys"; | |
| compatible = "gpio-keys"; | |
| vol_up { | |
| linux,can-disable; | |
| label = "volume_up"; | |
| linux,input-type = <0x01>; | |
| gpio-key,wakeup; | |
| linux,code = <0x73>; | |
| debounce-interval = <0x0f>; | |
| gpios = <0x17a 0x05 0x01>; | |
| }; | |
| }; | |
| qcom,cpu-hotplug { | |
| compatible = "qcom,cpu-hotplug"; | |
| cpu4-hotplug { | |
| qcom,cpu = <0x0f>; | |
| qcom,cdev-alias = "cpu-hotplug4"; | |
| phandle = <0x232>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu6-hotplug { | |
| qcom,cpu = <0x11>; | |
| qcom,cdev-alias = "cpu-hotplug6"; | |
| phandle = <0x234>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu1-hotplug { | |
| qcom,cpu = <0x0c>; | |
| qcom,cdev-alias = "cpu-hotplug1"; | |
| phandle = <0x22f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu3-hotplug { | |
| qcom,cpu = <0x0e>; | |
| qcom,cdev-alias = "cpu-hotplug3"; | |
| phandle = <0x231>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu5-hotplug { | |
| qcom,cpu = <0x10>; | |
| qcom,cdev-alias = "cpu-hotplug5"; | |
| phandle = <0x233>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu7-hotplug { | |
| qcom,cpu = <0x12>; | |
| qcom,cdev-alias = "cpu-hotplug7"; | |
| phandle = <0x235>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu0-hotplug { | |
| qcom,cpu = <0x0b>; | |
| qcom,cdev-alias = "cpu-hotplug0"; | |
| phandle = <0x22e>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu2-hotplug { | |
| qcom,cpu = <0x0d>; | |
| qcom,cdev-alias = "cpu-hotplug2"; | |
| phandle = <0x230>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| modem_etm0 { | |
| qcom,inst-id = <0x02>; | |
| coresight-name = "coresight-modem-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| phandle = <0x1a0>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9b>; | |
| phandle = <0xde>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm_fastrpc { | |
| qcom,fastrpc-adsp-audio-pdr; | |
| qcom,rpc-latency-us = <0x263>; | |
| compatible = "qcom,msm-fastrpc-compute"; | |
| qcom,fastrpc-adsp-sensors-pdr; | |
| qcom,adsp-remoteheap-vmid = <0x16 0x25>; | |
| qcom,msm_fastrpc_compute_cb3 { | |
| iommus = <0x29 0xc03 0x00>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb1 { | |
| iommus = <0x29 0xc01 0x00>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb13 { | |
| iommus = <0x29 0x1c6 0x00>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb6 { | |
| iommus = <0x29 0xc06 0x00>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb11 { | |
| iommus = <0x29 0x1c4 0x00>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb4 { | |
| iommus = <0x29 0xc04 0x00>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb2 { | |
| iommus = <0x29 0xc02 0x00>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb9 { | |
| iommus = <0x29 0xc09 0x00>; | |
| qcom,secure-context-bank; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb14 { | |
| iommus = <0x29 0x1c7 0x00>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb12 { | |
| iommus = <0x29 0x1c5 0x00>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb5 { | |
| iommus = <0x29 0xc05 0x00>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb10 { | |
| iommus = <0x29 0x1c3 0x00>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| }; | |
| replicator@8046000 { | |
| arm,primecell-periphid = <0xbb909>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "replicator-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-replicator-qdss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8046000 0x1000>; | |
| phandle = <0x1bb>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe7>; | |
| phandle = <0xe4>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe6>; | |
| phandle = <0xe8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@8a01000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-mapss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8a01000 0x1000>; | |
| phandle = <0x19e>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x99>; | |
| phandle = <0xbc>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interconnect { | |
| clock-names = "bus", "bus_a"; | |
| clocks = <0x1c 0x6a 0x1c 0x6b>; | |
| #interconnect-cells = <0x01>; | |
| compatible = "qcom,bengal-clk_virt"; | |
| phandle = <0xf0>; | |
| qcom,keepalive; | |
| }; | |
| rx_npl_clk { | |
| qcom,codec-ext-clk-src = <0x06>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x32a>; | |
| qcom,codec-lpass-clk-id = <0x30f>; | |
| qcom,codec-lpass-ext-clk-freq = <0x1588800>; | |
| }; | |
| ipa_smmu_ap { | |
| iommus = <0x29 0x140 0x00>; | |
| qcom,additional-mapping = <0xc123000 0xc123000 0x2000>; | |
| qcom,iommu-geometry = <0x00 0xb0000000>; | |
| compatible = "qcom,ipa-smmu-ap-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>; | |
| phandle = <0x184>; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| clock-controller@5f00000 { | |
| #reset-cells = <0x01>; | |
| clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "gcc_disp_gpll0_div_clk_src"; | |
| reg-names = "cc_base"; | |
| clocks = <0x1c 0x00 0x1c 0x01 0x5b 0x1d 0x3e>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,sm6115-dispcc", "syscon"; | |
| reg = <0x5f00000 0x20000>; | |
| phandle = <0x5c>; | |
| vdd_cx-supply = <0x32>; | |
| }; | |
| qcom,rpmcc { | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,rpmcc-khaje"; | |
| phandle = <0x1c>; | |
| }; | |
| qcom,bwmon-ddr@01b8e200 { | |
| reg-names = "base", "global_base"; | |
| interrupts = <0x00 0x1a5 0x04>; | |
| compatible = "qcom,bwmon4"; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,mport = <0x00>; | |
| qcom,count-unit = <0x10000>; | |
| reg = <0x1b8e300 0x100 0x1b8e200 0x100>; | |
| phandle = <0x181>; | |
| qcom,target-dev = <0x74>; | |
| }; | |
| etm@9040000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| cpu = <0x0b>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9040000 0x1000>; | |
| phandle = <0x1a1>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9c>; | |
| phandle = <0xa8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@8870000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| qcom,hw-enable-check; | |
| coresight-name = "coresight-tpdm-dcc"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8870000 0x1000>; | |
| phandle = <0x199>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x94>; | |
| phandle = <0xca>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cluster-device2 { | |
| power-domains = <0x15>; | |
| compatible = "qcom,lpm-cluster-dev"; | |
| }; | |
| jtagmm@9140000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x0c>; | |
| reg = <0x9140000 0x1000>; | |
| phandle = <0x13c>; | |
| }; | |
| kgsl-smmu@0x59a0000 { | |
| #global-interrupts = <0x01>; | |
| #address-cells = <0x01>; | |
| clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "gpu_cc_hlos1_vote_gpu_smmu_clk"; | |
| reg-names = "base", "tcu-base"; | |
| qcom,num-smr-override = <0x04>; | |
| interrupts = <0x00 0xa3 0x04 0x00 0xa7 0x04 0x00 0xa8 0x04 0x00 0xa9 0x04 0x00 0xaa 0x04 0x00 0xab 0x04 0x00 0xac 0x04 0x00 0xad 0x04 0x00 0xae 0x04>; | |
| clocks = <0x1d 0x4c 0x1d 0x4d 0x5d 0x04 0x5d 0x10>; | |
| qcom,actlr = <0x00 0x3ff 0x30b>; | |
| #size-cells = <0x01>; | |
| qcom,skip-init; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0xe9>; | |
| qcom,use-3-lvl-tables; | |
| #iommu-cells = <0x02>; | |
| compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; | |
| ranges; | |
| status = "okay"; | |
| reg = <0x59a0000 0x10000 0x59c2000 0x20>; | |
| phandle = <0x1db>; | |
| qcom,num-context-banks-override = <0x05>; | |
| qcom,testbus-version = <0x01>; | |
| qcom,dynamic; | |
| qcom,no-dynamic-asid; | |
| gfx_0_tbu@0x59c5000 { | |
| reg-names = "base", "status-reg"; | |
| qcom,stream-id-range = <0x00 0x400>; | |
| qcom,iova-width = <0x24>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x59c5000 0x1000 0x59c2200 0x08>; | |
| phandle = <0x1dc>; | |
| }; | |
| }; | |
| cxip-cdev@3ed000 { | |
| qcom,bypass-client-list = <0x1004 0x4004 0x6004 0xc004 0xc008>; | |
| compatible = "qcom,cxip-lm-cooling-device"; | |
| qcom,thermal-client-offset = <0x8000>; | |
| reg = <0x3ed000 0xc00c>; | |
| phandle = <0x3f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| tpdm@9860000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-apss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9860000 0x1000>; | |
| phandle = <0x1ab>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa6>; | |
| phandle = <0xb3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| modem_rfxe { | |
| qcom,dummy-source; | |
| coresight-name = "coresight-modem-rfxe"; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x194>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8d>; | |
| phandle = <0xdc>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| iommu_test_device { | |
| compatible = "qcom,iommu-debug-test"; | |
| usecase0_apps { | |
| iommus = <0x29 0x1e1 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| }; | |
| usecase4_apps_secure { | |
| iommus = <0x29 0x1e1 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| usecase2_apps_atomic { | |
| iommus = <0x29 0x1e1 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| usecase3_apps_dma { | |
| iommus = <0x29 0x1e1 0x00>; | |
| dma-coherent; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| }; | |
| usecase1_apps_fastmap { | |
| iommus = <0x29 0x1e1 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| }; | |
| qcom,msm-adsp-loader { | |
| qcom,adsp-state = <0x00>; | |
| nvmem-cells = <0x64>; | |
| adsp-fw-names = "adsp2"; | |
| compatible = "qcom,adsp-loader"; | |
| status = "ok"; | |
| nvmem-cell-names = "adsp_variant"; | |
| phandle = <0x266>; | |
| qcom,rproc-handle = <0x167>; | |
| adsp-fw-bit-values = <0x01>; | |
| }; | |
| syscon@5991540 { | |
| compatible = "syscon"; | |
| reg = <0x5991540 0x04>; | |
| phandle = <0x7a>; | |
| }; | |
| rx_core_clk { | |
| qcom,codec-ext-clk-src = <0x05>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x329>; | |
| qcom,codec-lpass-clk-id = <0x30e>; | |
| qcom,codec-lpass-ext-clk-freq = <0x1588800>; | |
| }; | |
| cti@801e000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti14"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x801e000 0x1000>; | |
| phandle = <0x1d1>; | |
| }; | |
| cx_ipeak@3ed000 { | |
| compatible = "qcom,cx-ipeak-v2"; | |
| reg = <0x3ed000 0xe008>; | |
| phandle = <0x17d>; | |
| }; | |
| tmc@8047000 { | |
| arm,primecell-periphid = <0xbb961>; | |
| coresight-ctis = <0xe3>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tmc-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tmc-etf"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8047000 0x1000>; | |
| phandle = <0x1ba>; | |
| coresight-csr = <0x88>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe5>; | |
| phandle = <0xe0>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe4>; | |
| phandle = <0xe7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@9640000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| cpu = <0x11>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm6"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9640000 0x1000>; | |
| phandle = <0x1a7>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa2>; | |
| phandle = <0xae>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| audio_etm0 { | |
| qcom,inst-id = <0x05>; | |
| coresight-name = "coresight-audio-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| phandle = <0x195>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8e>; | |
| phandle = <0xcf>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@801b000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti11"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x801b000 0x1000>; | |
| phandle = <0x1ce>; | |
| }; | |
| tpdm@884c000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-prng"; | |
| compatible = "arm,primecell"; | |
| reg = <0x884c000 0x1000>; | |
| phandle = <0x19a>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x95>; | |
| phandle = <0xcb>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| jtagmm@9740000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x12>; | |
| reg = <0x9740000 0x1000>; | |
| phandle = <0x142>; | |
| }; | |
| tpdm@8940000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-gpu"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x8940000 0x1000>; | |
| phandle = <0x193>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8c>; | |
| phandle = <0xbe>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| timer { | |
| interrupts = <0x01 0x01 0xf08 0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x00 0xf08>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv8-timer"; | |
| qcom,erratum-858921; | |
| }; | |
| qcom,smp2p-cdsp { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x00 0x107 0x01>; | |
| qcom,remote-pid = <0x05>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x31 0x1e>; | |
| qcom,smem = <0x5e 0x1b0>; | |
| qcom,smp2p-rdbg5-out { | |
| qcom,entry-name = "rdbg"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x116>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x34>; | |
| interrupt-controller; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x35>; | |
| }; | |
| qcom,smp2p-rdbg5-in { | |
| qcom,entry-name = "rdbg"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x117>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x309>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-name = "lab"; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| reg = <0x01>; | |
| qcom,supply-min-voltage = "", "Us"; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "ibb"; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| reg = <0x02>; | |
| qcom,supply-min-voltage = "", "Us"; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-enable-load = <0xf230>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| }; | |
| }; | |
| interconnect@1900000 { | |
| clock-names = "bus", "bus_a"; | |
| clocks = <0x1c 0x1c 0x1c 0x1d>; | |
| #interconnect-cells = <0x01>; | |
| compatible = "qcom,bengal-config_noc"; | |
| reg = <0x1900000 0x6200>; | |
| phandle = <0x27>; | |
| qcom,keepalive; | |
| }; | |
| cti@98E0000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-apss-cti0"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x98e0000 0x1000>; | |
| phandle = <0x1be>; | |
| }; | |
| qcom,rmnet-ipa { | |
| qcom,ipa-napi-enable; | |
| qcom,rmnet-ipa-ssr; | |
| qcom,ipa-advertise-sg-support; | |
| compatible = "qcom,rmnet-ipa3"; | |
| status = "disabled"; | |
| qcom,ipa-platform-type-msm; | |
| }; | |
| cluster-device0 { | |
| power-domains = <0x13>; | |
| compatible = "qcom,lpm-cluster-dev"; | |
| }; | |
| qcom,cpufreq-cdev { | |
| compatible = "qcom,cpufreq-cdev"; | |
| cpu-cluster0 { | |
| qcom,cpus = <0x0b 0x0c 0x0d 0x0e>; | |
| }; | |
| cpu-cluster1 { | |
| qcom,cpus = <0x0f 0x10 0x11 0x12>; | |
| }; | |
| }; | |
| ssusb@4e00000 { | |
| #address-cells = <0x01>; | |
| interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; | |
| qcom,interconnect-values-nom = <0x3a980 0xaae60 0x00 0x960 0x00 0x9c40>; | |
| clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "sleep_clk", "utmi_clk"; | |
| interconnects = <0x28 0x1c 0x26 0x200 0x28 0x1c 0x27 0x218 0x26 0x00 0x27 0x22e>; | |
| reg-names = "core_base"; | |
| resets = <0x1d 0x04>; | |
| clocks = <0x1d 0x80 0x1d 0x74 0x1d 0x38 0x1d 0x85 0x1d 0x82>; | |
| extcon = <0x2f0 0x14f>; | |
| #size-cells = <0x01>; | |
| dpdm-supply = <0x7e>; | |
| interrupts-extended = <0x01 0x00 0x12e 0x04 0x59 0x0c 0x04 0x59 0x5a 0x04>; | |
| qcom,core-clk-rate-hs = <0x3f940ab>; | |
| qcom,num-gsi-evt-buffs = <0x03>; | |
| compatible = "qcom,dwc-usb3-msm"; | |
| ranges; | |
| interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; | |
| qcom,core-clk-rate = <0x7f28155>; | |
| reg = <0x4e00000 0x100000>; | |
| phandle = <0x18d>; | |
| qcom,interconnect-values-svs = <0x3a980 0xaae60 0x00 0x960 0x00 0x9c40>; | |
| reset-names = "core_reset"; | |
| USB3_GDSC-supply = <0x7d>; | |
| qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>; | |
| dwc3@4e00000 { | |
| iommus = <0x29 0x120 0x00>; | |
| snps,hird-threshold = [10]; | |
| tx-fifo-resize; | |
| snps,dis_enblslpm_quirk; | |
| snps,usb3_lpm_capable; | |
| usb-role-switch; | |
| snps,usb3-u1u2-disable; | |
| snps,dis_u2_susphy_quirk; | |
| interrupts = <0x00 0xff 0x04>; | |
| interrupt-parent = <0x01>; | |
| compatible = "snps,dwc3"; | |
| snps,disable-clk-gating; | |
| snps,has-lpm-erratum; | |
| qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>; | |
| reg = <0x4e00000 0xcd00>; | |
| usb-phy = <0x7e 0x7f>; | |
| dr_mode = "otg"; | |
| maximum-speed = "super-speed"; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| }; | |
| sdhc2-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x39>; | |
| opp-100000000 { | |
| opp-peak-kBps = <0x3d090 0x208c8>; | |
| opp-hz = <0x00 0x5f5e100>; | |
| opp-avg-kBps = <0xc350 0x00>; | |
| }; | |
| opp-202000000 { | |
| opp-peak-kBps = <0xc3500 0x493e0>; | |
| opp-hz = <0x00 0xc0a4680>; | |
| opp-avg-kBps = <0x19640 0x00>; | |
| }; | |
| }; | |
| va_mini_dump { | |
| memory-region = <0x60>; | |
| compatible = "qcom,va-minidump"; | |
| status = "ok"; | |
| }; | |
| cti@8833000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-mss-q6"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8833000 0x1000>; | |
| phandle = <0x1c5>; | |
| }; | |
| qfprom@1b40000 { | |
| #address-cells = <0x01>; | |
| read-only; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qfprom"; | |
| ranges; | |
| reg = <0x1b40000 0x7000>; | |
| phandle = <0x174>; | |
| gpu_speed_bin@6006 { | |
| bits = <0x05 0x08>; | |
| reg = <0x6006 0x02>; | |
| phandle = <0x175>; | |
| }; | |
| feat_conf10@602c { | |
| reg = <0x602c 0x04>; | |
| phandle = <0x66>; | |
| }; | |
| gpu_gaming_bin@602d { | |
| bits = <0x05 0x01>; | |
| reg = <0x602d 0x01>; | |
| phandle = <0x176>; | |
| }; | |
| adsp_variant@6011 { | |
| bits = <0x03 0x01>; | |
| reg = <0x6011 0x01>; | |
| phandle = <0x64>; | |
| }; | |
| stm@20f0 { | |
| reg = <0x20f0 0x04>; | |
| phandle = <0x89>; | |
| }; | |
| boot_config@6070 { | |
| reg = <0x6070 0x04>; | |
| phandle = <0x37>; | |
| }; | |
| feat_conf5@6018 { | |
| reg = <0x6018 0x04>; | |
| phandle = <0x65>; | |
| }; | |
| }; | |
| qcom,gdsc@147d07c { | |
| qcom,no-status-check-on-disable; | |
| regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x147d07c 0x04>; | |
| phandle = <0xee>; | |
| }; | |
| qcom,gdsc@1458004 { | |
| regulator-name = "gcc_camss_top_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x1458004 0x04>; | |
| phandle = <0x187>; | |
| }; | |
| qcom,mem-buf-msgq { | |
| compatible = "qcom,mem-buf-msgq"; | |
| }; | |
| funnel@8944000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-funnel-gpu"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x8944000 0x1000>; | |
| phandle = <0x1b2>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xbe>; | |
| phandle = <0x8c>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xbd>; | |
| phandle = <0xc7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,spmi@1c40000 { | |
| #address-cells = <0x01>; | |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
| qcom,channel = <0x00>; | |
| cell-index = <0x00>; | |
| #size-cells = <0x01>; | |
| interrupts-extended = <0x59 0x56 0x04>; | |
| compatible = "qcom,spmi-pmic-arb"; | |
| #interrupt-cells = <0x04>; | |
| interrupt-names = "periph_irq"; | |
| reg = <0x1c40000 0x1100 0x1e00000 0x2000000 0x3e00000 0x100000 0x3f00000 0xa0000 0x1c0a000 0x26000>; | |
| phandle = <0x177>; | |
| qcom,ee = <0x00>; | |
| interrupt-controller; | |
| qcom,pm6125@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x00 0x00>; | |
| adc_tm@3400 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,spmi-adc-tm5-iio"; | |
| reg = <0x3400>; | |
| phandle = <0x58>; | |
| camera_flash_therm { | |
| io-channels = <0x6e 0x52>; | |
| reg = <0x00>; | |
| }; | |
| emmc_ufs_therm { | |
| io-channels = <0x6e 0x53>; | |
| reg = <0x01>; | |
| }; | |
| }; | |
| qcom,power-on@800 { | |
| interrupts = <0x00 0x08 0x00 0x03 0x00 0x08 0x01 0x03>; | |
| qcom,pon-dbc-delay = <0x3d09>; | |
| compatible = "qcom,qpnp-power-on"; | |
| qcom,system-reset; | |
| interrupt-names = "kpdpwr", "resin"; | |
| reg = <0x800>; | |
| qcom,kpdpwr-sw-debounce; | |
| qcom,store-hard-reset-reason; | |
| qcom,pon_1 { | |
| qcom,pull-up = <0x01>; | |
| qcom,pon-type = <0x00>; | |
| linux,code = <0x74>; | |
| }; | |
| qcom,pon_2 { | |
| qcom,pull-up = <0x01>; | |
| qcom,pon-type = <0x01>; | |
| linux,code = <0x72>; | |
| }; | |
| }; | |
| qcom,misc@900 { | |
| compatible = "qcom,qpnp-misc"; | |
| reg = <0x900>; | |
| phandle = <0x179>; | |
| }; | |
| vadc@3100 { | |
| io-channel-ranges; | |
| pinctrl-names = "default"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x6c 0x6d 0x2ea>; | |
| interrupts = <0x00 0x31 0x00 0x01>; | |
| #io-channel-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-adc5"; | |
| qcom,adc-vdd-reference = <0x753>; | |
| interrupt-names = "eoc-int-en-set"; | |
| reg = <0x3100>; | |
| phandle = <0x6e>; | |
| xo_therm { | |
| label = "xo_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4c>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| ref_gnd { | |
| label = "ref_gnd"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x00>; | |
| }; | |
| vph_pwr { | |
| label = "vph_pwr"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x83>; | |
| }; | |
| rf_pa1_therm { | |
| label = "rf_pa1_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x55>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| camera_flash_therm { | |
| label = "camera_flash_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x52>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| vref_1p25 { | |
| label = "vref_1p25"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x01>; | |
| }; | |
| die_temp { | |
| label = "die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x06>; | |
| }; | |
| pa_therm0 { | |
| label = "pa_therm0"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| quiet_therm { | |
| label = "quiet_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4e>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| emmc_ufs_therm { | |
| label = "emmc_ufs_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x53>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| }; | |
| pinctrl@c000 { | |
| gpio-controller; | |
| compatible = "qcom,pm6125-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0xc000>; | |
| phandle = <0x17a>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| rf_pa1_therm { | |
| rf_pa1_therm_default { | |
| pins = "gpio7"; | |
| bias-high-impedance; | |
| phandle = <0x2ea>; | |
| }; | |
| }; | |
| camera_therm { | |
| camera_therm_default { | |
| pins = "gpio3"; | |
| bias-high-impedance; | |
| phandle = <0x6c>; | |
| }; | |
| }; | |
| lcd_backlight_ctrl { | |
| lcd_backlight_ctrl_default { | |
| input-disable; | |
| function = "func1"; | |
| pins = "gpio8"; | |
| qcom,drive-strength = <0x03>; | |
| bias-disable; | |
| phandle = <0x313>; | |
| power-source = <0x00>; | |
| output-low; | |
| }; | |
| }; | |
| key_vol_up { | |
| key_vol_up_default { | |
| function = "normal"; | |
| pins = "gpio5"; | |
| phandle = <0x2eb>; | |
| bias-pull-up; | |
| power-source = <0x00>; | |
| input-enable; | |
| }; | |
| }; | |
| emmc_therm { | |
| emmc_therm_default { | |
| pins = "gpio4"; | |
| bias-high-impedance; | |
| phandle = <0x6d>; | |
| }; | |
| }; | |
| }; | |
| qcom,pm6125_rtc { | |
| interrupts = <0x00 0x61 0x01 0x00>; | |
| compatible = "qcom,pm8941-rtc"; | |
| phandle = <0x17b>; | |
| }; | |
| clock-controller@5b00 { | |
| clock-output-names = "pm6125_div_clk1"; | |
| clock-names = "xo"; | |
| assigned-clocks = <0x6f 0x01>; | |
| assigned-clock-rates = <0x927c00>; | |
| clocks = <0x1c 0x00>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,spmi-clkdiv"; | |
| qcom,num-clkdivs = <0x01>; | |
| reg = <0x5b00>; | |
| phandle = <0x6f>; | |
| }; | |
| adc_tm@3500 { | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x35 0x00 0x01>; | |
| #size-cells = <0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,spmi-adc-tm5"; | |
| interrupt-names = "pm-adc-tm5"; | |
| reg = <0x3500>; | |
| phandle = <0x57>; | |
| xo_therm { | |
| io-channels = <0x6e 0x4c>; | |
| qcom,ratiometric; | |
| reg = <0x02>; | |
| qcom,hw-settle-time-us = <0xc8>; | |
| }; | |
| rf_pa1_therm { | |
| io-channels = <0x6e 0x55>; | |
| qcom,ratiometric; | |
| reg = <0x03>; | |
| qcom,hw-settle-time-us = <0xc8>; | |
| }; | |
| pa_therm0 { | |
| io-channels = <0x6e 0x4d>; | |
| qcom,ratiometric; | |
| reg = <0x00>; | |
| qcom,hw-settle-time-us = <0xc8>; | |
| }; | |
| quiet_therm { | |
| io-channels = <0x6e 0x4e>; | |
| qcom,ratiometric; | |
| reg = <0x01>; | |
| qcom,hw-settle-time-us = <0xc8>; | |
| }; | |
| }; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| reg = <0x100>; | |
| phandle = <0x178>; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| qcom,temperature-threshold-set = <0x01>; | |
| interrupts = <0x00 0x24 0x00 0x03>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0x2400>; | |
| phandle = <0x3c>; | |
| }; | |
| }; | |
| qcom,pm6125@1 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x01 0x00>; | |
| qcom,pwms@b300 { | |
| qcom,num-lpg-channels = <0x01>; | |
| reg-names = "lpg-base"; | |
| #pwm-cells = <0x02>; | |
| compatible = "qcom,pwm-lpg"; | |
| status = "ok"; | |
| reg = <0xb300>; | |
| phandle = <0x17c>; | |
| }; | |
| }; | |
| }; | |
| tpda@8a04000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpda-mapss"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x4c>; | |
| reg = <0x8a04000 0x1000>; | |
| phandle = <0x1b1>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xbc>; | |
| phandle = <0x99>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xbb>; | |
| phandle = <0xdb>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@9810000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-funnel-apss1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9810000 0x1000>; | |
| phandle = <0x1b0>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb7>; | |
| phandle = <0xa7>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0xb9>; | |
| phandle = <0xb4>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xba>; | |
| phandle = <0xb2>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xb8>; | |
| phandle = <0xb0>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb6>; | |
| phandle = <0xdf>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| mini_dump_mode { | |
| compatible = "qcom,minidump"; | |
| status = "ok"; | |
| }; | |
| cti@8018000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti8"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8018000 0x1000>; | |
| phandle = <0x1d9>; | |
| }; | |
| jtagmm@9040000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x0b>; | |
| reg = <0x9040000 0x1000>; | |
| phandle = <0x13b>; | |
| }; | |
| qcom,gdsc@599106c { | |
| hw-ctrl-addr = <0x7a>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| parent-supply = <0x32>; | |
| qcom,clk-dis-wait-val = <0x08>; | |
| regulator-name = "gpu_cx_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x599106c 0x04>; | |
| phandle = <0xe9>; | |
| }; | |
| clock-controller@1400000 { | |
| #reset-cells = <0x01>; | |
| clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; | |
| reg-names = "cc_base"; | |
| vdd_cx_ao-supply = <0x5a>; | |
| clocks = <0x1c 0x00 0x1c 0x01 0x5b>; | |
| #clock-cells = <0x01>; | |
| vdd_mx-supply = <0x2b>; | |
| compatible = "qcom,gcc-sm6115", "syscon"; | |
| reg = <0x1400000 0x1f0000>; | |
| phandle = <0x1d>; | |
| vdd_cx-supply = <0x32>; | |
| }; | |
| qcom,mem-buf { | |
| qcom,mem-buf-capabilities = "supplier"; | |
| compatible = "qcom,mem-buf"; | |
| qcom,vmid = <0x03>; | |
| }; | |
| funnel@8005000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-funnel-qatb"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8005000 0x1000>; | |
| phandle = <0x1b6>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xd3>; | |
| phandle = <0xc5>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0xd5>; | |
| phandle = <0xd1>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xd4>; | |
| phandle = <0xc1>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xd2>; | |
| phandle = <0xd8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@98a0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-llm-silver"; | |
| compatible = "arm,primecell"; | |
| reg = <0x98a0000 0x1000>; | |
| phandle = <0x1aa>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa5>; | |
| phandle = <0xb5>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@8015000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti5"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8015000 0x1000>; | |
| phandle = <0x1d6>; | |
| }; | |
| qcom,msm-imem@c125000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,msm-imem"; | |
| ranges = <0x00 0xc125000 0x1000>; | |
| reg = <0xc125000 0x1000>; | |
| dload_type@1c { | |
| compatible = "qcom,msm-imem-dload-type"; | |
| reg = <0x1c 0x04>; | |
| }; | |
| restart_reason@65c { | |
| compatible = "qcom,msm-imem-restart_reason"; | |
| reg = <0x65c 0x04>; | |
| }; | |
| boot_stats@6b0 { | |
| compatible = "qcom,msm-imem-boot_stats"; | |
| reg = <0x6b0 0x20>; | |
| }; | |
| pil@94c { | |
| compatible = "qcom,pil-reloc-info"; | |
| reg = <0x94c 0xc8>; | |
| }; | |
| mem_dump_table@10 { | |
| compatible = "qcom,msm-imem-mem_dump_table"; | |
| reg = <0x10 0x08>; | |
| }; | |
| diag_dload@c8 { | |
| compatible = "qcom,msm-imem-diag-dload"; | |
| reg = <0xc8 0xc8>; | |
| }; | |
| kaslr_offset@6d0 { | |
| compatible = "qcom,msm-imem-kaslr_offset"; | |
| reg = <0x6d0 0x0c>; | |
| }; | |
| }; | |
| spf_core_platform { | |
| compatible = "qcom,spf-core-platform"; | |
| phandle = <0x268>; | |
| msm_cdc_pinctrl@18 { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x262>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x263>; | |
| phandle = <0x2dc>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| pri_mi2s_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x277 0x279 0x27b 0x27d>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x276 0x278 0x27a 0x27c>; | |
| phandle = <0x33c>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| lpi_pinctrl@ac40000 { | |
| qcom,gpios-count = <0x13>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| gpio-controller; | |
| qcom,lpi-slew-offset-tbl = <0x00 0x02 0x04 0x08 0x0a 0x0c 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x14>; | |
| clocks = <0x24d 0x00>; | |
| qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000>; | |
| compatible = "qcom,lpi-pinctrl"; | |
| reg = <0xa7c0000 0x00>; | |
| phandle = <0x269>; | |
| #gpio-cells = <0x02>; | |
| qcom,slew-reg = <0xa95a000 0x00>; | |
| lpi_tdm3_sd0 { | |
| lpi_tdm3_sd0_sleep { | |
| phandle = <0x2ae>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm3_sd0_active { | |
| phandle = <0x2af>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| wsa_mclk_sleep { | |
| phandle = <0x263>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| quat_mi2s_sd1 { | |
| quat_mi2s_sd1_sleep { | |
| phandle = <0x270>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd1_active { | |
| phandle = <0x271>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd3 { | |
| quat_aux_sd3_active { | |
| phandle = <0x2bd>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd3_sleep { | |
| phandle = <0x2bc>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sck { | |
| lpi_aux1_sck_active { | |
| phandle = <0x2bf>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sck_sleep { | |
| phandle = <0x2be>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_clk_active { | |
| phandle = <0x256>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x0a>; | |
| bias-disable; | |
| slew-rate = <0x03>; | |
| }; | |
| }; | |
| lpi_i2s2_sck { | |
| lpi_i2s2_sck_sleep { | |
| phandle = <0x27e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sck_active { | |
| phandle = <0x27f>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_sd1 { | |
| lpi_aux3_sd1_active { | |
| phandle = <0x2d5>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_sd1_sleep { | |
| phandle = <0x2d4>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_ws { | |
| lpi_aux2_ws_active { | |
| phandle = <0x2c9>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux2_ws_sleep { | |
| phandle = <0x2c8>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd1 { | |
| quat_aux_sd1_active { | |
| phandle = <0x2b9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd1_sleep { | |
| phandle = <0x2b8>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_clk_sleep { | |
| phandle = <0x259>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x0a>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_ws { | |
| quat_tdm_ws_active { | |
| phandle = <0x291>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_ws_sleep { | |
| phandle = <0x290>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sd0 { | |
| lpi_aux1_sd0_active { | |
| phandle = <0x2c3>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sd0_sleep { | |
| phandle = <0x2c2>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data1_active { | |
| phandle = <0x258>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x0a>; | |
| bias-bus-hold; | |
| slew-rate = <0x03>; | |
| }; | |
| }; | |
| lpi_i2s1_ws { | |
| lpi_i2s1_ws_active { | |
| phandle = <0x279>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_ws_sleep { | |
| phandle = <0x278>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s2_sd0 { | |
| lpi_i2s2_sd0_sleep { | |
| phandle = <0x282>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd0_active { | |
| phandle = <0x283>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_sd1 { | |
| lpi_tdm2_sd1_active { | |
| phandle = <0x2a9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sd1_sleep { | |
| phandle = <0x2a8>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic01_clk_active { | |
| phandle = <0x24e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| dmic01_clk_sleep { | |
| phandle = <0x250>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| lpi_aux2_sck { | |
| lpi_aux2_sck_sleep { | |
| phandle = <0x2c6>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sck_active { | |
| phandle = <0x2c7>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_ws { | |
| lpi_tdm1_ws_active { | |
| phandle = <0x29d>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_ws_sleep { | |
| phandle = <0x29c>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_ws { | |
| quat_aux_ws_sleep { | |
| phandle = <0x2b4>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_ws_active { | |
| phandle = <0x2b5>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s3_sck { | |
| lpi_i2s3_sck_active { | |
| phandle = <0x287>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio14"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s3_sck_sleep { | |
| phandle = <0x286>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio14"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data_active { | |
| phandle = <0x257>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x0a>; | |
| bias-bus-hold; | |
| slew-rate = <0x03>; | |
| }; | |
| }; | |
| dmic23_data_sleep { | |
| phandle = <0x255>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s1_sd1 { | |
| lpi_i2s1_sd1_active { | |
| phandle = <0x27d>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sd1_sleep { | |
| phandle = <0x27c>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_sd0 { | |
| lpi_aux2_sd0_sleep { | |
| phandle = <0x2ca>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sd0_active { | |
| phandle = <0x2cb>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sck { | |
| lpi_tdm1_sck_active { | |
| phandle = <0x29b>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sck_sleep { | |
| phandle = <0x29a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data_sleep { | |
| phandle = <0x25a>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x0a>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd2 { | |
| quat_tdm_sd2_sleep { | |
| phandle = <0x296>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd2_active { | |
| phandle = <0x297>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sck { | |
| quat_tdm_sck_active { | |
| phandle = <0x28f>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_sck_sleep { | |
| phandle = <0x28e>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s3_sd0 { | |
| lpi_i2s3_sd0_active { | |
| phandle = <0x28b>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s3_sd0_sleep { | |
| phandle = <0x28a>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm3_sd1 { | |
| lpi_tdm3_sd1_active { | |
| phandle = <0x2b1>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm3_sd1_sleep { | |
| phandle = <0x2b0>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_ws { | |
| lpi_aux1_ws_active { | |
| phandle = <0x2c1>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_ws_sleep { | |
| phandle = <0x2c0>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd2 { | |
| quat_mi2s_sd2_sleep { | |
| phandle = <0x272>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd2_active { | |
| phandle = <0x273>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sck { | |
| quat_mi2s_sck_sleep { | |
| phandle = <0x26a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sck_active { | |
| phandle = <0x26b>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s3_ws { | |
| lpi_i2s3_ws_active { | |
| phandle = <0x289>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s3_ws_sleep { | |
| phandle = <0x288>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sd0 { | |
| lpi_tdm1_sd0_active { | |
| phandle = <0x29f>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sd0_sleep { | |
| phandle = <0x29e>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_ws { | |
| quat_mi2s_ws_sleep { | |
| phandle = <0x26c>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_ws_active { | |
| phandle = <0x26d>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd0 { | |
| quat_tdm_sd0_sleep { | |
| phandle = <0x292>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd0_active { | |
| phandle = <0x293>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_sck { | |
| lpi_aux3_sck_active { | |
| phandle = <0x2cf>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio14"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_sck_sleep { | |
| phandle = <0x2ce>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio14"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data1_sleep { | |
| phandle = <0x260>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x0a>; | |
| bias-bus-hold; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd0 { | |
| quat_mi2s_sd0_sleep { | |
| phandle = <0x26e>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd0_active { | |
| phandle = <0x26f>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| dmic01_data_sleep { | |
| phandle = <0x251>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_sd2 { | |
| quat_aux_sd2_active { | |
| phandle = <0x2bb>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd2_sleep { | |
| phandle = <0x2ba>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic23_data_active { | |
| phandle = <0x253>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_sck { | |
| quat_aux_sck_active { | |
| phandle = <0x2b3>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sck_sleep { | |
| phandle = <0x2b2>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sd1 { | |
| lpi_aux1_sd1_active { | |
| phandle = <0x2c5>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sd1_sleep { | |
| phandle = <0x2c4>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data1_sleep { | |
| phandle = <0x25b>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x0a>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm3_ws { | |
| lpi_tdm3_ws_sleep { | |
| phandle = <0x2ac>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm3_ws_active { | |
| phandle = <0x2ad>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s2_sd1 { | |
| lpi_i2s2_sd1_sleep { | |
| phandle = <0x284>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd1_active { | |
| phandle = <0x285>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_sd0 { | |
| lpi_aux3_sd0_active { | |
| phandle = <0x2d3>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_sd0_sleep { | |
| phandle = <0x2d2>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_sck { | |
| lpi_tdm2_sck_active { | |
| phandle = <0x2a3>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sck_sleep { | |
| phandle = <0x2a2>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd0 { | |
| quat_aux_sd0_active { | |
| phandle = <0x2b7>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd0_sleep { | |
| phandle = <0x2b6>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_clk_sleep { | |
| phandle = <0x25f>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x0a>; | |
| }; | |
| }; | |
| lpi_tdm2_sd0 { | |
| lpi_tdm2_sd0_active { | |
| phandle = <0x2a7>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sd0_sleep { | |
| phandle = <0x2a6>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_clk_active { | |
| phandle = <0x25c>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x0a>; | |
| bias-disable; | |
| slew-rate = <0x03>; | |
| }; | |
| }; | |
| lpi_aux3_ws { | |
| lpi_aux3_ws_active { | |
| phandle = <0x2d1>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_ws_sleep { | |
| phandle = <0x2d0>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| wsa_mclk_active { | |
| phandle = <0x262>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s2_ws { | |
| lpi_i2s2_ws_sleep { | |
| phandle = <0x280>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_ws_active { | |
| phandle = <0x281>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s1_sck { | |
| lpi_i2s1_sck_active { | |
| phandle = <0x277>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sck_sleep { | |
| phandle = <0x276>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data1_active { | |
| phandle = <0x25d>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x0a>; | |
| bias-bus-hold; | |
| slew-rate = <0x03>; | |
| }; | |
| }; | |
| tx_swr_data2_sleep { | |
| phandle = <0x261>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x0a>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sd1 { | |
| lpi_aux2_sd1_sleep { | |
| phandle = <0x2cc>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sd1_active { | |
| phandle = <0x2cd>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| dmic23_clk_sleep { | |
| phandle = <0x254>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| quat_tdm_sd3 { | |
| quat_tdm_sd3_sleep { | |
| phandle = <0x298>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd3_active { | |
| phandle = <0x299>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data2_active { | |
| phandle = <0x25e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x0a>; | |
| bias-bus-hold; | |
| slew-rate = <0x03>; | |
| }; | |
| }; | |
| lpi_i2s3_sd1 { | |
| lpi_i2s3_sd1_active { | |
| phandle = <0x28d>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s3_sd1_sleep { | |
| phandle = <0x28c>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm3_sck { | |
| lpi_tdm3_sck_sleep { | |
| phandle = <0x2aa>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio14"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm3_sck_active { | |
| phandle = <0x2ab>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio14"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s1_sd0 { | |
| lpi_i2s1_sd0_active { | |
| phandle = <0x27b>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sd0_sleep { | |
| phandle = <0x27a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd3 { | |
| quat_mi2s_sd3_sleep { | |
| phandle = <0x274>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd3_active { | |
| phandle = <0x275>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x04>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sd1 { | |
| lpi_tdm1_sd1_active { | |
| phandle = <0x2a1>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sd1_sleep { | |
| phandle = <0x2a0>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_ws { | |
| lpi_tdm2_ws_sleep { | |
| phandle = <0x2a4>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm2_ws_active { | |
| phandle = <0x2a5>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd1 { | |
| quat_tdm_sd1_active { | |
| phandle = <0x295>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_sd1_sleep { | |
| phandle = <0x294>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic23_clk_active { | |
| phandle = <0x252>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| dmic01_data_active { | |
| phandle = <0x24f>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cdc_dmic01_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x24e 0x24f>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x250 0x251>; | |
| phandle = <0x2d8>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| bolero-codec { | |
| qcom,num-macros = <0x02>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| clocks = <0x24d 0x00>; | |
| compatible = "qcom,bolero-codec"; | |
| phandle = <0x2dd>; | |
| qcom,bolero-version = <0x05>; | |
| wcd937x-codec { | |
| qcom,rx-slave = <0x32e>; | |
| qcom,wcd-rst-gpio-node = <0x32d>; | |
| qcom,tx-slave = <0x32f>; | |
| cdc-vddpx-supply = <0x20>; | |
| qcom,swr-tx-port-params = <0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; | |
| qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x493e00 0x2e 0x01 0x1f 0x01 0x493e00 0x32 0x01 0x20 0x02 0x493e00 0x33 0x02 0x22 0x01 0x00 0x31 0x02 0x23 0x02 0x00 0x32 0x02 0x1d 0x04 0x493e00 0x33 0x03 0x24 0x01 0x00 0x34 0x03 0x25 0x02 0x00 0x35 0x03 0x26 0x04 0x00 0x36 0x03 0x27 0x08 0x00 0x37>; | |
| qcom,cdc-micbias2-mv = <0x708>; | |
| qcom,cdc-vdd-rxtx-voltage = <0x1b7740 0x1b7740>; | |
| qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15>; | |
| qcom,cdc-vdd-rxtx-current = <0x2710>; | |
| cdc-vdd-buck-supply = <0x160>; | |
| qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddpx"; | |
| cdc-vdd-rxtx-supply = <0x20>; | |
| qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
| compatible = "qcom,wcd937x-codec"; | |
| qcom,cdc-vdd-buck-current = <0x9eb10>; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| status = "disabled"; | |
| qcom,cdc-vddpx-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-vddpx-current = <0x4e20>; | |
| phandle = <0x33a>; | |
| qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; | |
| qcom,split-codec = <0x01>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| }; | |
| va-macro@a730000 { | |
| qcom,default-clk-id = <0x00>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,va-clk-mux-select = <0x01>; | |
| clocks = <0x24d 0x00>; | |
| qcom,va-dmic-sample-rate = <0x927c0>; | |
| compatible = "qcom,va-macro"; | |
| qcom,va-island-mode-muxsel = "\nz", ""; | |
| reg = <0xa730000 0x00>; | |
| phandle = <0x338>; | |
| qcom,is-used-swr-gpio = <0x00>; | |
| va_swr_master { | |
| qcom,is-always-on = <0x01>; | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,swr-num-dev = <0x01>; | |
| interrupts = <0x00 0x128 0x04 0x00 0x4f 0x04>; | |
| clocks = <0x24d 0x00>; | |
| swrm-io-base = <0xa740000 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,swr-master-version = <0x1060000>; | |
| qcom,swr_master_id = <0x03>; | |
| compatible = "qcom,swr-mstr"; | |
| status = "disabled"; | |
| qcom,mipi-sdw-block-packing-mode = <0x01>; | |
| interrupt-names = "swr_master_irq", "swr_wake_irq"; | |
| qcom,swr-port-mapping = <0x01 0x2e 0x01 0x01 0x2f 0x02 0x01 0x30 0x04 0x01 0x31 0x08 0x02 0x32 0x01 0x02 0x33 0x02 0x02 0x34 0x04 0x02 0x35 0x08 0x03 0x36 0x01 0x03 0x37 0x02 0x03 0x38 0x04 0x03 0x39 0x08>; | |
| phandle = <0x339>; | |
| qcom,swr-wakeup-required = <0x01>; | |
| qcom,swr-mstr-irq-wakeup-capable = <0x01>; | |
| qcom,swr-num-ports = <0x03>; | |
| qcom,swrm-hctl-reg = <0xa7ec100>; | |
| wcd937x-tx-slave { | |
| compatible = "qcom,wcd937x-slave"; | |
| status = "disabled"; | |
| reg = <0x0a 0x1170223>; | |
| phandle = <0x32f>; | |
| }; | |
| }; | |
| }; | |
| bolero-clk-rsc-mngr { | |
| clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", "va_core_clk", "va_npl_clk"; | |
| qcom,va_mclk_mode_muxsel = "\nz", ""; | |
| clocks = <0x327 0x00 0x328 0x00 0x329 0x00 0x32a 0x00 0x32b 0x00 0x32c 0x00>; | |
| qcom,rx_mclk_mode_muxsel = <0xa5640d8>; | |
| qcom,fs-gen-sequence = <0x3000 0x01 0x01 0x3004 0x03 0x03 0x3004 0x03 0x01 0x3080 0x02 0x02>; | |
| compatible = "qcom,bolero-clk-rsc-mngr"; | |
| }; | |
| rx-macro@a600000 { | |
| qcom,default-clk-id = <0x00>; | |
| clock-names = "rx_core_clk", "rx_npl_clk"; | |
| clocks = <0x329 0x00 0x32a 0x00>; | |
| qcom,rx_mclk_mode_muxsel = <0xa5640d8>; | |
| compatible = "qcom,rx-macro"; | |
| status = "disabled"; | |
| reg = <0xa600000 0x00>; | |
| qcom,rx-bcl-pmic-params = [00 04 3e]; | |
| phandle = <0x336>; | |
| qcom,is-used-swr-gpio = <0x00>; | |
| rx_swr_master { | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,swr-num-dev = <0x01>; | |
| interrupts = <0x00 0x129 0x04>; | |
| clocks = <0x24d 0x00>; | |
| swrm-io-base = <0xa610000 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,swr-master-version = <0x1060000>; | |
| qcom,swr_master_id = <0x02>; | |
| compatible = "qcom,swr-mstr"; | |
| qcom,mipi-sdw-block-packing-mode = <0x01>; | |
| interrupt-names = "swr_master_irq"; | |
| qcom,swr-port-mapping = <0x01 0x0e 0x01 0x01 0x0f 0x02 0x02 0x12 0x01 0x03 0x10 0x01 0x03 0x11 0x02 0x04 0x13 0x01 0x05 0x14 0x01 0x05 0x15 0x02>; | |
| phandle = <0x337>; | |
| qcom,swr-num-ports = <0x05>; | |
| qcom,disable-div2-clk-switch = <0x01>; | |
| qcom,swrm-hctl-reg = <0xa6a9098>; | |
| wcd937x-rx-slave { | |
| compatible = "qcom,wcd937x-slave"; | |
| status = "disabled"; | |
| reg = <0x0a 0x1170224>; | |
| phandle = <0x32e>; | |
| }; | |
| }; | |
| }; | |
| tx-macro@a620000 { | |
| clock-names = "tx_core_clk", "tx_npl_clk"; | |
| clocks = <0x327 0x00 0x328 0x00>; | |
| qcom,tx-dmic-sample-rate = <0x249f00>; | |
| compatible = "qcom,tx-macro"; | |
| reg = <0xa620000 0x00>; | |
| phandle = <0x335>; | |
| qcom,is-used-swr-gpio = <0x00>; | |
| }; | |
| }; | |
| quat_mi2s_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x26b 0x26d 0x26e 0x271>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x26a 0x26c 0x26e 0x270>; | |
| phandle = <0x332>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| sec_mi2s_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x27f 0x281 0x283 0x285>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x27e 0x280 0x282 0x284>; | |
| phandle = <0x331>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| qcom,msm-audio-ion { | |
| iommus = <0x29 0x1c1 0x00>; | |
| qcom,smmu-enabled; | |
| qcom,smmu-sid-mask = <0x00 0x0f>; | |
| compatible = "qcom,msm-audio-ion"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>; | |
| phandle = <0x2d6>; | |
| qcom,smmu-version = <0x02>; | |
| }; | |
| qcom,msm-audio-ion-cma { | |
| compatible = "qcom,msm-audio-ion-cma"; | |
| phandle = <0x2d7>; | |
| }; | |
| sound { | |
| qcom,rxtx-bolero-codec = <0x01>; | |
| qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3"; | |
| nvmem-cells = <0x64>; | |
| qcom,msm-mbhc-gnd-swh = <0x00>; | |
| qcom,sec-mi2s-gpios = <0x331>; | |
| asoc-codec = <0x264 0x2dd 0x330>; | |
| qcom,cdc-dmic01-gpios = <0x2d8>; | |
| qcom,quat-mi2s-gpios = <0x332>; | |
| qcom,afe-rxtx-lb = <0x00>; | |
| asoc-codec-names = "msm-stub-codec.1", "bolero-codec", "es8326_codec"; | |
| qcom,msm-mbhc-usbc-audio-supported = <0x01>; | |
| qcom,msm_audio_ssr_devs = <0x2e3 0x269 0x2dd>; | |
| qcom,msm-mi2s-master = <0x01 0x01 0x01 0x01>; | |
| qcom,model = "bengal-idp-snd-card"; | |
| qcom,tdm-audio-intf = <0x00>; | |
| qcom,va-bolero-codec = <0x00>; | |
| compatible = "qcom,bengal-asoc-snd"; | |
| qcom,msm-mbhc-hphl-swh = <0x00>; | |
| nvmem-cell-names = "adsp_variant"; | |
| qcom,auxpcm-audio-intf = <0x00>; | |
| phandle = <0x33b>; | |
| qcom,wcd-disabled = <0x01>; | |
| qcom,mi2s-audio-intf = <0x01>; | |
| qcom,wsa-aux-dev-prefix = "SpkrMono"; | |
| qcom,wsa-max-devs = <0x00>; | |
| qcom,wcn-btfm = <0x01>; | |
| qcom,mi2s-mclk-attribute = <0x00 0x00 0x00 0x01 0x00 0x00 0x00>; | |
| qcom,cdc-dmic23-gpios = <0x2d9>; | |
| }; | |
| cdc_dmic23_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x252 0x253>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x254 0x255>; | |
| phandle = <0x2d9>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| va_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| qcom,chip-wakeup-reg = <0x3ca04c>; | |
| qcom,chip-wakeup-maskbit = <0x00>; | |
| qcom,chip-wakeup-default-val = <0x01>; | |
| pinctrl-0 = <0x25c 0x25d 0x25e>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x25f 0x260 0x261>; | |
| phandle = <0x2db>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| rx_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x256 0x257 0x258>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x259 0x25a 0x25b>; | |
| phandle = <0x2da>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| }; | |
| qcom,icnss@C800000 { | |
| iommus = <0x29 0x1a0 0x01>; | |
| vdd-1.8-xo-supply = <0x23>; | |
| reg-names = "membase", "smmu_iova_ipa"; | |
| qcom,vdd-cx-mx-config = <0x9c400 0x9c400>; | |
| qcom,wlan; | |
| interrupts = <0x00 0x166 0x04 0x00 0x167 0x04 0x00 0x168 0x04 0x00 0x169 0x04 0x00 0x16a 0x04 0x00 0x16b 0x04 0x00 0x16c 0x04 0x00 0x16d 0x04 0x00 0x16e 0x04 0x00 0x16f 0x04 0x00 0x170 0x04 0x00 0x171 0x04>; | |
| qcom,vdd-3.3-ch0-config = <0x2dc6c0 0x328980>; | |
| vdd-3.3-ch0-supply = <0x22>; | |
| qcom,iommu-geometry = <0xa0000000 0x10010000>; | |
| compatible = "qcom,icnss"; | |
| qcom,wlan-msa-fixed-region = <0x135>; | |
| qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; | |
| reg = <0xc800000 0x800000 0xb0000000 0x10000>; | |
| phandle = <0x23f>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| vdd-1.3-rfa-supply = <0x21>; | |
| vdd-cx-mx-supply = <0x15c>; | |
| qcom,iommu-dma = "fastmap"; | |
| qcom,smp2p_map_wlan_1_in { | |
| interrupts-extended = <0x23e 0x00 0x00 0x23e 0x01 0x00>; | |
| interrupt-names = "qcom,smp2p-force-fatal-error", "qcom,smp2p-early-crash-ind"; | |
| }; | |
| }; | |
| tpdm@899c000 { | |
| qcom,dummy-source; | |
| coresight-name = "coresight-tpdm-wcss"; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x19f>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9a>; | |
| phandle = <0xdd>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,demux { | |
| compatible = "qcom,demux"; | |
| }; | |
| cti@8012000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti2"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8012000 0x1000>; | |
| phandle = <0x1d3>; | |
| }; | |
| restart@440b000 { | |
| reg-names = "pshold-base", "tcsr-boot-misc-detect"; | |
| compatible = "qcom,pshold"; | |
| reg = <0x440b000 0x04 0x3d3000 0x04>; | |
| }; | |
| funnel@8045000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-funnel-merg"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8045000 0x1000>; | |
| phandle = <0x1b9>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe1>; | |
| phandle = <0xd6>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xe2>; | |
| phandle = <0xda>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe0>; | |
| phandle = <0xe5>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcedev@1b20000 { | |
| iommus = <0x29 0x86 0x11 0x29 0x96 0x11>; | |
| qcom,ce-hw-shared; | |
| interconnect-names = "data_path"; | |
| qcom,ce-device = <0x00>; | |
| clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
| interconnects = <0x28 0x07 0x26 0x200>; | |
| reg-names = "crypto-base", "crypto-bam-base"; | |
| qcom,bam-ee = <0x00>; | |
| interrupts = <0x00 0xf7 0x04>; | |
| clocks = <0x1c 0x46 0x1c 0x46 0x1c 0x46 0x1c 0x46>; | |
| qcom,ce-opp-freq = <0xb71b000>; | |
| compatible = "qcom,qcedev"; | |
| qcom,bam-pipe-pair = <0x03>; | |
| reg = <0x1b20000 0x20000 0x1b04000 0x24000>; | |
| phandle = <0x14c>; | |
| qcom,smmu-s1-enable; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,iommu-dma = "atomic"; | |
| qcom_cedev_s_cb { | |
| iommus = <0x29 0x93 0x00 0x29 0x9c 0x01 0x29 0x9e 0x00>; | |
| qcom,secure-context-bank; | |
| label = "secure_context"; | |
| compatible = "qcom,qcedev,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x70000000 0x10000000>; | |
| qcom,iommu-vmid = <0x09>; | |
| }; | |
| qcom_cedev_ns_cb { | |
| iommus = <0x29 0x92 0x00 0x29 0x98 0x01 0x29 0x9f 0x00>; | |
| label = "ns_context"; | |
| compatible = "qcom,qcedev,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x70000000 0x10000000>; | |
| }; | |
| }; | |
| cti@8B59000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-dlct-cti0"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8b59000 0x1000>; | |
| phandle = <0x1c8>; | |
| }; | |
| etm@9540000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| cpu = <0x10>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm5"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9540000 0x1000>; | |
| phandle = <0x1a6>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa1>; | |
| phandle = <0xad>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@8B5A000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-dlct-cti1"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8b5a000 0x1000>; | |
| phandle = <0x1c9>; | |
| }; | |
| jtagmm@9640000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x11>; | |
| reg = <0x9640000 0x1000>; | |
| phandle = <0x141>; | |
| }; | |
| tpdm@8840000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-vsense"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8840000 0x1000>; | |
| phandle = <0x198>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x93>; | |
| phandle = <0xc9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm_gsi { | |
| compatible = "qcom,msm_gsi"; | |
| }; | |
| qcom,cpufreq-hw { | |
| clock-names = "xo", "alternate"; | |
| reg-names = "freq-domain0", "freq-domain1"; | |
| qcom,max-lut-entries = <0x0c>; | |
| #freq-domain-cells = <0x02>; | |
| clocks = <0x1c 0x00 0x1d 0x00>; | |
| qcom,no-accumulative-counter; | |
| compatible = "qcom,cpufreq-hw"; | |
| reg = <0xf521000 0x1000 0xf523000 0x1000>; | |
| phandle = <0x05>; | |
| }; | |
| funnel@8042000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-funnel-in1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x8042000 0x1000>; | |
| phandle = <0x1b8>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0xdd>; | |
| phandle = <0x9a>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xdb>; | |
| phandle = <0xbb>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xdf>; | |
| phandle = <0xb6>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xde>; | |
| phandle = <0x9b>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xdc>; | |
| phandle = <0x8d>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xda>; | |
| phandle = <0xe2>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| debug-clock-controller@0 { | |
| qcom,gpucc = <0x5d>; | |
| clock-names = "xo_clk_src"; | |
| clocks = <0x1c 0x00>; | |
| #clock-cells = <0x01>; | |
| qcom,gcc = <0x1d>; | |
| qcom,dispcc = <0x5c>; | |
| compatible = "qcom,sm6115-debugcc"; | |
| qcom,mccc = <0x5e>; | |
| phandle = <0x171>; | |
| qcom,cpucc = <0x5f>; | |
| }; | |
| qtee_shmbridge { | |
| qcom,disable-shmbridge-support; | |
| compatible = "qcom,tee-shared-memory-bridge"; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_5_in { | |
| interrupts-extended = <0x117 0x00 0x00>; | |
| compatible = "qcom,smp2p-interrupt-rdbg-5-in"; | |
| interrupt-names = "rdbg-smp2p-in"; | |
| }; | |
| usb_nop_phy { | |
| compatible = "usb-nop-xceiv"; | |
| phandle = <0x18e>; | |
| }; | |
| bt_wcn3990 { | |
| qca,bt-vdd-core-supply = <0x21>; | |
| qca,bt-vdd-core-current-level = <0x01>; | |
| qca,bt-vdd-pa-voltage-level = <0x2dc6c0 0x328980>; | |
| qca,bt-vdd-io-voltage-level = <0x19f0a0 0x1cfde0>; | |
| qca,bt-vdd-xtal-voltage-level = <0x19f0a0 0x1cfde0>; | |
| qca,bt-vdd-pa-supply = <0x22>; | |
| qca,bt-vdd-xtal-supply = <0x23>; | |
| compatible = "qca,wcn3990"; | |
| qca,bt-vdd-core-voltage-level = <0x13e5c0 0x13e5c0>; | |
| phandle = <0x145>; | |
| qca,bt-vdd-pa-current-level = <0x01>; | |
| qca,bt-vdd-io-supply = <0x20>; | |
| qca,bt-vdd-io-current-level = <0x01>; | |
| qca,bt-vdd-xtal-current-level = <0x01>; | |
| qca,bt-sw-ctrl-gpio = <0x1f 0x57 0x00>; | |
| }; | |
| qcom,msm-stub-codec { | |
| compatible = "qcom,msm-stub-codec"; | |
| phandle = <0x264>; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_2_in { | |
| interrupts-extended = <0x115 0x00 0x00>; | |
| compatible = "qcom,smp2p-interrupt-rdbg-2-in"; | |
| interrupt-names = "rdbg-smp2p-in"; | |
| }; | |
| qcom,smp2p-modem { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x00 0x46 0x01>; | |
| qcom,remote-pid = <0x01>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x31 0x0e>; | |
| qcom,smem = <0x1b3 0x1ac>; | |
| qcom,smp2p-ipa-1-in { | |
| qcom,entry-name = "ipa"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x78>; | |
| interrupt-controller; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x71>; | |
| interrupt-controller; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x72>; | |
| }; | |
| qcom,smp2p-ipa-1-out { | |
| qcom,entry-name = "ipa"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x77>; | |
| }; | |
| qcom,smp2p-wlan-1-in { | |
| qcom,entry-name = "wlan"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x23e>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| cti@89A4000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-wcss-cti0"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x89a4000 0x1000>; | |
| phandle = <0x1c0>; | |
| }; | |
| apps-smmu@0xc600000 { | |
| #global-interrupts = <0x01>; | |
| #address-cells = <0x01>; | |
| interconnects = <0x26 0x00 0x28 0x23c>; | |
| reg-names = "base", "tcu-base"; | |
| qcom,num-smr-override = <0x32>; | |
| interrupts = <0x00 0x51 0x04 0x00 0x58 0x04 0x00 0x59 0x04 0x00 0x5a 0x04 0x00 0x5b 0x04 0x00 0x5c 0x04 0x00 0x5d 0x04 0x00 0x5e 0x04 0x00 0x5f 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0x77 0x04 0x00 0x78 0x04 0x00 0x79 0x04 0x00 0x7a 0x04 0x00 0x7b 0x04 0x00 0x7c 0x04 0x00 0x7d 0x04 0x00 0x7e 0x04 0x00 0x7f 0x04 0x00 0x80 0x04 0x00 0x81 0x04 0x00 0x82 0x04 0x00 0x83 0x04 0x00 0x84 0x04 0x00 0x85 0x04 0x00 0x86 0x04 0x00 0x87 0x04 0x00 0x88 0x04 0x00 0x89 0x04 0x00 0x8a 0x04 0x00 0x8b 0x04 0x00 0x8c 0x04 0x00 0x8d 0x04 0x00 0x8e 0x04 0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04 0x00 0x93 0x04 0x00 0x94 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04>; | |
| qcom,actlr = <0x400 0x3ff 0x103 0x800 0x3ff 0x103>; | |
| #size-cells = <0x01>; | |
| qcom,skip-init; | |
| qcom,use-3-lvl-tables; | |
| #iommu-cells = <0x02>; | |
| compatible = "qcom,qsmmu-v500"; | |
| ranges; | |
| status = "okay"; | |
| reg = <0xc600000 0x80000 0xc782000 0x20>; | |
| phandle = <0x29>; | |
| qcom,handoff-smrs = <0x420 0x02>; | |
| qcom,num-context-banks-override = <0x30>; | |
| qcom,active-only; | |
| cdsp_tbu@0xc791000 { | |
| interconnects = <0x26 0x00 0x26 0x200 0x26 0x00 0x28 0x23c>; | |
| reg-names = "base", "status-reg"; | |
| qcom,stream-id-range = <0xc00 0x400>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0xee>; | |
| qcom,iova-width = <0x20>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0xc791000 0x1000 0xc782218 0x08>; | |
| phandle = <0x1e0>; | |
| qcom,active-only; | |
| }; | |
| mm_nrt_tbu@0xc78d000 { | |
| interconnects = <0xed 0x0a 0xed 0x233 0x26 0x00 0x28 0x23c>; | |
| reg-names = "base", "status-reg"; | |
| qcom,stream-id-range = <0x800 0x400>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0xec>; | |
| qcom,iova-width = <0x20>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0xc78d000 0x1000 0xc782210 0x08>; | |
| phandle = <0x1df>; | |
| qcom,active-only; | |
| }; | |
| mm_rt_tbu@0xc789000 { | |
| interconnects = <0xeb 0x0e 0xeb 0x234 0x26 0x00 0x28 0x23c>; | |
| reg-names = "base", "status-reg"; | |
| qcom,stream-id-range = <0x400 0x400>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0xea>; | |
| qcom,iova-width = <0x24>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0xc789000 0x1000 0xc782208 0x08>; | |
| phandle = <0x1de>; | |
| qcom,active-only; | |
| }; | |
| anoc_1_tbu@0xc785000 { | |
| interconnects = <0x26 0x00 0x27 0x217 0x26 0x00 0x28 0x23c>; | |
| reg-names = "base", "status-reg"; | |
| qcom,stream-id-range = <0x00 0x400>; | |
| qcom,iova-width = <0x24>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0xc785000 0x1000 0xc782200 0x08>; | |
| phandle = <0x1dd>; | |
| qcom,active-only; | |
| }; | |
| }; | |
| remoteproc-mss@6080000 { | |
| qcom,smem-state-names = "stop"; | |
| clock-names = "xo"; | |
| reg-names = "cx"; | |
| memory-region = <0x70>; | |
| clocks = <0x1c 0x00>; | |
| interrupts-extended = <0x01 0x00 0x133 0x01 0x71 0x00 0x00 0x71 0x02 0x00 0x71 0x01 0x00 0x71 0x03 0x00 0x71 0x07 0x00>; | |
| cx-supply = <0x32>; | |
| compatible = "qcom,bengal-modem-pas"; | |
| interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack", "shutdown-ack"; | |
| reg = <0x6080000 0x100>; | |
| phandle = <0x17e>; | |
| qcom,smem-states = <0x72 0x00>; | |
| cx-uV-uA = <0x180 0x186a0>; | |
| glink-edge { | |
| transport = "smem"; | |
| interrupts = <0x00 0x44 0x01>; | |
| qcom,glink-label = "mpss"; | |
| label = "modem"; | |
| qcom,remote-pid = <0x01>; | |
| mboxes = <0x31 0x0c>; | |
| mbox-names = "mpss_smem"; | |
| qcom,modem_qrtr { | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| qcom,msm_fastrpc_rpmsg { | |
| qcom,intents = <0x64 0x40>; | |
| compatible = "qcom,msm-fastrpc-rpmsg"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| }; | |
| qcom,modem_ds { | |
| qcom,intents = <0x4000 0x02>; | |
| qcom,glink-channels = "DS"; | |
| }; | |
| }; | |
| }; | |
| qfprom@0 { | |
| nvmem-cells = <0x64 0x65 0x66>; | |
| compatible = "qcom,qfprom-sys"; | |
| nvmem-cell-names = "adsp_variant", "feat_conf5", "feat_conf10"; | |
| phandle = <0x173>; | |
| }; | |
| syscon@5991008 { | |
| compatible = "syscon"; | |
| reg = <0x5991008 0x04>; | |
| phandle = <0x7b>; | |
| }; | |
| qcom,glink { | |
| compatible = "qcom,glink"; | |
| }; | |
| bamdma@0xa580000 { | |
| qcom,num-ees = <0x02>; | |
| reg-names = "bam", "bam_remote_mem"; | |
| interrupts = <0x00 0x11c 0x04>; | |
| num-channels = <0x1f>; | |
| qcom,controlled-remotely; | |
| compatible = "qcom,bam-v1.7.0"; | |
| reg = <0xa584000 0x20000 0xa66f000 0x1000>; | |
| phandle = <0x1e>; | |
| qcom,ee = <0x01>; | |
| #dma-cells = <0x01>; | |
| }; | |
| qcom,ghd { | |
| qcom,config-reg = <0xf1d1434>; | |
| qcom,threshold-arr = <0xf1d141c 0xf1d1420 0xf1d1424 0xf1d1428 0xf1d142c 0xf1d1430>; | |
| compatible = "qcom,gladiator-hang-detect"; | |
| }; | |
| qcom,smem { | |
| memory-region = <0x62>; | |
| compatible = "qcom,smem"; | |
| phandle = <0x172>; | |
| hwlocks = <0x63 0x03>; | |
| }; | |
| tpda@8004000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x07 0x20 0x08 0x20 0x0a 0x20 0x0f 0x40>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpda"; | |
| qcom,dsb-elem-size = <0x00 0x20 0x01 0x20 0x05 0x20 0x0c 0x20 0x0d 0x20 0x0f 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x41>; | |
| reg = <0x8004000 0x1000>; | |
| phandle = <0x1b4>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xc6>; | |
| phandle = <0x8b>; | |
| }; | |
| }; | |
| port@12 { | |
| reg = <0x0c>; | |
| endpoint { | |
| remote-endpoint = <0xcc>; | |
| phandle = <0x96>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0xc9>; | |
| phandle = <0x93>; | |
| }; | |
| }; | |
| port@10 { | |
| reg = <0x0a>; | |
| endpoint { | |
| remote-endpoint = <0xcb>; | |
| phandle = <0x95>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0xc8>; | |
| phandle = <0xbf>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xc7>; | |
| phandle = <0xbd>; | |
| }; | |
| }; | |
| port@15 { | |
| reg = <0x0f>; | |
| endpoint { | |
| remote-endpoint = <0xce>; | |
| phandle = <0x98>; | |
| }; | |
| }; | |
| port@13 { | |
| reg = <0x0d>; | |
| endpoint { | |
| remote-endpoint = <0xcd>; | |
| phandle = <0x97>; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0x08>; | |
| endpoint { | |
| remote-endpoint = <0xca>; | |
| phandle = <0x94>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xc5>; | |
| phandle = <0xd3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ts_charger { | |
| compatible = "ts,charger"; | |
| status = "disabled"; | |
| panel = <0x312 0x319 0x31b 0x31c>; | |
| }; | |
| va_npl_clk { | |
| qcom,codec-ext-clk-src = <0x0a>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x32c>; | |
| qcom,codec-lpass-clk-id = <0x308>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| interconnect@1 { | |
| clock-names = "bus", "bus_a"; | |
| clocks = <0x1c 0x6c 0x1c 0x6d>; | |
| #interconnect-cells = <0x01>; | |
| compatible = "qcom,bengal-mmrt_virt"; | |
| qcom,util-factor = <0x8b>; | |
| phandle = <0xeb>; | |
| qcom,keepalive; | |
| }; | |
| qcom,pmu { | |
| qcom,pmu-events-tbl = <0x08 0xff 0xff 0xff 0x11 0xff 0xff 0xff 0x17 0xff 0xff 0xff>; | |
| compatible = "qcom,pmu"; | |
| phandle = <0x17f>; | |
| }; | |
| qcom,msm-rtb { | |
| compatible = "qcom,msm-rtb"; | |
| qcom,rtb-size = <0x100000>; | |
| }; | |
| interconnect@1880000 { | |
| clock-names = "bus", "bus_a"; | |
| clocks = <0x1c 0x04 0x1c 0x05 0x1d 0x38 0x1d 0x74>; | |
| #interconnect-cells = <0x01>; | |
| compatible = "qcom,bengal-system_noc"; | |
| reg = <0x1880000 0x5f080>; | |
| phandle = <0x28>; | |
| qcom,keepalive; | |
| }; | |
| tpd@9830000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-tpdm-actpm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9830000 0x1000>; | |
| phandle = <0x1a9>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa4>; | |
| phandle = <0xb1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@8A21000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-lpass-q6"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x8a21000 0x1000>; | |
| phandle = <0x1c3>; | |
| }; | |
| qcom,msm-gladiator-v2@f100000 { | |
| clock-names = "atb_clk"; | |
| reg-names = "gladiator_base"; | |
| interrupts = <0x00 0x16 0x04>; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,msm-gladiator-v2"; | |
| reg = <0xf100000 0xdc00>; | |
| }; | |
| qcom,gdsc@599100c { | |
| parent-supply = <0x32>; | |
| domain-addr = <0x7c>; | |
| regulator-name = "gpu_gx_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x599100c 0x04>; | |
| sw-reset = <0x7b>; | |
| phandle = <0x18c>; | |
| }; | |
| qcom,msm_notifier@0 { | |
| compatible = "qcom,msm-notifier"; | |
| phandle = <0x322>; | |
| panel = <0x314 0x315>; | |
| }; | |
| qcom,gdsc@141a004 { | |
| regulator-name = "gcc_usb30_prim_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x141a004 0x04>; | |
| phandle = <0x7d>; | |
| }; | |
| fan { | |
| cooling-levels = <0x00 0xff>; | |
| cooling-max-state = <0x01>; | |
| gpio-fan,speed-map = <0x00 0x00 0x01 0x01>; | |
| compatible = "gpio-fan"; | |
| phandle = <0x303>; | |
| gpios = <0x1f 0x5c 0x00>; | |
| cooling-min-state = <0x00>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| arm64_cpu_erp { | |
| interrupts = <0x00 0x2b 0x04 0x00 0x2c 0x04 0x00 0x29 0x04 0x00 0x2a 0x04>; | |
| compatible = "arm,arm64-cpu-erp"; | |
| interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq"; | |
| poll-delay-ms = <0x1388>; | |
| }; | |
| cti@98F0000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-apss-cti1"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x98f0000 0x1000>; | |
| phandle = <0x1bf>; | |
| }; | |
| mcu@0 { | |
| pinctrl-names = "default"; | |
| mcu-select-gpios = <0x1f 0x18 0x01>; | |
| stick-en-gpio = <0x1f 0x16 0x01>; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2f2>; | |
| mcu-mode-gpios = <0x1f 0x24 0x01>; | |
| mcu-boot0 = <0x1f 0x1b 0x01>; | |
| mcu-start-gpios = <0x1f 0x12 0x01>; | |
| #size-cells = <0x01>; | |
| mcu-back-gpios = <0x1f 0x22 0x01>; | |
| compatible = "uart,mcu_joystick"; | |
| mcu-power = <0x1f 0x19 0x01>; | |
| status = "ok"; | |
| mcu-boot1 = <0x1f 0x1c 0x01>; | |
| mcu-reset = <0x1f 0x1a 0x01>; | |
| reg = <0x00>; | |
| phandle = <0x302>; | |
| panel = <0x312 0x319 0x31b 0x31c>; | |
| }; | |
| qcom,chd_silver { | |
| qcom,config-arr = <0xf1880b8 0xf1980b8 0xf1a80b8 0xf1b80b8>; | |
| label = "silver"; | |
| qcom,threshold-arr = <0xf1880b0 0xf1980b0 0xf1a80b0 0xf1b80b0>; | |
| compatible = "qcom,core-hang-detect"; | |
| }; | |
| etm@9440000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x1c 0x08>; | |
| cpu = <0x0f>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm4"; | |
| compatible = "arm,primecell"; | |
| reg = <0x9440000 0x1000>; | |
| phandle = <0x1a5>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa0>; | |
| phandle = <0xac>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| jtagmm@9540000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x1c 0x08>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x10>; | |
| reg = <0x9540000 0x1000>; | |
| phandle = <0x140>; | |
| }; | |
| cti@801d000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti13"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x801d000 0x1000>; | |
| phandle = <0x1d0>; | |
| }; | |
| qcom,kgsl-iommu@59a0000 { | |
| vddcx-supply = <0xe9>; | |
| compatible = "qcom,kgsl-smmu-v2"; | |
| reg = <0x59a0000 0x10000>; | |
| phandle = <0x2e5>; | |
| gfx3d_user { | |
| iommus = <0x1db 0x00 0x01>; | |
| label = "gfx3d_user"; | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x2e6>; | |
| qcom,gpu-offset = <0xa8000>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| gfx3d_secure { | |
| iommus = <0x1db 0x02 0x00>; | |
| label = "gfx3d_secure"; | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x2e7>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| }; | |
| stm@8002000 { | |
| arm,primecell-periphid = <0xbb962>; | |
| nvmem-cells = <0x89>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "stm-base", "stm-stimulus-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-stm"; | |
| compatible = "arm,primecell"; | |
| nvmem-cell-names = "debug_fuse"; | |
| reg = <0x8002000 0x1000 0xe280000 0x180000>; | |
| phandle = <0x191>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8a>; | |
| phandle = <0xd9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,lmh-cpu-vdd@f550800 { | |
| compatible = "qcom,lmh-cpu-vdd"; | |
| reg = <0xf550800 0x1000>; | |
| phandle = <0x23c>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| qcrypto@1b20000 { | |
| iommus = <0x29 0x84 0x11 0x29 0x94 0x11>; | |
| qcom,ce-hw-shared; | |
| interconnect-names = "data_path"; | |
| qcom,ce-device = <0x00>; | |
| clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
| interconnects = <0x28 0x07 0x26 0x200>; | |
| reg-names = "crypto-base", "crypto-bam-base"; | |
| qcom,use-sw-aes-xts-algo; | |
| qcom,clk-mgmt-sus-res; | |
| qcom,bam-ee = <0x00>; | |
| interrupts = <0x00 0xf7 0x04>; | |
| qcom,use-sw-aead-algo; | |
| clocks = <0x1c 0x46 0x1c 0x46 0x1c 0x46 0x1c 0x46>; | |
| compatible = "qcom,qcrypto"; | |
| qcom,bam-pipe-pair = <0x02>; | |
| qcom,use-sw-ahash-algo; | |
| qcom,use-sw-aes-ccm-algo; | |
| reg = <0x1b20000 0x20000 0x1b04000 0x24000>; | |
| phandle = <0x14d>; | |
| qcom,smmu-s1-enable; | |
| qcom,use-sw-hmac-algo; | |
| qcom,use-sw-aes-cbc-ecb-ctr-algo; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| qcom,gdsc@145807c { | |
| regulator-name = "gcc_venus_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x145807c 0x04>; | |
| phandle = <0x18a>; | |
| }; | |
| qmi-tmd-devices { | |
| compatible = "qcom,qmi-cooling-devices"; | |
| adsp { | |
| qcom,instance-id = <0x01>; | |
| adsp_vdd { | |
| phandle = <0x23b>; | |
| qcom,qmi-dev-name = "cpuv_restriction_cold"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| cdsp { | |
| qcom,instance-id = <0x43>; | |
| hvx { | |
| phandle = <0x23a>; | |
| qcom,qmi-dev-name = "cdsp_hw"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cdsp { | |
| phandle = <0x41>; | |
| qcom,qmi-dev-name = "cdsp_sw"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| modem { | |
| qcom,instance-id = <0x00>; | |
| modem_vdd { | |
| phandle = <0x238>; | |
| qcom,qmi-dev-name = "cpuv_restriction_cold"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_proc { | |
| phandle = <0x44>; | |
| qcom,qmi-dev-name = "modem"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_wlan { | |
| phandle = <0x239>; | |
| qcom,qmi-dev-name = "wlan"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_pa { | |
| phandle = <0x45>; | |
| qcom,qmi-dev-name = "pa"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_skin { | |
| phandle = <0x237>; | |
| qcom,qmi-dev-name = "modem_skin"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_current { | |
| phandle = <0x236>; | |
| qcom,qmi-dev-name = "modem_current"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| }; | |
| cti@801a000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti10"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x801a000 0x1000>; | |
| phandle = <0x1cd>; | |
| }; | |
| sdhci@4744000 { | |
| iommus = <0x29 0xc0 0x00>; | |
| pinctrl-names = "default", "sleep"; | |
| mmc-hs400-enhanced-strobe; | |
| nvmem-cells = <0x37>; | |
| interconnect-names = "sdhc-ddr", "cpu-sdhc"; | |
| qcom,vdd-voltage-level = <0x2d2a80 0x2d2a80>; | |
| qcom,restore-after-cx-collapse; | |
| pinctrl-0 = <0x1e1>; | |
| clock-names = "iface", "core", "ice_core"; | |
| interconnects = <0x28 0x1a 0x26 0x200 0x26 0x00 0x27 0x228>; | |
| reg-names = "hc", "cqhci", "cqhci_ice"; | |
| mmc-hs200-1_8v; | |
| bus-width = <0x08>; | |
| non-removable; | |
| no-sdio; | |
| resets = <0x1d 0x02>; | |
| mmc-hs400-1_8v; | |
| clocks = <0x1d 0x6a 0x1d 0x6b 0x1d 0x6d>; | |
| supports-cqe; | |
| qcom,vdd-io-current-level = <0x00 0x4f588>; | |
| cap-mmc-hw-reset; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| qcom,ice-clk-rates = <0x11e1a300 0x5f5e100>; | |
| interrupts-extended = <0x01 0x00 0x15c 0x04 0x01 0x00 0x160 0x04 0x1f 0x13 0x01>; | |
| vdd-supply = <0x166>; | |
| no-sd; | |
| mmc-ddr-1_8v; | |
| compatible = "qcom,sdhci-msm-v5"; | |
| qcom,devfreq,freq-table = <0x2faf080 0xbebc200>; | |
| qcom,vdd-io-lpm-sup; | |
| vdd-io-supply = <0x15e>; | |
| pinctrl-1 = <0x1e2>; | |
| qcom,vdd-current-level = <0x00 0x8b290>; | |
| status = "ok"; | |
| qcom,dll-hsr-list = <0xf642c 0x00 0x00 0x10800 0x80040850>; | |
| interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq"; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| nvmem-cell-names = "boot_conf"; | |
| reg = <0x4744000 0x1000 0x4745000 0x1000 0x4748000 0x8000>; | |
| phandle = <0x16a>; | |
| qcom,vdd-io-always-on; | |
| reset-names = "core_reset"; | |
| operating-points-v2 = <0x38>; | |
| qcom,scaling-lower-bus-speed-mode = "DDR52"; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>; | |
| qcom,iommu-dma = "fastmap"; | |
| qos0 { | |
| mask = <0xf0>; | |
| vote = <0x2c>; | |
| }; | |
| qos1 { | |
| mask = <0x0f>; | |
| vote = <0x2c>; | |
| }; | |
| }; | |
| tx_npl_clk { | |
| qcom,codec-ext-clk-src = <0x08>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x328>; | |
| qcom,codec-lpass-clk-id = <0x30d>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| qcom,limits-0-dcvs@f550800 { | |
| qcom,affinity = <0x00>; | |
| interrupts = <0x00 0x25 0x04>; | |
| compatible = "qcom,msm-hw-limits"; | |
| reg = <0xf550800 0x1000 0xf521000 0x1000>; | |
| phandle = <0x06>; | |
| }; | |
| turing_etm0 { | |
| qcom,inst-id = <0x0d>; | |
| coresight-name = "coresight-turing-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| phandle = <0xc2>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x92>; | |
| phandle = <0xc4>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ddr-freq-table { | |
| phandle = <0x73>; | |
| ddr4 { | |
| qcom,freq-tbl = <0x30d40 0x858b8 0xbb800 0xf84a8 0x17ba38 0x1b86e0 0x1febe0>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr3 { | |
| qcom,freq-tbl = <0x30d40 0x493e0 0x6e1b8 0x858b8 0xa6428 0xbb800 0xe34b8>; | |
| qcom,ddr-type = <0x05>; | |
| }; | |
| }; | |
| slim@a5c0000 { | |
| #address-cells = <0x01>; | |
| reg-names = "ctrl", "slimbus_remote_mem"; | |
| interrupts = <0x00 0x11b 0x04>; | |
| #size-cells = <0x00>; | |
| dma-names = "rx", "tx"; | |
| compatible = "qcom,slim-ngd-v1.5.0"; | |
| status = "ok"; | |
| reg = <0xa5c0000 0x2c000 0xa66e000 0x1000>; | |
| phandle = <0x24b>; | |
| dmas = <0x1e 0x03 0x1e 0x04>; | |
| ngd@1 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x01>; | |
| btfmslim-driver { | |
| compatible = "slim217,221"; | |
| reg = <0x01 0x00>; | |
| phandle = <0x24c>; | |
| }; | |
| }; | |
| }; | |
| sdhci@4784000 { | |
| iommus = <0x29 0xa0 0x00>; | |
| qcom,vdd-io-bias-voltage-level = <0x132a40 0x132a40>; | |
| pinctrl-names = "default", "sleep"; | |
| interconnect-names = "sdhc-ddr", "cpu-sdhc"; | |
| qcom,vdd-voltage-level = <0x2d2a80 0x2d2a80>; | |
| qcom,restore-after-cx-collapse; | |
| pinctrl-0 = <0x1e3>; | |
| clock-names = "iface", "core"; | |
| interconnects = <0x28 0x1b 0x26 0x200 0x26 0x00 0x27 0x229>; | |
| reg-names = "hc"; | |
| no-mmc; | |
| bus-width = <0x04>; | |
| no-sdio; | |
| interrupts = <0x00 0x15e 0x04 0x00 0x161 0x04>; | |
| clocks = <0x1d 0x6f 0x1d 0x70>; | |
| qcom,vdd-io-current-level = <0x00 0x55f0>; | |
| qcom,vdd-io-bias-current-level = <0x00 0x1770>; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| vdd-supply = <0x165>; | |
| compatible = "qcom,sdhci-msm-v5"; | |
| vdd-io-supply = <0x159>; | |
| pinctrl-1 = <0x1e4>; | |
| qcom,vdd-current-level = <0x00 0xc3500>; | |
| status = "ok"; | |
| qcom,dll-hsr-list = <0x7642c 0x00 0x00 0x10800 0x80040868>; | |
| interrupt-names = "hc_irq", "pwr_irq"; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| reg = <0x4784000 0x1000>; | |
| phandle = <0x16b>; | |
| vdd-io-bias-supply = <0x15b>; | |
| operating-points-v2 = <0x39>; | |
| cd-gpios = <0x1f 0x58 0x01>; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; | |
| qcom,iommu-dma = "fastmap"; | |
| qos0 { | |
| mask = <0xf0>; | |
| vote = <0x2c>; | |
| }; | |
| qos1 { | |
| mask = <0x0f>; | |
| vote = <0x2c>; | |
| }; | |
| }; | |
| wsa_ana_clk { | |
| qcom,codec-ext-clk-src = <0x03>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x333>; | |
| qcom,codec-lpass-clk-id = <0x301>; | |
| qcom,codec-lpass-ext-clk-freq = <0x927c00>; | |
| }; | |
| syscon@00340000 { | |
| compatible = "syscon"; | |
| reg = <0x340000 0x20000>; | |
| phandle = <0x61>; | |
| }; | |
| qcom,wdt@f017000 { | |
| qcom,bark-time = <0x2af8>; | |
| reg-names = "wdt-base"; | |
| interrupts = <0x00 0x03 0x01 0x00 0x04 0x04>; | |
| qcom,wakeup-enable; | |
| compatible = "qcom,msm-watchdog"; | |
| qcom,ipi-ping; | |
| qcom,pet-time = <0x2490>; | |
| reg = <0xf017000 0x1000>; | |
| phandle = <0x150>; | |
| }; | |
| ipa_smmu_wlan { | |
| iommus = <0x29 0x141 0x00>; | |
| compatible = "qcom,ipa-smmu-wlan-cb"; | |
| phandle = <0x185>; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| cluster-device3 { | |
| power-domains = <0x18>; | |
| compatible = "qcom,lpm-cluster-dev"; | |
| }; | |
| qcom,mpm2-sleep-counter@4403000 { | |
| clock-frequency = <0x8000>; | |
| compatible = "qcom,mpm2-sleep-counter"; | |
| reg = <0x4403000 0x1000>; | |
| }; | |
| cti@8A02000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x1c 0x08>; | |
| coresight-name = "coresight-cti-mapss"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x8a02000 0x1000>; | |
| phandle = <0x1c7>; | |
| }; | |
| qcom,memlat { | |
| compatible = "qcom,memlat"; | |
| phandle = <0x182>; | |
| ddr { | |
| qcom,miss-ev = <0x17>; | |
| qcom,sampling-path = <0x75>; | |
| compatible = "qcom,memlat-grp"; | |
| qcom,target-dev = <0x74>; | |
| silver { | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x0b 0x0c 0x0d 0x0e>; | |
| compatible = "qcom,memlat-mon"; | |
| ddr4-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x13ec00 0x858b8 0x15aae0 0xbb800 0x1d0d80 0xf84a8 0x1ec300 0x17ba38>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr3-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0xd2f00 0x30d40 0x13ec00 0x6e1b8 0x1b8a00 0xbb800>; | |
| qcom,ddr-type = <0x05>; | |
| }; | |
| }; | |
| silver-compute { | |
| qcom,compute-mon; | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x0b 0x0c 0x0d 0x0e>; | |
| compatible = "qcom,memlat-mon"; | |
| ddr4-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x15aae0 0x858b8 0x1d0d80 0xbb800 0x1ec300 0x17ba38>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr3-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x96000 0x30d40 0x13ec00 0x6e1b8 0x1b8a00 0xbb800>; | |
| qcom,ddr-type = <0x05>; | |
| }; | |
| }; | |
| gold-compute { | |
| qcom,compute-mon; | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x0f 0x10 0x11 0x12>; | |
| compatible = "qcom,memlat-mon"; | |
| ddr4-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x101d00 0x858b8 0x156350 0xbb800 0x1b8a00 0xf84a8 0x1ec300 0x1b86e0 0x203a00 0x1febe0>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr3-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x9f600 0x30d40 0x101d00 0x6e1b8 0x156300 0x858b8 0x177000 0xbb800 0x1ec300 0xe34b8>; | |
| qcom,ddr-type = <0x05>; | |
| }; | |
| }; | |
| gold { | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x0f 0x10 0x11 0x12>; | |
| compatible = "qcom,memlat-mon"; | |
| ddr4-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0xdc500 0x858b8 0x156300 0xf84a8 0x1b8a00 0x17ba38 0x1ec300 0x1b86e0 0x203a00 0x1febe0>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr3-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x101d00 0x30d40 0x156300 0x6e1b8 0x1b8a00 0xbb800 0x1ec300 0xe34b8>; | |
| qcom,ddr-type = <0x05>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| psci { | |
| method = "smc"; | |
| compatible = "arm,psci-1.0"; | |
| cluster-pd3 { | |
| domain-idle-states = <0x1a>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x18>; | |
| }; | |
| cpu-pd3 { | |
| power-domains = <0x13>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x12b>; | |
| }; | |
| cluster-pd1 { | |
| power-domains = <0x15>; | |
| domain-idle-states = <0x17>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x14>; | |
| }; | |
| cpu-pd1 { | |
| power-domains = <0x13>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x129>; | |
| }; | |
| cpu-pd6 { | |
| power-domains = <0x14>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x12d>; | |
| }; | |
| cpu-pd4 { | |
| power-domains = <0x14>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x08>; | |
| }; | |
| cluster-pd2 { | |
| power-domains = <0x18>; | |
| domain-idle-states = <0x19>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x15>; | |
| }; | |
| cpu-pd2 { | |
| power-domains = <0x13>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x12a>; | |
| }; | |
| cluster-pd0 { | |
| power-domains = <0x15>; | |
| domain-idle-states = <0x16>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x13>; | |
| }; | |
| cpu-pd0 { | |
| power-domains = <0x13>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x03>; | |
| }; | |
| cpu-pd7 { | |
| power-domains = <0x14>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x12e>; | |
| }; | |
| cpu-pd5 { | |
| power-domains = <0x14>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x12c>; | |
| }; | |
| }; | |
| idle-states { | |
| cluster-e1 { | |
| entry-latency-us = <0x6c>; | |
| idle-state-name = "cci-ret"; | |
| exit-latency-us = <0x1c2>; | |
| arm,psci-suspend-param = <0x42000043>; | |
| compatible = "domain-idle-state"; | |
| phandle = <0x19>; | |
| min-residency-us = <0x99>; | |
| }; | |
| silver-c3 { | |
| entry-latency-us = <0x129>; | |
| local-timer-stop; | |
| idle-state-name = "pc"; | |
| exit-latency-us = <0x144>; | |
| arm,psci-suspend-param = <0x40000003>; | |
| compatible = "arm,idle-state"; | |
| phandle = <0x02>; | |
| min-residency-us = <0x456>; | |
| }; | |
| gold-c3 { | |
| entry-latency-us = <0x122>; | |
| local-timer-stop; | |
| idle-state-name = "pc"; | |
| exit-latency-us = <0x178>; | |
| arm,psci-suspend-param = <0x40000003>; | |
| compatible = "arm,idle-state"; | |
| phandle = <0x07>; | |
| min-residency-us = <0x49e>; | |
| }; | |
| silver-cluster-d3 { | |
| entry-latency-us = <0x280>; | |
| idle-state-name = "pwr-l2-pc"; | |
| exit-latency-us = <0x680>; | |
| arm,psci-suspend-param = <0x41000043>; | |
| compatible = "domain-idle-state"; | |
| phandle = <0x16>; | |
| min-residency-us = <0x1f9e>; | |
| }; | |
| gold-cluster-d3 { | |
| entry-latency-us = <0x320>; | |
| idle-state-name = "perf-l2-pc"; | |
| exit-latency-us = <0x846>; | |
| arm,psci-suspend-param = <0x41000043>; | |
| compatible = "domain-idle-state"; | |
| phandle = <0x17>; | |
| min-residency-us = <0x1cd0>; | |
| }; | |
| cluster-e3 { | |
| entry-latency-us = <0x2a4f>; | |
| idle-state-name = "cci-pc"; | |
| exit-latency-us = <0x119a>; | |
| arm,psci-suspend-param = <0x42000343>; | |
| compatible = "domain-idle-state"; | |
| phandle = <0x1a>; | |
| min-residency-us = <0x3bea>; | |
| }; | |
| }; | |
| aliases { | |
| i2c1 = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000"; | |
| mmc1 = "/soc/sdhci@4784000"; | |
| swr0 = "/soc/spf_core_platform/bolero-codec/va-macro@a730000/va_swr_master"; | |
| hsuart0 = "/soc/qcom,qupv3_0_geni_se@4ac0000/qcom,qup_uart@4a8c000"; | |
| swr1 = "/soc/spf_core_platform/bolero-codec/rx-macro@a600000/rx_swr_master"; | |
| hsuart1 = "/soc/qcom,qupv3_0_geni_se@4ac0000/qcom,qup_uart@4a80000"; | |
| mmc0 = "/soc/sdhci@4744000"; | |
| phandle = <0x118>; | |
| ufshc1 = "/soc/ufshc@4804000"; | |
| serial0 = "/soc/qcom,qupv3_0_geni_se@4ac0000/qcom,qup_uart@4a90000"; | |
| }; | |
| firmware { | |
| phandle = <0x12f>; | |
| qcom_scm { | |
| compatible = "qcom,scm"; | |
| qcom,dload-mode = <0x1b 0x13000>; | |
| }; | |
| android { | |
| compatible = "android,firmware"; | |
| fstab { | |
| compatible = "android,fstab"; | |
| vendor { | |
| fsmgr_flags = "wait,slotselect,avb"; | |
| mnt_flags = "ro,barrier=1,discard"; | |
| dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; | |
| type = "ext4"; | |
| compatible = "android,vendor"; | |
| status = "disabled"; | |
| }; | |
| }; | |
| vbmeta { | |
| parts = "vbmeta,boot,system,vendor,dtbo,recovery"; | |
| compatible = "android,vbmeta"; | |
| }; | |
| }; | |
| }; | |
| chosen { | |
| linux,initrd-end = <0x00 0x456fe7e4>; | |
| bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node ftrace_dump_on_oops ssbd=force-off disable_dma32=on cgroup.memory=nokmem,nosocket panic=5 video=vfb:640x400,bpp=32,memsize=3072000 bootconfig buildvariant=user audit=0 enforcing=0 androidboot.selinux=permissive audit=0 enforcing=0 androidboot.selinux=permissive msm_drm.dsi_display0=qcom,mdss_dsi_hx83112a_1080p_video: rootwait ro init=/init androidboot.virtualmac=0000000000000000 silent_boot.mode=nonsilent oemboot.info=00000000"; | |
| kaslr-seed = <0x00 0x00>; | |
| linux,initrd-start = <0x00 0x44ded000>; | |
| }; | |
| cpus { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| cpu@1 { | |
| power-domains = <0x03>; | |
| capacity-dmips-mhz = <0x400>; | |
| power-domain-names = "psci"; | |
| qcom,lmh-dcvs = <0x06>; | |
| qcom,freq-domain = <0x05 0x00 0x07>; | |
| cpu-idle-states = <0x02>; | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| dynamic-power-coefficient = <0x64>; | |
| next-level-cache = <0x04>; | |
| reg = <0x00 0x01>; | |
| enable-method = "psci"; | |
| phandle = <0x0c>; | |
| #cooling-cells = <0x02>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x11c>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x11b>; | |
| }; | |
| }; | |
| cpu@103 { | |
| power-domains = <0x08>; | |
| capacity-dmips-mhz = <0x666>; | |
| power-domain-names = "psci"; | |
| qcom,lmh-dcvs = <0x0a>; | |
| qcom,freq-domain = <0x05 0x01 0x07>; | |
| cpu-idle-states = <0x07>; | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| dynamic-power-coefficient = <0x11a>; | |
| next-level-cache = <0x09>; | |
| reg = <0x00 0x103>; | |
| enable-method = "psci"; | |
| phandle = <0x12>; | |
| #cooling-cells = <0x02>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x128>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x127>; | |
| }; | |
| }; | |
| cpu@101 { | |
| power-domains = <0x08>; | |
| capacity-dmips-mhz = <0x666>; | |
| power-domain-names = "psci"; | |
| qcom,lmh-dcvs = <0x0a>; | |
| qcom,freq-domain = <0x05 0x01 0x07>; | |
| cpu-idle-states = <0x07>; | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| dynamic-power-coefficient = <0x11a>; | |
| next-level-cache = <0x09>; | |
| reg = <0x00 0x101>; | |
| enable-method = "psci"; | |
| phandle = <0x10>; | |
| #cooling-cells = <0x02>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x124>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x123>; | |
| }; | |
| }; | |
| cpu-map { | |
| cluster0 { | |
| core3 { | |
| cpu = <0x0e>; | |
| }; | |
| core1 { | |
| cpu = <0x0c>; | |
| }; | |
| core2 { | |
| cpu = <0x0d>; | |
| }; | |
| core0 { | |
| cpu = <0x0b>; | |
| }; | |
| }; | |
| cluster1 { | |
| core3 { | |
| cpu = <0x12>; | |
| }; | |
| core1 { | |
| cpu = <0x10>; | |
| }; | |
| core2 { | |
| cpu = <0x11>; | |
| }; | |
| core0 { | |
| cpu = <0x0f>; | |
| }; | |
| }; | |
| }; | |
| cpu@2 { | |
| power-domains = <0x03>; | |
| capacity-dmips-mhz = <0x400>; | |
| power-domain-names = "psci"; | |
| qcom,lmh-dcvs = <0x06>; | |
| qcom,freq-domain = <0x05 0x00 0x07>; | |
| cpu-idle-states = <0x02>; | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| dynamic-power-coefficient = <0x64>; | |
| next-level-cache = <0x04>; | |
| reg = <0x00 0x02>; | |
| enable-method = "psci"; | |
| phandle = <0x0d>; | |
| #cooling-cells = <0x02>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x11e>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x11d>; | |
| }; | |
| }; | |
| cpu@0 { | |
| power-domains = <0x03>; | |
| capacity-dmips-mhz = <0x400>; | |
| power-domain-names = "psci"; | |
| qcom,lmh-dcvs = <0x06>; | |
| qcom,freq-domain = <0x05 0x00 0x07>; | |
| cpu-idle-states = <0x02>; | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| dynamic-power-coefficient = <0x64>; | |
| next-level-cache = <0x04>; | |
| reg = <0x00 0x00>; | |
| enable-method = "psci"; | |
| phandle = <0x0b>; | |
| #cooling-cells = <0x02>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x04>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x11a>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x119>; | |
| }; | |
| }; | |
| cpu@102 { | |
| power-domains = <0x08>; | |
| capacity-dmips-mhz = <0x666>; | |
| power-domain-names = "psci"; | |
| qcom,lmh-dcvs = <0x0a>; | |
| qcom,freq-domain = <0x05 0x01 0x07>; | |
| cpu-idle-states = <0x07>; | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| dynamic-power-coefficient = <0x11a>; | |
| next-level-cache = <0x09>; | |
| reg = <0x00 0x102>; | |
| enable-method = "psci"; | |
| phandle = <0x11>; | |
| #cooling-cells = <0x02>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x126>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x125>; | |
| }; | |
| }; | |
| cpu@100 { | |
| power-domains = <0x08>; | |
| capacity-dmips-mhz = <0x666>; | |
| power-domain-names = "psci"; | |
| qcom,lmh-dcvs = <0x0a>; | |
| qcom,freq-domain = <0x05 0x01 0x07>; | |
| cpu-idle-states = <0x07>; | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| dynamic-power-coefficient = <0x11a>; | |
| next-level-cache = <0x09>; | |
| reg = <0x00 0x100>; | |
| enable-method = "psci"; | |
| phandle = <0x0f>; | |
| #cooling-cells = <0x02>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x09>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x122>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x121>; | |
| }; | |
| }; | |
| cpu@3 { | |
| power-domains = <0x03>; | |
| capacity-dmips-mhz = <0x400>; | |
| power-domain-names = "psci"; | |
| qcom,lmh-dcvs = <0x06>; | |
| qcom,freq-domain = <0x05 0x00 0x07>; | |
| cpu-idle-states = <0x02>; | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| dynamic-power-coefficient = <0x64>; | |
| next-level-cache = <0x04>; | |
| reg = <0x00 0x03>; | |
| enable-method = "psci"; | |
| phandle = <0x0e>; | |
| #cooling-cells = <0x02>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x120>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x11f>; | |
| }; | |
| }; | |
| }; | |
| __symbols__ { | |
| funnel_in1_in_tpda_mapss = "/soc/funnel@8042000/in-ports/port@1/endpoint"; | |
| funnel_turing_in_turing_etm0 = "/soc/funnel@8861000/in-ports/port@1/endpoint"; | |
| smmu_sde_unsec = "/soc/qcom,smmu_sde_unsec_cb"; | |
| smp2p_rdbg5_out = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-out"; | |
| quat_tdm_sd2_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sd2/quat_tdm_sd2_sleep"; | |
| tpdm_dcc_out_tpda8 = "/soc/tpdm@8870000/out-ports/port/endpoint"; | |
| cdsp_smp2p_in = "/soc/qcom,smp2p-cdsp/slave-kernel"; | |
| cti3 = "/soc/cti@8013000"; | |
| qcom_memlat = "/soc/qcom,memlat"; | |
| pm6125_l17 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa17/regulator-l17"; | |
| funnel_apss0_in_etm2 = "/soc/funnel@9800000/in-ports/port@2/endpoint"; | |
| qupv3_se2_i2c_sleep = "/soc/pinctrl@400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sleep"; | |
| quat_mi2s_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_ws/quat_mi2s_ws_sleep"; | |
| sdc1_on = "/soc/pinctrl@400000/sdc1_on"; | |
| ddr_freq_table = "/soc/ddr-freq-table"; | |
| wsa_mclk_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/wsa_mclk_sleep"; | |
| lpi_tdm3_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; | |
| cdsp_cx_mon = "/soc/thermal-zones/cdsp-hvx/trips/cdsp-cx-mon"; | |
| pm6125_pwm = "/soc/qcom,spmi@1c40000/qcom,pm6125@1/qcom,pwms@b300"; | |
| cpu5_config = "/soc/thermal-zones/cpu-1-1/trips/cpu5-config"; | |
| pm6125_gpios = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/pinctrl@c000"; | |
| etm7 = "/soc/etm@9740000"; | |
| tpda_apss_in_tpdm_apss = "/soc/tpda@9862000/in-ports/port@0/endpoint"; | |
| cdsp_sec_mem = "/reserved-memory/cdsp_sec_regions@46200000"; | |
| msm_cdsp_rm = "/soc/remoteproc-cdsp@b300000/glink-edge/qcom,msm_cdsprm_rpmsg/qcom,msm_cdsp_rm"; | |
| lpi_tdm3_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; | |
| quat_tdm_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_ws/quat_tdm_ws_active"; | |
| cti_wcss_cti1 = "/soc/cti@89A5000"; | |
| quat_mi2s_sd3_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; | |
| thermal_zones = "/soc/thermal-zones"; | |
| intc = "/soc/interrupt-controller@f200000"; | |
| pm6125_s8 = "/soc/qcom,rpm-smd/rpm-regulator-smpa8/regulator-s8"; | |
| va_md_mem = "/reserved-memory/va_md_mem_region"; | |
| gpu_gx_gdsc = "/soc/qcom,gdsc@599100c"; | |
| cdsp_trip0 = "/soc/thermal-zones/cdsp-hvx/trips/cdsp-trip0"; | |
| L1_I_100 = "/cpus/cpu@100/l1-icache"; | |
| adsp_smp2p_in = "/soc/qcom,smp2p-adsp/slave-kernel"; | |
| qupv3_se4_2uart_pins = "/soc/pinctrl@400000/qupv3_se4_2uart_pins"; | |
| lpi_i2s3_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s3_sck/lpi_i2s3_sck_active"; | |
| L1A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa1/regulator-l1"; | |
| APSS_WFI = "/idle-states/cluster-e1"; | |
| CPU_PD1 = "/psci/cpu-pd1"; | |
| rx_swr_clk_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/rx_swr_clk_active"; | |
| lpi_tdm2_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; | |
| cdc_dmic01_data_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/dmic01_data_active"; | |
| swao_csr = "/soc/csr@8a03000"; | |
| cdsp_sw = "/soc/qmi-tmd-devices/cdsp/cdsp"; | |
| pm6125_s3_level_ao = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level-ao"; | |
| bengal_snd = "/soc/spf_core_platform/sound"; | |
| quat_aux_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sck/quat_aux_sck_active"; | |
| mdss_dsi0 = "/soc/qcom,mdss_dsi_ctrl0@5e94000"; | |
| audio_etm0_out_funnel_lpass_lpi = "/soc/audio_etm0/out-ports/port/endpoint"; | |
| replicator_qdss_out_tmc_etr = "/soc/replicator@8046000/out-ports/port@0/endpoint"; | |
| qupv3_se2_spi_sleep = "/soc/pinctrl@400000/qupv3_se2_spi_pins/qupv3_se2_spi_sleep"; | |
| L7P = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9/qcom,pm8008-regulator/qcom,pm8008-l7@4400"; | |
| pm6125_s5_level = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-level"; | |
| snoc = "/soc/snoc"; | |
| lpi_i2s3_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; | |
| kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@59a0000"; | |
| gcc_usb30_prim_gdsc = "/soc/qcom,gdsc@141a004"; | |
| lpi_i2s3_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s3_ws/lpi_i2s3_ws_active"; | |
| qupv3_se3_4uart_pins = "/soc/pinctrl@400000/qupv3_se3_4uart_pins"; | |
| cti10 = "/soc/cti@801a000"; | |
| cpu6_config = "/soc/thermal-zones/cpu-1-2/trips/cpu6-config"; | |
| modem_vdd = "/soc/qmi-tmd-devices/modem/modem_vdd"; | |
| lmh_dcvs1 = "/soc/qcom,limits-1-dcvs@f550800"; | |
| tsens0 = "/soc/tsens@c222000"; | |
| funnel_merg_out_tmc_etf = "/soc/funnel@8045000/out-ports/port@0/endpoint"; | |
| quat_aux_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sd0/quat_aux_sd0_active"; | |
| audio_cma_mem = "/reserved-memory/audio_cma_region"; | |
| qupv3_se4_2uart = "/soc/qcom,qupv3_0_geni_se@4ac0000/qcom,qup_uart@4a90000"; | |
| va_macro = "/soc/spf_core_platform/bolero-codec/va-macro@a730000"; | |
| CLUSTER_PD1 = "/psci/cluster-pd1"; | |
| pil_gpu_mem = "/reserved-memory/gpu_region@55615000"; | |
| ts_int_suspend = "/soc/pinctrl@400000/pmx_ts_int_suspend/ts_int_suspend"; | |
| cpu7_pause = "/soc/qcom,cpu-pause/cpu7-pause"; | |
| cpu4_hotplug = "/soc/qcom,cpu-hotplug/cpu4-hotplug"; | |
| lpi_aux3_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux3_ws/lpi_aux3_ws_active"; | |
| cam_sensor_csi_mux_oe_active = "/soc/pinctrl@400000/cam_sensor_csi_mux_oe_active"; | |
| L6P = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9/qcom,pm8008-regulator/qcom,pm8008-l6@4400"; | |
| lpi_i2s2_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; | |
| tpda_llm_silver = "/soc/tpda@98c0000"; | |
| tpda13_in_tpdm_west = "/soc/tpda@8004000/in-ports/port@13/endpoint"; | |
| VDD_CX_LEVEL_AO = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level-ao"; | |
| qcom_ddr_dcvs_hw = "/soc/qcom,dcvs/ddr"; | |
| etm6_out_funnel_apss0 = "/soc/etm@9640000/out-ports/port/endpoint"; | |
| xo_board = "/soc/clocks/xo_board"; | |
| VDD_MX_LEVEL_AO = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-level-ao"; | |
| ipa_smmu_uc = "/soc/ipa_smmu_uc"; | |
| qupv3_se0_i2c = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a80000"; | |
| qupv3_se2_i2c_pins = "/soc/pinctrl@400000/qupv3_se2_i2c_pins"; | |
| cti1 = "/soc/cti@8011000"; | |
| pm6125_l15 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa15/regulator-l15"; | |
| L1_D_103 = "/cpus/cpu@103/l1-dcache"; | |
| SILVER_CLUSTER_D3 = "/idle-states/silver-cluster-d3"; | |
| funnel_apss0_in_etm0 = "/soc/funnel@9800000/in-ports/port@0/endpoint"; | |
| lpi_aux2_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; | |
| VDD_MX_FLOOR_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-floor-level"; | |
| cx_ipeak_lm = "/soc/cx_ipeak@3ed000"; | |
| lpi_i2s3_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; | |
| smmu_rot_unsec = "/soc/qcom,mdss_rotator/qcom,smmu_rot_unsec_cb"; | |
| qupv3_se2_spi = "/soc/qcom,qupv3_0_geni_se@4ac0000/spi@4a88000"; | |
| L5P = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9/qcom,pm8008-regulator/qcom,pm8008-l5@4400"; | |
| cti_dlct_cti2 = "/soc/cti@8B5B000"; | |
| funnel_apss1_in_tpda_actpm = "/soc/funnel@9810000/in-ports/port@2/endpoint"; | |
| cti_cortex_M3 = "/soc/cti@8B30000"; | |
| etm5 = "/soc/etm@9540000"; | |
| sde_te_suspend = "/soc/pinctrl@400000/pmx_sde_te/sde_te_suspend"; | |
| etm4_out_funnel_apss0 = "/soc/etm@9440000/out-ports/port/endpoint"; | |
| lpi_tdm1_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm1_sck/lpi_tdm1_sck_active"; | |
| rx_swr_clk_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/rx_swr_clk_sleep"; | |
| cdc_dmic01_data_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/dmic01_data_sleep"; | |
| L24A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa24/regulator-l24"; | |
| sleepstate_smp2p_out = "/soc/qcom,smp2p-adsp/sleepstate-out"; | |
| quat_aux_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sd0/quat_aux_sd0_sleep"; | |
| vendor_hooks = "/soc/qcom,cpu-vendor-hooks"; | |
| quat_aux_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sd1/quat_aux_sd1_active"; | |
| pm6125_s6 = "/soc/qcom,rpm-smd/rpm-regulator-smpa6/regulator-s6"; | |
| funnel_lpass_lpi = "/soc/funnel@8a24000"; | |
| funnel_apss1_in_funnel_apss0 = "/soc/funnel@9810000/in-ports/port@0/endpoint"; | |
| va_swr_gpios = "/soc/spf_core_platform/va_swr_clk_data_pinctrl"; | |
| mx_cdev = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/mx-cdev-lvl"; | |
| cam_sensor_csi_mux_oe_suspend = "/soc/pinctrl@400000/cam_sensor_csi_mux_oe_suspend"; | |
| funnel_gpu = "/soc/funnel@8944000"; | |
| cam_sensor_rear1_reset_active = "/soc/pinctrl@400000/cam_sensor_rear1_reset_active"; | |
| rx_swr_data1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/rx_swr_data1_active"; | |
| jtag_mm6 = "/soc/jtagmm@9640000"; | |
| L4P = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9/qcom,pm8008-regulator/qcom,pm8008-l4@4300"; | |
| tpda_mapss_in_tpdm_mapss = "/soc/tpda@8a04000/in-ports/port@0/endpoint"; | |
| cxip_cdev = "/soc/cxip-cdev@3ed000"; | |
| sdc2_off = "/soc/pinctrl@400000/sdc2_off"; | |
| lpi_tdm1_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; | |
| funnel_merg = "/soc/funnel@8045000"; | |
| removed_mem = "/reserved-memory/removed_region@60000000"; | |
| etm2_out_funnel_apss0 = "/soc/etm@9240000/out-ports/port/endpoint"; | |
| dfps_data_memory = "/reserved-memory/dfps_data_region@5cf00000"; | |
| cdsp_tbu = "/soc/apps-smmu@0xc600000/cdsp_tbu@0xc791000"; | |
| L23A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa23/regulator-l23"; | |
| ts_reset_suspend = "/soc/pinctrl@400000/pmx_ts_reset_suspend/ts_reset_suspend"; | |
| adsp_smp2p_out = "/soc/qcom,smp2p-adsp/master-kernel"; | |
| modem_pas = "/soc/remoteproc-mss@6080000"; | |
| silv_cpus_config = "/soc/thermal-zones/cpuss-2/trips/silv-cpus-config"; | |
| smem = "/soc/qcom,smem"; | |
| VDD_MSS_FLOOR_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-floor-level"; | |
| cam_sensor_rear2_reset_suspend = "/soc/pinctrl@400000/cam_sensor_rear2_reset_suspend"; | |
| tmc_etr = "/soc/tmc@8048000"; | |
| stm = "/soc/stm@8002000"; | |
| pm6125_l23 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa23/regulator-l23"; | |
| L3P = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9/qcom,pm8008-regulator/qcom,pm8008-l3@4200"; | |
| funnel_qatb_in_tpda = "/soc/funnel@8005000/in-ports/port@0/endpoint"; | |
| ts_int_active = "/soc/pinctrl@400000/pmx_ts_int_active/ts_int_active"; | |
| tpdm_actpm_out_tpda_actpm = "/soc/tpd@9830000/out-ports/port/endpoint"; | |
| L2_1 = "/cpus/cpu@100/l2-cache"; | |
| etm0_out_funnel_apss0 = "/soc/etm@9040000/out-ports/port/endpoint"; | |
| quat_aux_sd2_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sd2/quat_aux_sd2_active"; | |
| lpi_i2s2_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; | |
| L22A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa22/regulator-l22"; | |
| system_cma = "/reserved-memory/linux,cma"; | |
| mem_client_3_size = "/soc/qcom,memshare/qcom,client_3"; | |
| quat_aux_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_ws/quat_aux_ws_sleep"; | |
| tpda_apss = "/soc/tpda@9862000"; | |
| gpi_dma0 = "/soc/qcom,gpi-dma@4a00000"; | |
| qseecom_mem = "/reserved-memory/qseecom_region"; | |
| qfprom = "/soc/qfprom@1b40000"; | |
| qupv3_se2_spi_pins = "/soc/pinctrl@400000/qupv3_se2_spi_pins"; | |
| stm_out_funnel_in0 = "/soc/stm@8002000/out-ports/port/endpoint"; | |
| tpdm_dl_ct_out_tpda0 = "/soc/tpdm@8b58000/out-ports/port/endpoint"; | |
| quat_mi2s_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; | |
| L1_D_3 = "/cpus/cpu@3/l1-dcache"; | |
| funnel_in1_in_modem_etm0 = "/soc/funnel@8042000/in-ports/port@4/endpoint"; | |
| pm6125_l13 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa13/regulator-l13"; | |
| lpi_tdm1_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; | |
| L2P = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9/qcom,pm8008-regulator/qcom,pm8008-l2@4100"; | |
| L1_D_101 = "/cpus/cpu@101/l1-dcache"; | |
| tpdm_prng = "/soc/tpdm@884c000"; | |
| lpi_tdm2_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm2_ws/lpi_tdm2_ws_active"; | |
| cpu6_7_config = "/soc/thermal-zones/cpuss-1/trips/cpu-6-7-config"; | |
| lpi_tdm3_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; | |
| qupv3_se0_i2c_sleep = "/soc/pinctrl@400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sleep"; | |
| L21A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa21/regulator-l21"; | |
| qupv3_se5_i2c_sleep = "/soc/pinctrl@400000/qupv3_se5_i2c_pins/qupv3_se5_i2c_sleep"; | |
| rx_macro = "/soc/spf_core_platform/bolero-codec/rx-macro@a600000"; | |
| swr0 = "/soc/spf_core_platform/bolero-codec/va-macro@a730000/va_swr_master"; | |
| cti_dlct_cti0 = "/soc/cti@8B59000"; | |
| etm3 = "/soc/etm@9340000"; | |
| cpu6_hotplug = "/soc/qcom,cpu-hotplug/cpu6-hotplug"; | |
| qseecom_ta_mem = "/reserved-memory/qseecom_ta_region"; | |
| tpda_out_funnel_qatb = "/soc/tpda@8004000/out-ports/port@0/endpoint"; | |
| lpi_aux3_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux3_sck/lpi_aux3_sck_active"; | |
| smp2p_rdbg2_out = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-out"; | |
| lpi_tdm1_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; | |
| dispcc = "/soc/clock-controller@5f00000"; | |
| lpi_i2s1_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s1_sck/lpi_i2s1_sck_active"; | |
| pm6125_trip0 = "/soc/thermal-zones/pm6125-tz/trips/trip0"; | |
| L1_I_2 = "/cpus/cpu@2/l1-icache"; | |
| lmh_cpu_vdd = "/soc/qcom,lmh-cpu-vdd@f550800"; | |
| L1P = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9/qcom,pm8008-regulator/qcom,pm8008-l1@4000"; | |
| pm8008_9 = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9"; | |
| cti_apss_cti1 = "/soc/cti@98F0000"; | |
| bolero_cdc = "/soc/spf_core_platform/bolero-codec"; | |
| smp2p_ipa_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-in"; | |
| quat_aux_sd3_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sd3/quat_aux_sd3_active"; | |
| L20A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa20/regulator-l20"; | |
| mdss_dsi_phy0 = "/soc/qcom,mdss_dsi_phy0@5e94400"; | |
| pm8008_active = "/soc/pinctrl@400000/pm8008_active"; | |
| jtag_mm4 = "/soc/jtagmm@9440000"; | |
| qcom_smcinvoke = "/soc/smcinvoke@61800000"; | |
| sde_dsi_suspend = "/soc/pinctrl@400000/pmx_sde/sde_dsi_suspend"; | |
| rpm_bus = "/soc/qcom,rpm-smd"; | |
| sdhc_2 = "/soc/sdhci@4784000"; | |
| pm6125_l9 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa9/regulator-l9"; | |
| lpi_aux3_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux3_sd0/lpi_aux3_sd0_active"; | |
| lpi_i2s1_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; | |
| CPU6 = "/cpus/cpu@102"; | |
| tpdm_turing = "/soc/tpdm@8860000"; | |
| tpda_actpm = "/soc/tpda@9832000"; | |
| cpu4_pause = "/soc/qcom,cpu-pause/cpu4-pause"; | |
| qupv3_se3_cts = "/soc/pinctrl@400000/qupv3_se3_4uart_pins/qupv3_se3_cts"; | |
| qupv3_se0_spi_sleep = "/soc/pinctrl@400000/qupv3_se0_spi_pins/qupv3_se0_spi_sleep"; | |
| smp2p_ipa_1_out = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-out"; | |
| funnel_apss0 = "/soc/funnel@9800000"; | |
| VDD_CX_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level"; | |
| qupv3_se5_spi_sleep = "/soc/pinctrl@400000/qupv3_se5_spi_pins/qupv3_se5_spi_sleep"; | |
| funnel_turing_out_tpda5 = "/soc/funnel@8861000/out-ports/port@0/endpoint"; | |
| tcsr_mutex = "/soc/hwlock"; | |
| funnel_apss1_in_tpda_apss = "/soc/funnel@9810000/in-ports/port@4/endpoint"; | |
| cti8 = "/soc/cti@8018000"; | |
| lpi_tdm3_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; | |
| pm6125_l21 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa21/regulator-l21"; | |
| lpi_i2s1_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s1_ws/lpi_i2s1_ws_active"; | |
| funnel_apss0_in_etm7 = "/soc/funnel@9800000/in-ports/port@7/endpoint"; | |
| lpi_i2s2_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; | |
| tpda_mapss_out_funnel_in1 = "/soc/tpda@8a04000/out-ports/port@0/endpoint"; | |
| tpda0_in_tpdm_dl_ct = "/soc/tpda@8004000/in-ports/port@0/endpoint"; | |
| wlan_msa_mem = "/reserved-memory/wlan_msa_region@51900000"; | |
| tpda1_in_funnel_gpu = "/soc/tpda@8004000/in-ports/port@1/endpoint"; | |
| SILVER_OFF = "/idle-states/silver-c3"; | |
| quat_tdm_sd3_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sd3/quat_tdm_sd3_sleep"; | |
| tpda_mapss = "/soc/tpda@8a04000"; | |
| adsp_mem = "/reserved-memory/adsp_region"; | |
| tpda_apss_out_funnel_apss1 = "/soc/tpda@9862000/out-ports/port@0/endpoint"; | |
| modem_proc = "/soc/qmi-tmd-devices/modem/modem_proc"; | |
| lpi_aux1_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux1_ws/lpi_aux1_ws_active"; | |
| pm6125_s5_floor_level = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-floor-level"; | |
| lpi_aux2_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux2_sck/lpi_aux2_sck_sleep"; | |
| pm8008_chip = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@8/qcom,pm8008-chip@900"; | |
| modem_wlan = "/soc/qmi-tmd-devices/modem/modem_wlan"; | |
| cam_sensor_mclk1_suspend = "/soc/pinctrl@400000/cam_sensor_mclk1_suspend"; | |
| cti_mss_q6 = "/soc/cti@8833000"; | |
| L19A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa19/regulator-l19"; | |
| tpdm_center = "/soc/tpdm@8b58000"; | |
| L1_D_1 = "/cpus/cpu@1/l1-dcache"; | |
| VDD_MSS_LEVEL_AO = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level-ao"; | |
| pm6125_l11 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa11/regulator-l11"; | |
| cam_sensor_rear0_reset_suspend = "/soc/pinctrl@400000/cam_sensor_rear0_reset_suspend"; | |
| cpufreq_hw = "/soc/qcom,cpufreq-hw"; | |
| funnel_lpass_lpi_in_audio_etm0 = "/soc/funnel@8a24000/in-ports/port@0/endpoint"; | |
| lpi_aux3_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux3_sd1/lpi_aux3_sd1_active"; | |
| rpmcc = "/soc/qcom,rpmcc"; | |
| qcom_rng = "/soc/qrng@1b53000"; | |
| lpi_i2s1_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; | |
| adsp_vdd = "/soc/qmi-tmd-devices/adsp/adsp_vdd"; | |
| adsp_notify = "/soc/qcom,msm-adsp-notify"; | |
| lpi_tdm3_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; | |
| gpu_step_trip = "/soc/thermal-zones/gpu/trips/gpu-trip"; | |
| CPU_PD6 = "/psci/cpu-pd6"; | |
| tpdm_apss = "/soc/tpdm@9860000"; | |
| quat_aux_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sck/quat_aux_sck_sleep"; | |
| funnel_turing_in_tpdm_turing = "/soc/funnel@8861000/in-ports/port@0/endpoint"; | |
| tpda = "/soc/tpda@8004000"; | |
| mpm = "/soc/interrupt-controller@45f01b8"; | |
| etm1 = "/soc/etm@9140000"; | |
| tpda7_in_tpdm_vsense = "/soc/tpda@8004000/in-ports/port@7/endpoint"; | |
| S3A_FLOOR_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-floor-level"; | |
| funnel_merg_in_funnel_in1 = "/soc/funnel@8045000/in-ports/port@1/endpoint"; | |
| pm6125_s3_floor_level = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-floor-level"; | |
| L18A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa18/regulator-l18"; | |
| qupv3_se3_4uart = "/soc/qcom,qupv3_0_geni_se@4ac0000/qcom,qup_uart@4a8c000"; | |
| tpdm_lpass_out_funnel_lpass_lpi = "/soc/tpdm@8a26000/out-ports/port/endpoint"; | |
| L1_I_0 = "/cpus/cpu@0/l1-icache"; | |
| apcs_glb = "/soc/mailbox@0f111000"; | |
| smmu_rot_sec = "/soc/qcom,mdss_rotator/qcom,smmu_rot_sec_cb"; | |
| APSS_OFF = "/idle-states/cluster-e3"; | |
| tmc_etf_out_replicator_qdss = "/soc/tmc@8047000/out-ports/port@0/endpoint"; | |
| cti15 = "/soc/cti@801f000"; | |
| tpdm_vsense_out_tpda7 = "/soc/tpdm@8840000/out-ports/port/endpoint"; | |
| jtag_mm2 = "/soc/jtagmm@9240000"; | |
| qupv3_0 = "/soc/qcom,qupv3_0_geni_se@4ac0000"; | |
| cdc_dmic23_gpios = "/soc/spf_core_platform/cdc_dmic23_pinctrl"; | |
| pm6125_l7 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa7/regulator-l7"; | |
| qupv3_se2_spi_active = "/soc/pinctrl@400000/qupv3_se2_spi_pins/qupv3_se2_spi_active"; | |
| pil_ipa_gsi_mem = "/reserved-memory/ipa_gsi_region@55610000"; | |
| tmc_etf = "/soc/tmc@8047000"; | |
| mm_rt_tbu = "/soc/apps-smmu@0xc600000/mm_rt_tbu@0xc789000"; | |
| CPU4 = "/cpus/cpu@100"; | |
| config_noc = "/soc/interconnect@1900000"; | |
| L17A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa17/regulator-l17"; | |
| kgsl_smmu = "/soc/kgsl-smmu@0x59a0000"; | |
| cti_isdb_gpu = "/soc/cti@8941000"; | |
| gcc_venus_gdsc = "/soc/qcom,gdsc@145807c"; | |
| funnel_in0 = "/soc/funnel@8041000"; | |
| tcsr_mutex_block = "/soc/syscon@00340000"; | |
| soc = "/soc"; | |
| rx_swr_data_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/rx_swr_data_active"; | |
| qupv3_se1_i2c = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000"; | |
| modem_smp2p_out = "/soc/qcom,smp2p-modem/master-kernel"; | |
| mm_nrt_tbu = "/soc/apps-smmu@0xc600000/mm_nrt_tbu@0xc78d000"; | |
| bwmon_ddr = "/soc/qcom,bwmon-ddr@01b8e200"; | |
| cx_cdev = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/cx-cdev-lvl"; | |
| cti6 = "/soc/cti@8016000"; | |
| qupv3_se1_i2c_active = "/soc/pinctrl@400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_active"; | |
| funnel_apss0_in_etm5 = "/soc/funnel@9800000/in-ports/port@5/endpoint"; | |
| lpi_i2s2_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; | |
| turing_etm0_out_funnel_turing = "/soc/turing_etm0/out-ports/port/endpoint"; | |
| pm6125_l2_level = "/soc/qcom,rpm-smd/rpm-regulator-ldoa2/regulator-l2-level"; | |
| wcd937x_reset_active = "/soc/pinctrl@400000/wcd937x_reset_active"; | |
| qupv3_se4_2uart_sleep = "/soc/pinctrl@400000/qupv3_se4_2uart_pins/qupv3_se4_2uart_sleep"; | |
| mccc_debug = "/soc/syscon@447d200"; | |
| L16A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa16/regulator-l16"; | |
| quat_mi2s_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sck/quat_mi2s_sck_sleep"; | |
| spmi_bus = "/soc/qcom,spmi@1c40000"; | |
| lpi_aux2_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; | |
| tpda12_in_tpdm_qm = "/soc/tpda@8004000/in-ports/port@12/endpoint"; | |
| adsp_pas = "/soc/remoteproc-adsp@ab00000"; | |
| cpu1_hotplug = "/soc/qcom,cpu-hotplug/cpu1-hotplug"; | |
| qupv3_se5_i2c = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a94000"; | |
| modem_pa = "/soc/qmi-tmd-devices/modem/modem_pa"; | |
| L1_I_103 = "/cpus/cpu@103/l1-icache"; | |
| gpu_speed_bin = "/soc/qfprom@1b40000/gpu_speed_bin@6006"; | |
| tpdm_gpu = "/soc/tpdm@8940000"; | |
| lpi_i2s3_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; | |
| S3A_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level"; | |
| L15A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa15/regulator-l15"; | |
| CPU_PD4 = "/psci/cpu-pd4"; | |
| cti_mapss = "/soc/cti@8A02000"; | |
| lpi_tdm1_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; | |
| feat_conf5 = "/soc/qfprom@1b40000/feat_conf5@6018"; | |
| quat_aux_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sd1/quat_aux_sd1_sleep"; | |
| pm6125_misc = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/qcom,misc@900"; | |
| lpi_aux1_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux1_sck/lpi_aux1_sck_active"; | |
| qupv3_se0_2uart_pins = "/soc/pinctrl@400000/qupv3_se0_2uart_pins"; | |
| cci1_suspend = "/soc/pinctrl@400000/cci1_suspend"; | |
| funnel_qatb = "/soc/funnel@8005000"; | |
| gfx_0_tbu = "/soc/kgsl-smmu@0x59a0000/gfx_0_tbu@0x59c5000"; | |
| cam_sensor_mclk3_suspend = "/soc/pinctrl@400000/cam_sensor_mclk3_suspend"; | |
| cpu1_pause = "/soc/qcom,cpu-pause/cpu1-pause"; | |
| modem_smp2p_in = "/soc/qcom,smp2p-modem/slave-kernel"; | |
| qcom_crypto = "/soc/qcrypto@1b20000"; | |
| cti13 = "/soc/cti@801d000"; | |
| rx_swr_data_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/rx_swr_data_sleep"; | |
| GOLD_OFF = "/idle-states/gold-c3"; | |
| tpda15_in_tpdm_pimem = "/soc/tpda@8004000/in-ports/port@15/endpoint"; | |
| smem_mem = "/reserved-memory/smem_region@46000000"; | |
| L14A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa14/regulator-l14"; | |
| jtag_mm0 = "/soc/jtagmm@9040000"; | |
| lpi_aux1_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux1_sd0/lpi_aux1_sd0_active"; | |
| smmu_sde_sec = "/soc/qcom,smmu_sde_sec_cb"; | |
| pm6125_l5 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa5/regulator-l5"; | |
| qupv3_se0_2uart_sleep = "/soc/pinctrl@400000/qupv3_se0_2uart_pins/qupv3_se0_2uart_sleep"; | |
| wsa881x_analog_clk_gpio = "/soc/spf_core_platform/msm_cdc_pinctrl@18"; | |
| gpu_cx_hw_ctrl = "/soc/syscon@5991540"; | |
| dsi_pll_codes_data = "/soc/dsi_pll_codes"; | |
| CPU2 = "/cpus/cpu@2"; | |
| cpu_pmu = "/soc/cpu-pmu"; | |
| dcc = "/soc/dcc_v2@1be2000"; | |
| hyp_mem = "/reserved-memory/hyp_region@45700000"; | |
| quat_tdm_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sd0/quat_tdm_sd0_sleep"; | |
| hlos1_vote_turing_mmu_tbu1_gdsc = "/soc/qcom,gdsc@147d060"; | |
| funnel_lpass_lpi_in_tpdm_lpass = "/soc/funnel@8a24000/in-ports/port@5/endpoint"; | |
| pm6125_tz = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/qcom,temp-alarm@2400"; | |
| cam_sensor_rear2_reset_active = "/soc/pinctrl@400000/cam_sensor_rear2_reset_active"; | |
| L13A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa13/regulator-l13"; | |
| modem_etm0_out_funnel_in1 = "/soc/modem_etm0/out-ports/port/endpoint"; | |
| cti4 = "/soc/cti@8014000"; | |
| pm6125_l18 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa18/regulator-l18"; | |
| mdss_mdp = "/soc/qcom,mdss_mdp"; | |
| funnel_apss0_in_etm3 = "/soc/funnel@9800000/in-ports/port@3/endpoint"; | |
| tpda_llm_silver_in_tpdm_llm_silver = "/soc/tpda@98c0000/in-ports/port@0/endpoint"; | |
| mdss_rotator = "/soc/qcom,mdss_rotator"; | |
| tb_trig1_on = "/soc/pinctrl@400000/tb_trig1_on"; | |
| quat_mi2s_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; | |
| mmrt_virt = "/soc/interconnect@1"; | |
| modem_etm0 = "/soc/modem_etm0"; | |
| tpda_actpm_out_funnel_apss1 = "/soc/tpda@9832000/out-ports/port@0/endpoint"; | |
| pil_ipa_fw_mem = "/reserved-memory/ipa_fw_region@55600000"; | |
| smp2p_rdbg5_in = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-in"; | |
| cti_wcss_cti2 = "/soc/cti@89A6000"; | |
| funnel_in0_in_snoc = "/soc/funnel@8041000/in-ports/port@5/endpoint"; | |
| pm6125_vadc = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/vadc@3100"; | |
| funnel_turing_out_funnel_qatb = "/soc/funnel@8861000/out-ports/port@1/endpoint"; | |
| lpi_aux1_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux1_sd1/lpi_aux1_sd1_active"; | |
| L12A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa12/regulator-l12"; | |
| qupv3_se0_2uart_active = "/soc/pinctrl@400000/qupv3_se0_2uart_pins/qupv3_se0_2uart_active"; | |
| lpi_tlmm = "/soc/spf_core_platform/lpi_pinctrl@ac40000"; | |
| pm6125_s5_level_ao = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-level-ao"; | |
| lpi_i2s3_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; | |
| ufsphy_mem = "/soc/ufsphy_mem@4807000"; | |
| qupv3_se3_rts = "/soc/pinctrl@400000/qupv3_se3_4uart_pins/qupv3_se3_rts"; | |
| funnel_gpu_out_tpda1 = "/soc/funnel@8944000/out-ports/port@0/endpoint"; | |
| cdsp_pas = "/soc/remoteproc-cdsp@b300000"; | |
| cdsp_trip1 = "/soc/thermal-zones/cdsp-hvx/trips/cdsp-trip1"; | |
| L1_I_101 = "/cpus/cpu@101/l1-icache"; | |
| rx_swr_gpios = "/soc/spf_core_platform/rx_swr_clk_data_pinctrl"; | |
| ipa_smmu_ap = "/soc/ipa_smmu_ap"; | |
| CPU_PD2 = "/psci/cpu-pd2"; | |
| smp2p_rdbg2_in = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-in"; | |
| lpi_tdm1_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; | |
| S5A_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-level"; | |
| cam_sensor_mclk0_active = "/soc/pinctrl@400000/cam_sensor_mclk0_active"; | |
| pm6125_clkdiv = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/clock-controller@5b00"; | |
| msm_audio_ion_cma = "/soc/spf_core_platform/qcom,msm-audio-ion-cma"; | |
| lpi_aux3_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; | |
| pm6125_s3_level = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level"; | |
| cam_sensor_csi_mux_sel_active = "/soc/pinctrl@400000/cam_sensor_csi_mux_sel_active"; | |
| pm6125_adc_tm_iio = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/adc_tm@3400"; | |
| feat_conf10 = "/soc/qfprom@1b40000/feat_conf10@602c"; | |
| lpi_aux1_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux1_ws/lpi_aux1_ws_sleep"; | |
| L11A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa11/regulator-l11"; | |
| emmc_therm_default = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/pinctrl@c000/emmc_therm/emmc_therm_default"; | |
| camera_therm_default = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/pinctrl@c000/camera_therm/camera_therm_default"; | |
| S8A = "/soc/qcom,rpm-smd/rpm-regulator-smpa8/regulator-s8"; | |
| funnel_in0_in_funnel_qatb = "/soc/funnel@8041000/in-ports/port@6/endpoint"; | |
| cpu3_hotplug = "/soc/qcom,cpu-hotplug/cpu3-hotplug"; | |
| cti11 = "/soc/cti@801b000"; | |
| sdhc1_opp_table = "/soc/sdhc1-opp-table"; | |
| qupv3_se0_spi_active = "/soc/pinctrl@400000/qupv3_se0_spi_pins/qupv3_se0_spi_active"; | |
| cdc_dmic23_clk_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/dmic23_clk_active"; | |
| pm8008_gpio1_active = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@8/pinctrl@c000/pm8008_gpio1_active"; | |
| cpu5_pause = "/soc/qcom,cpu-pause/cpu5-pause"; | |
| lpi_tdm2_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm2_sck/lpi_tdm2_sck_active"; | |
| cdc_dmic23_clk_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/dmic23_clk_sleep"; | |
| eud = "/soc/qcom,msm-eud@1610000"; | |
| CLUSTER_PD2 = "/psci/cluster-pd2"; | |
| gcc = "/soc/clock-controller@1400000"; | |
| ts_release = "/soc/pinctrl@400000/pmx_ts_release/ts_release"; | |
| tpdm_gpu_out_funnel_gpu = "/soc/tpdm@8940000/out-ports/port/endpoint"; | |
| CPU0 = "/cpus/cpu@0"; | |
| L10A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa10/regulator-l10"; | |
| ddr_dcvs_sp = "/soc/qcom,dcvs/ddr/sp"; | |
| cam_sensor_front0_reset_suspend = "/soc/pinctrl@400000/cam_sensor_front0_reset_suspend"; | |
| qcom_dcvs = "/soc/qcom,dcvs"; | |
| ipa_hw = "/soc/qcom,ipa@0x5800000"; | |
| modem_rfxe = "/soc/modem_rfxe"; | |
| S7A = "/soc/qcom,rpm-smd/rpm-regulator-smpa7/regulator-s7"; | |
| gfx3d_user = "/soc/qcom,kgsl-iommu@59a0000/gfx3d_user"; | |
| wdog = "/soc/qcom,wdt@f017000"; | |
| tpdm_qm = "/soc/tpdm@89d0000"; | |
| tpdm_west = "/soc/tpdm@8a58000"; | |
| gcc_ufs_phy_gdsc = "/soc/qcom,gdsc@1445004"; | |
| cti2 = "/soc/cti@8012000"; | |
| pm6125_l16 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa16/regulator-l16"; | |
| lpi_tdm2_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; | |
| cam_sensor_mclk1_active = "/soc/pinctrl@400000/cam_sensor_mclk1_active"; | |
| funnel_apss0_in_etm1 = "/soc/funnel@9800000/in-ports/port@1/endpoint"; | |
| tx_swr_data1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/tx_swr_data1_sleep"; | |
| funnel_turing = "/soc/funnel@8861000"; | |
| qupv3_se5_spi_active = "/soc/pinctrl@400000/qupv3_se5_spi_pins/qupv3_se5_spi_active"; | |
| hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = "/soc/qcom,gdsc@147d078"; | |
| cti_dlct_cti3 = "/soc/cti@8B5C000"; | |
| etm6 = "/soc/etm@9640000"; | |
| tcsr = "/soc/syscon@0x003C0000"; | |
| funnel_in0_in_stm = "/soc/funnel@8041000/in-ports/port@7/endpoint"; | |
| pm8008_regulators = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@9/qcom,pm8008-regulator"; | |
| S6A = "/soc/qcom,rpm-smd/rpm-regulator-smpa6/regulator-s6"; | |
| slim_msm = "/soc/slim@a5c0000"; | |
| quat_tdm_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sck/quat_tdm_sck_active"; | |
| cti_wcss_cti0 = "/soc/cti@89A4000"; | |
| funnel_in1_out_funnel_merg = "/soc/funnel@8042000/out-ports/port@0/endpoint"; | |
| quat_tdm_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_ws/quat_tdm_ws_sleep"; | |
| tpdm_actpm = "/soc/tpd@9830000"; | |
| etm7_out_funnel_apss0 = "/soc/etm@9740000/out-ports/port/endpoint"; | |
| funnel_in1_in_tpdm_wcss_silver = "/soc/funnel@8042000/in-ports/port@3/endpoint"; | |
| pm6125_s7 = "/soc/qcom,rpm-smd/rpm-regulator-smpa7/regulator-s7"; | |
| sleepstate_smp2p_in = "/soc/qcom,smp2p-adsp/qcom,sleepstate-in"; | |
| audio_etm0 = "/soc/audio_etm0"; | |
| rx_swr_data1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/rx_swr_data1_sleep"; | |
| audio_gpr = "/soc/remoteproc-adsp@ab00000/glink-edge/qcom,gpr"; | |
| spkr_1_sd_n_active = "/soc/pinctrl@400000/spkr_1_sd_n/spkr_1_sd_n_active"; | |
| pm8008_interrupt = "/soc/pinctrl@400000/pm8008_interrupt"; | |
| jtag_mm7 = "/soc/jtagmm@9740000"; | |
| CPU_PD0 = "/psci/cpu-pd0"; | |
| quat_tdm_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sd0/quat_tdm_sd0_active"; | |
| qupv3_se0_spi = "/soc/qcom,qupv3_0_geni_se@4ac0000/spi@4a80000"; | |
| lpi_tdm3_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm3_ws/lpi_tdm3_ws_active"; | |
| lpi_tdm2_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; | |
| hlos1_vote_turing_mmu_tbu0_gdsc = "/soc/qcom,gdsc@147d07c"; | |
| cam_sensor_mclk2_active = "/soc/pinctrl@400000/cam_sensor_mclk2_active"; | |
| pil_adsp_mem = "/reserved-memory/pil_adsp_region@53800000"; | |
| qupv3_se1_i2c_sleep = "/soc/pinctrl@400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sleep"; | |
| tpdm_mapss = "/soc/tpdm@8a01000"; | |
| etm5_out_funnel_apss0 = "/soc/etm@9540000/out-ports/port/endpoint"; | |
| gpu_gaming_bin = "/soc/qfprom@1b40000/gpu_gaming_bin@602d"; | |
| tpdm_west_out_tpda13 = "/soc/tpdm@8a58000/out-ports/port/endpoint"; | |
| qupv3_se2_i2c = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a88000"; | |
| bluetooth = "/soc/wcn3990"; | |
| funnel_apss0_out_funnel_apss1 = "/soc/funnel@9800000/out-ports/port@0/endpoint"; | |
| funnel_apss1_in_tpda_llm_silver = "/soc/funnel@9810000/in-ports/port@3/endpoint"; | |
| pm8008_gpios = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@8/pinctrl@c000"; | |
| mdss_core_gdsc = "/soc/qcom,gdsc@5f03000"; | |
| pm6125_l24 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa24/regulator-l24"; | |
| lmh_dcvs0 = "/soc/qcom,limits-0-dcvs@f550800"; | |
| gcc_vcodec0_gdsc = "/soc/qcom,gdsc@1458098"; | |
| lpi_tdm2_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; | |
| reserved_memory = "/reserved-memory"; | |
| pm6125_l1 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa1/regulator-l1"; | |
| quat_tdm_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sck/quat_tdm_sck_sleep"; | |
| hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = "/soc/qcom,gdsc@147d074"; | |
| logbuf = "/soc/qcom,logbuf-vendor-hooks"; | |
| CLUSTER_PD0 = "/psci/cluster-pd0"; | |
| tpdm_wcss_silver_out_funnel_in1 = "/soc/tpdm@899c000/out-ports/port/endpoint"; | |
| tpdm_pimem = "/soc/tpdm@8850000"; | |
| lpi_i2s2_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s2_sck/lpi_i2s2_sck_active"; | |
| tpda_llm_silver_out_funnel_apss1 = "/soc/tpda@98c0000/out-ports/port@0/endpoint"; | |
| etm3_out_funnel_apss0 = "/soc/etm@9340000/out-ports/port/endpoint"; | |
| cdc_dmic23_data_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/dmic23_data_active"; | |
| tpdm_turing_out_funnel_turing = "/soc/tpdm@8860000/out-ports/port/endpoint"; | |
| sde_dsi_active = "/soc/pinctrl@400000/pmx_sde/sde_dsi_active"; | |
| pm6125_l3_level = "/soc/qcom,rpm-smd/rpm-regulator-ldoa3/regulator-l3-level"; | |
| mmnrt_virt = "/soc/interconnect@0"; | |
| pil_modem_mem = "/reserved-memory/modem_region@4ab00000"; | |
| quat_tdm_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sd1/quat_tdm_sd1_active"; | |
| cti0 = "/soc/cti@8010000"; | |
| cpu5_hotplug = "/soc/qcom,cpu-hotplug/cpu5-hotplug"; | |
| pm6125_l14 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa14/regulator-l14"; | |
| funnel_in1_in_modem_rxfe = "/soc/funnel@8042000/in-ports/port@2/endpoint"; | |
| L1_D_102 = "/cpus/cpu@102/l1-dcache"; | |
| lpi_i2s2_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; | |
| cam_sensor_mclk3_active = "/soc/pinctrl@400000/cam_sensor_mclk3_active"; | |
| tpdm_pimem_out_tpda15 = "/soc/tpdm@8850000/out-ports/port/endpoint"; | |
| qupv3_se1_spi_sleep = "/soc/pinctrl@400000/qupv3_se1_spi_pins/qupv3_se1_spi_sleep"; | |
| qupv3_se0_i2c_pins = "/soc/pinctrl@400000/qupv3_se0_i2c_pins"; | |
| swr1 = "/soc/spf_core_platform/bolero-codec/rx-macro@a600000/rx_swr_master"; | |
| cti_dlct_cti1 = "/soc/cti@8B5A000"; | |
| etm1_out_funnel_apss0 = "/soc/etm@9140000/out-ports/port/endpoint"; | |
| cpu4_5_config = "/soc/thermal-zones/cpuss-0/trips/cpu-4-5-config"; | |
| qcom_pmu = "/soc/qcom,pmu"; | |
| etm4 = "/soc/etm@9440000"; | |
| VDD_GFX_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level"; | |
| lpi_i2s2_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s2_ws/lpi_i2s2_ws_active"; | |
| sdc2_on = "/soc/pinctrl@400000/sdc2_on"; | |
| cti_turing_q6 = "/soc/cti@8867000"; | |
| lpi_i2s3_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; | |
| qupv3_se3_default_cts = "/soc/pinctrl@400000/qupv3_se3_4uart_pins/qupv3_se3_default_cts"; | |
| aliases = "/aliases"; | |
| pm6125_trip1 = "/soc/thermal-zones/pm6125-tz/trips/trip1"; | |
| L1_I_3 = "/cpus/cpu@3/l1-icache"; | |
| cdc_dmic01_gpios = "/soc/spf_core_platform/cdc_dmic01_pinctrl"; | |
| quat_aux_sd2_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sd2/quat_aux_sd2_sleep"; | |
| audio_pkt_core_platform = "/soc/qcom,audio-pkt-core-platform"; | |
| lpi_aux2_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux2_ws/lpi_aux2_ws_active"; | |
| lpass_audio_hw_vote = "/soc/vote_lpass_audio_hw"; | |
| lpi_aux3_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux3_sck/lpi_aux3_sck_sleep"; | |
| firmware = "/firmware"; | |
| lpi_i2s1_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; | |
| bimc = "/soc/interconnect@4480000"; | |
| jtag_mm5 = "/soc/jtagmm@9540000"; | |
| tpdm_dcc = "/soc/tpdm@8870000"; | |
| system_noc = "/soc/interconnect@1880000"; | |
| cpu2_pause = "/soc/qcom,cpu-pause/cpu2-pause"; | |
| wcd937x_reset_sleep = "/soc/pinctrl@400000/wcd937x_reset_sleep"; | |
| tpdm_llm_silver_out_tpda_llm_silver = "/soc/tpdm@98a0000/out-ports/port/endpoint"; | |
| quat_tdm_sd2_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sd2/quat_tdm_sd2_active"; | |
| CPU7 = "/cpus/cpu@103"; | |
| msm_vidc = "/soc/qcom,vidc@5a00000"; | |
| lpi_aux1_sd0_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; | |
| funnel_in1_in_funnel_apss1 = "/soc/funnel@8042000/in-ports/port@6/endpoint"; | |
| quat_aux_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_ws/quat_aux_ws_active"; | |
| tpdm_wcss = "/soc/tpdm@899c000"; | |
| PM8008_EN = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@8/qcom,pm8008-chip@900/qcom,pm8008-chip-en"; | |
| lpi_i2s2_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; | |
| ufshc_mem = "/soc/ufshc@4804000"; | |
| spf_core_platform = "/soc/spf_core_platform"; | |
| pil_cdsp_mem = "/reserved-memory/cdsp_regions@51a00000"; | |
| funnel_apss1 = "/soc/funnel@9810000"; | |
| funnel_in0_out_funnel_merg = "/soc/funnel@8041000/out-ports/port@0/endpoint"; | |
| cti9 = "/soc/cti@8019000"; | |
| pm6125_l22 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa22/regulator-l22"; | |
| qupv3_se3_tx = "/soc/pinctrl@400000/qupv3_se3_4uart_pins/qupv3_se3_tx"; | |
| pm6125_revid = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/qcom,revid@100"; | |
| cti_lpass_q6 = "/soc/cti@8A21000"; | |
| L2_0 = "/cpus/cpu@0/l2-cache"; | |
| cam_sensor_mclk0_suspend = "/soc/pinctrl@400000/cam_sensor_mclk0_suspend"; | |
| quat_tdm_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sd1/quat_tdm_sd1_sleep"; | |
| ts_reset_active = "/soc/pinctrl@400000/pmx_ts_reset_active/ts_reset_active"; | |
| lpi_aux2_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux2_ws/lpi_aux2_ws_sleep"; | |
| adsp_loader = "/soc/qcom,msm-adsp-loader"; | |
| ramoops_mem = "/reserved-memory/ramoops_region"; | |
| msm_audio_ion = "/soc/spf_core_platform/qcom,msm-audio-ion"; | |
| modem_skin = "/soc/qmi-tmd-devices/modem/modem_skin"; | |
| cam_sensor_rear1_reset_suspend = "/soc/pinctrl@400000/cam_sensor_rear1_reset_suspend"; | |
| tx_swr_clk_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/tx_swr_clk_sleep"; | |
| qupv3_se4_2uart_active = "/soc/pinctrl@400000/qupv3_se4_2uart_pins/qupv3_se4_2uart_active"; | |
| tpdm_lpass = "/soc/tpdm@8a26000"; | |
| clk_virt = "/soc/interconnect"; | |
| qcom_seecom = "/soc/qseecom@61800000"; | |
| L1_D_2 = "/cpus/cpu@2/l1-dcache"; | |
| cdc_dmic01_clk_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/dmic01_clk_active"; | |
| pm6125_l12 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa12/regulator-l12"; | |
| L1_D_100 = "/cpus/cpu@100/l1-dcache"; | |
| quat_mi2s_sd2_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; | |
| quat_tdm_sd3_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_tdm_sd3/quat_tdm_sd3_active"; | |
| qupv3_se5_i2c_pins = "/soc/pinctrl@400000/qupv3_se5_i2c_pins"; | |
| usb0 = "/soc/ssusb@4e00000"; | |
| qupv3_se0_spi_pins = "/soc/pinctrl@400000/qupv3_se0_spi_pins"; | |
| CPU_PD7 = "/psci/cpu-pd7"; | |
| user_contig_mem = "/reserved-memory/user_contig_region"; | |
| tpda8_in_tpdm_dcc = "/soc/tpda@8004000/in-ports/port@8/endpoint"; | |
| usb_nop_phy = "/soc/usb_nop_phy"; | |
| cam_sensor_csi_mux_sel_suspend = "/soc/pinctrl@400000/cam_sensor_csi_mux_sel_suspend"; | |
| etm2 = "/soc/etm@9240000"; | |
| lpass_lpi_out_funnel_qatb = "/soc/funnel@8a24000/out-ports/port/endpoint"; | |
| lpi_i2s3_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; | |
| tx_swr_clk_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/tx_swr_clk_active"; | |
| qupv3_se2_i2c_active = "/soc/pinctrl@400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_active"; | |
| pmx_sde = "/soc/pinctrl@400000/pmx_sde"; | |
| secure_display_memory = "/reserved-memory/secure_display_region"; | |
| L1_I_1 = "/cpus/cpu@1/l1-icache"; | |
| qfprom_sys = "/soc/qfprom@0"; | |
| pm8008_8 = "/soc/qcom,qupv3_0_geni_se@4ac0000/i2c@4a84000/qcom,pm8008@8"; | |
| quat_mi2s_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_ws/quat_mi2s_ws_active"; | |
| VDD_MX_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-level"; | |
| cti_apss_cti0 = "/soc/cti@98E0000"; | |
| qupv3_se3_rx = "/soc/pinctrl@400000/qupv3_se3_4uart_pins/qupv3_se3_rx"; | |
| cpu7_hotplug = "/soc/qcom,cpu-hotplug/cpu7-hotplug"; | |
| xbl_aop_mem = "/reserved-memory/xbl_aop_region@45e00000"; | |
| cdsp_smp2p_out = "/soc/qcom,smp2p-cdsp/master-kernel"; | |
| lpi_aux3_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; | |
| jtag_mm3 = "/soc/jtagmm@9340000"; | |
| smp2p_wlan_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-wlan-1-in"; | |
| funnel_gpu_in_tpdm_gpu = "/soc/funnel@8944000/in-ports/port@0/endpoint"; | |
| S5A_LEVEL_AO = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-level-ao"; | |
| sdhc_1 = "/soc/sdhci@4744000"; | |
| pm6125_l8 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa8/regulator-l8"; | |
| sec_apps_mem = "/reserved-memory/sec_apps_region@45fff000"; | |
| gpu_gx_domain_addr = "/soc/syscon@5991508"; | |
| mdm0_cx_mon = "/soc/thermal-zones/mdm-0/trips/mdm0-cx-mon"; | |
| stub_codec = "/soc/qcom,msm-stub-codec"; | |
| CPU5 = "/cpus/cpu@101"; | |
| funnel_in1 = "/soc/funnel@8042000"; | |
| tpda10_in_tpdm_prng = "/soc/tpda@8004000/in-ports/port@10/endpoint"; | |
| lpi_tdm1_ws_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm1_ws/lpi_tdm1_ws_active"; | |
| gpucc = "/soc/clock-controller@5990000"; | |
| wsa_mclk_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/wsa_mclk_active"; | |
| lpi_tdm2_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; | |
| cpu6_pause = "/soc/qcom,cpu-pause/cpu6-pause"; | |
| spkr_1_sd_n_sleep = "/soc/pinctrl@400000/spkr_1_sd_n/spkr_1_sd_n_sleep"; | |
| rpm_msg_ram = "/soc/memory@045f0000"; | |
| quat_mi2s_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sck/quat_mi2s_sck_active"; | |
| sde_te_active = "/soc/pinctrl@400000/pmx_sde_te/sde_te_active"; | |
| cti7 = "/soc/cti@8017000"; | |
| lpi_aux2_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux2_sck/lpi_aux2_sck_active"; | |
| pm6125_l20 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa20/regulator-l20"; | |
| tpdm_mapss_out_tpda_mapss = "/soc/tpdm@8a01000/out-ports/port/endpoint"; | |
| GOLD_CLUSTER_D3 = "/idle-states/gold-cluster-d3"; | |
| anoc_1_tbu = "/soc/apps-smmu@0xc600000/anoc_1_tbu@0xc785000"; | |
| funnel_apss0_in_etm6 = "/soc/funnel@9800000/in-ports/port@6/endpoint"; | |
| tmc_etr_in_replicator_qdss = "/soc/tmc@8048000/in-ports/port@0/endpoint"; | |
| L9A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa9/regulator-l9"; | |
| tpdm_prng_out_tpda10 = "/soc/tpdm@884c000/out-ports/port/endpoint"; | |
| cpu0_hotplug = "/soc/qcom,cpu-hotplug/cpu0-hotplug"; | |
| snoc_out_funnel_in0 = "/soc/snoc/out-ports/port/endpoint"; | |
| cam_sensor_rear0_reset_active = "/soc/pinctrl@400000/cam_sensor_rear0_reset_active"; | |
| tx_swr_data1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/tx_swr_data1_active"; | |
| lpi_tdm1_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; | |
| sleep_clk = "/soc/clocks/sleep_clk"; | |
| boot_config = "/soc/qfprom@1b40000/boot_config@6070"; | |
| quat_mi2s_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sd0/quat_mi2s_sd0_active"; | |
| tx_swr_data2_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/tx_swr_data2_sleep"; | |
| lpi_aux2_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux2_sd0/lpi_aux2_sd0_active"; | |
| L1_D_0 = "/cpus/cpu@0/l1-dcache"; | |
| pm6125_l10 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa10/regulator-l10"; | |
| tpda5_in_funnel_turing = "/soc/tpda@8004000/in-ports/port@5/endpoint"; | |
| VDD_MSS_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level"; | |
| mdm1_cx_mon = "/soc/thermal-zones/mdm-1/trips/mdm1-cx-mon"; | |
| cci0_suspend = "/soc/pinctrl@400000/cci0_suspend"; | |
| qcom_cedev = "/soc/qcedev@1b20000"; | |
| qupv3_se5_spi_pins = "/soc/pinctrl@400000/qupv3_se5_spi_pins"; | |
| qupv3_se3_default_tx = "/soc/pinctrl@400000/qupv3_se3_4uart_pins/qupv3_se3_default_tx"; | |
| L8A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa8/regulator-l8"; | |
| cam_sensor_front0_reset_active = "/soc/pinctrl@400000/cam_sensor_front0_reset_active"; | |
| adsp_variant = "/soc/qfprom@1b40000/adsp_variant@6011"; | |
| cam_sensor_mclk2_suspend = "/soc/pinctrl@400000/cam_sensor_mclk2_suspend"; | |
| CPU_PD5 = "/psci/cpu-pd5"; | |
| L2A_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-ldoa2/regulator-l2-level"; | |
| pm6125_adc_tm = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/adc_tm@3500"; | |
| qupv3_se1_spi = "/soc/qcom,qupv3_0_geni_se@4ac0000/spi@4a84000"; | |
| etm0 = "/soc/etm@9040000"; | |
| usb_qmp_phy = "/soc/ssphy@1615000"; | |
| funnel_merg_in_funnel_in0 = "/soc/funnel@8045000/in-ports/port@0/endpoint"; | |
| dump_mem = "/reserved-memory/mem_dump_region"; | |
| replicator_qdss = "/soc/replicator@8046000"; | |
| lpi_i2s1_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; | |
| cti14 = "/soc/cti@801e000"; | |
| L7A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa7/regulator-l7"; | |
| funnel_qatb_out_funnel_in0 = "/soc/funnel@8005000/out-ports/port@0/endpoint"; | |
| cci0_active = "/soc/pinctrl@400000/cci0_active"; | |
| qupv3_se1_i2c_pins = "/soc/pinctrl@400000/qupv3_se1_i2c_pins"; | |
| tx_swr_data2_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/tx_swr_data2_active"; | |
| jtag_mm1 = "/soc/jtagmm@9140000"; | |
| video_mem = "/reserved-memory/video_region@55617000"; | |
| tpdm_qm_out_tpda12 = "/soc/tpdm@89d0000/out-ports/port/endpoint"; | |
| lpi_aux1_sck_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux1_sck/lpi_aux1_sck_sleep"; | |
| tpdm_apss_out_tpda_apss = "/soc/tpdm@9860000/out-ports/port/endpoint"; | |
| pm6125_l6 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa6/regulator-l6"; | |
| quat_mi2s_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sd1/quat_mi2s_sd1_active"; | |
| funnel_qatb_in_funnel_turing = "/soc/funnel@8005000/in-ports/port@6/endpoint"; | |
| sdc1_off = "/soc/pinctrl@400000/sdc1_off"; | |
| stm_debug_fuse = "/soc/qfprom@1b40000/stm@20f0"; | |
| lpi_aux2_sd1_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux2_sd1/lpi_aux2_sd1_active"; | |
| qupv3_se5_spi = "/soc/qcom,qupv3_0_geni_se@4ac0000/spi@4a94000"; | |
| CPU3 = "/cpus/cpu@3"; | |
| slimbus = "/soc/slim@a5c0000/ngd@1/btfmslim-driver"; | |
| slimbam = "/soc/bamdma@0xa580000"; | |
| lpi_tdm2_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; | |
| non_secure_display_memory = "/reserved-memory/non_secure_display_region"; | |
| qusb_phy0 = "/soc/qusb@1613000"; | |
| qupv3_se3_default_rx = "/soc/pinctrl@400000/qupv3_se3_4uart_pins/qupv3_se3_default_rx"; | |
| L6A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa6/regulator-l6"; | |
| tlmm = "/soc/pinctrl@400000"; | |
| cdc_dmic23_data_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/dmic23_data_sleep"; | |
| L3A_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-ldoa3/regulator-l3-level"; | |
| qupv3_se3_default_rts = "/soc/pinctrl@400000/qupv3_se3_4uart_pins/qupv3_se3_default_rts"; | |
| cti5 = "/soc/cti@8015000"; | |
| apps_smmu = "/soc/apps-smmu@0xc600000"; | |
| pm6125_l19 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa19/regulator-l19"; | |
| funnel_apss0_in_etm4 = "/soc/funnel@9800000/in-ports/port@4/endpoint"; | |
| gpu_cx_mon = "/soc/thermal-zones/gpu/trips/gpu-cx-mon"; | |
| cdc_dmic01_clk_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/dmic01_clk_sleep"; | |
| tmc_etf_in_funnel_merg = "/soc/tmc@8047000/in-ports/port@0/endpoint"; | |
| cdsp_hw = "/soc/qmi-tmd-devices/cdsp/hvx"; | |
| funnel_apss1_out_funnel_in1 = "/soc/funnel@9810000/out-ports/port@0/endpoint"; | |
| gfx3d_secure = "/soc/qcom,kgsl-iommu@59a0000/gfx3d_secure"; | |
| sdhc2_opp_table = "/soc/sdhc2-opp-table"; | |
| funnel_qatb_in_lpass_lpi = "/soc/funnel@8005000/in-ports/port@5/endpoint"; | |
| csr = "/soc/csr@8001000"; | |
| gpu_cx_gdsc = "/soc/qcom,gdsc@599106c"; | |
| audio_prm = "/soc/remoteproc-adsp@ab00000/glink-edge/qcom,gpr/q6prm"; | |
| cci1_active = "/soc/pinctrl@400000/cci1_active"; | |
| L5A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa5/regulator-l5"; | |
| qupv3_se1_spi_active = "/soc/pinctrl@400000/qupv3_se1_spi_pins/qupv3_se1_spi_active"; | |
| glink_edge = "/soc/remoteproc-adsp@ab00000/glink-edge"; | |
| lpi_tdm3_sck_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm3_sck/lpi_tdm3_sck_active"; | |
| quat_mi2s_sd2_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sd2/quat_mi2s_sd2_active"; | |
| S5A_FLOOR_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5-floor-level"; | |
| turing_etm0 = "/soc/turing_etm0"; | |
| cpucc_debug = "/soc/syscon@f11101c"; | |
| L1_I_102 = "/cpus/cpu@102/l1-icache"; | |
| lpi_aux3_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux3_ws/lpi_aux3_ws_sleep"; | |
| CPU_PD3 = "/psci/cpu-pd3"; | |
| replicator_qdss_in_tmc_etf = "/soc/replicator@8046000/in-ports/port@0/endpoint"; | |
| qcom_tzlog = "/soc/tz-log@c125720"; | |
| cpu2_hotplug = "/soc/qcom,cpu-hotplug/cpu2-hotplug"; | |
| msm_gpu = "/soc/qcom,kgsl-3d0@5900000"; | |
| gpu_gx_sw_reset = "/soc/syscon@5991008"; | |
| qupv3_se0_i2c_active = "/soc/pinctrl@400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_active"; | |
| modem_rxfe_out_funnel_in1 = "/soc/modem_rfxe/out-ports/port/endpoint"; | |
| quat_aux_sd3_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_aux_sd3/quat_aux_sd3_sleep"; | |
| L4A = "/soc/qcom,rpm-smd/rpm-regulator-ldoa4/regulator-l4"; | |
| lpi_tdm3_sd0_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; | |
| lpi_i2s1_ws_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; | |
| lpi_i2s1_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; | |
| cpu4_config = "/soc/thermal-zones/cpu-1-0/trips/cpu4-config"; | |
| tpda_actpm_in_tpdm_actpm = "/soc/tpda@9832000/in-ports/port@0/endpoint"; | |
| qupv3_se0_2uart = "/soc/qcom,qupv3_0_geni_se@4ac0000/qcom,qup_uart@4a80000"; | |
| pm6125_rtc = "/soc/qcom,spmi@1c40000/qcom,pm6125@0/qcom,pm6125_rtc"; | |
| apss_tgu = "/soc/tgu@9900000"; | |
| gcc_camss_top_gdsc = "/soc/qcom,gdsc@1458004"; | |
| cti12 = "/soc/cti@801c000"; | |
| cpu3_pause = "/soc/qcom,cpu-pause/cpu3-pause"; | |
| qupv3_se1_spi_pins = "/soc/pinctrl@400000/qupv3_se1_spi_pins"; | |
| icnss = "/soc/qcom,icnss@C800000"; | |
| ipa_smmu_wlan = "/soc/ipa_smmu_wlan"; | |
| modem_current = "/soc/qmi-tmd-devices/modem/modem_current"; | |
| tpdm_llm_silver = "/soc/tpdm@98a0000"; | |
| lpi_aux1_sd1_sleep = "/soc/spf_core_platform/lpi_pinctrl@ac40000/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; | |
| pm6125_l4 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa4/regulator-l4"; | |
| CLUSTER_PD3 = "/psci/cluster-pd3"; | |
| debugcc = "/soc/debug-clock-controller@0"; | |
| S3A_LEVEL_AO = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-level-ao"; | |
| VDD_CX_FLOOR_LEVEL = "/soc/qcom,rpm-smd/rpm-regulator-smpa3/regulator-s3-floor-level"; | |
| tpdm_vsense = "/soc/tpdm@8840000"; | |
| CPU1 = "/cpus/cpu@1"; | |
| quat_mi2s_sd3_active = "/soc/spf_core_platform/lpi_pinctrl@ac40000/quat_mi2s_sd3/quat_mi2s_sd3_active"; | |
| qupv3_se5_i2c_active = "/soc/pinctrl@400000/qupv3_se5_i2c_pins/qupv3_se5_i2c_active"; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| phandle = <0x130>; | |
| linux,cma { | |
| linux,cma-default; | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x2000000>; | |
| phandle = <0xef>; | |
| reusable; | |
| }; | |
| dfps_data_region@5cf00000 { | |
| label = "dfps_data_region"; | |
| reg = <0x00 0x5cf00000 0x00 0x100000>; | |
| phandle = <0x30d>; | |
| }; | |
| ipa_gsi_region@55610000 { | |
| reg = <0x00 0x55610000 0x00 0x5000>; | |
| phandle = <0x136>; | |
| no-map; | |
| }; | |
| modem_region@4ab00000 { | |
| reg = <0x00 0x4ab00000 0x00 0x6900000>; | |
| phandle = <0x70>; | |
| no-map; | |
| }; | |
| smem_region@46000000 { | |
| reg = <0x00 0x46000000 0x00 0x200000>; | |
| phandle = <0x62>; | |
| no-map; | |
| }; | |
| wlan_msa_region@51900000 { | |
| reg = <0x00 0x51900000 0x00 0x100000>; | |
| phandle = <0x135>; | |
| no-map; | |
| }; | |
| hyp_region@45700000 { | |
| reg = <0x00 0x45700000 0x00 0x600000>; | |
| phandle = <0x131>; | |
| no-map; | |
| }; | |
| pil_adsp_region@53800000 { | |
| reg = <0x00 0x53800000 0x00 0x1e00000>; | |
| phandle = <0x2e>; | |
| no-map; | |
| }; | |
| ipa_fw_region@55600000 { | |
| reg = <0x00 0x55600000 0x00 0x10000>; | |
| phandle = <0x76>; | |
| no-map; | |
| }; | |
| va_md_mem_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x1000000>; | |
| phandle = <0x60>; | |
| reusable; | |
| }; | |
| secure_display_region { | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x5c00000>; | |
| phandle = <0x84>; | |
| reusable; | |
| }; | |
| adsp_region { | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x800000>; | |
| phandle = <0x68>; | |
| reusable; | |
| }; | |
| non_secure_display_region { | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0xa400000>; | |
| phandle = <0x86>; | |
| reusable; | |
| }; | |
| sec_apps_region@45fff000 { | |
| reg = <0x00 0x45fff000 0x00 0x1000>; | |
| phandle = <0x133>; | |
| no-map; | |
| }; | |
| cdsp_regions@51a00000 { | |
| reg = <0x00 0x51a00000 0x00 0x1e00000>; | |
| phandle = <0x33>; | |
| no-map; | |
| }; | |
| audio_cma_region { | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x1c00000>; | |
| phandle = <0x87>; | |
| reusable; | |
| }; | |
| gpu_region@55615000 { | |
| reg = <0x00 0x55615000 0x00 0x2000>; | |
| phandle = <0x137>; | |
| no-map; | |
| }; | |
| ramoops_region { | |
| pmsg-size = <0x200000>; | |
| mem-type = <0x02>; | |
| alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>; | |
| compatible = "ramoops"; | |
| size = <0x00 0x200000>; | |
| phandle = <0x139>; | |
| }; | |
| video_region@55617000 { | |
| reg = <0x00 0x55617000 0x00 0x700000>; | |
| phandle = <0x138>; | |
| no-map; | |
| }; | |
| qseecom_ta_region { | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x1000000>; | |
| phandle = <0x25>; | |
| reusable; | |
| }; | |
| user_contig_region { | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x1000000>; | |
| phandle = <0x85>; | |
| reusable; | |
| }; | |
| xbl_aop_region@45e00000 { | |
| reg = <0x00 0x45e00000 0x00 0x140000>; | |
| phandle = <0x132>; | |
| no-map; | |
| }; | |
| splash_region@5c000000 { | |
| label = "cont_splash_region"; | |
| reg = <0x00 0x5c000000 0x00 0xf00000>; | |
| phandle = <0x324>; | |
| }; | |
| mem_dump_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x800000>; | |
| phandle = <0x36>; | |
| reusable; | |
| }; | |
| qseecom_region { | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x1400000>; | |
| phandle = <0x24>; | |
| reusable; | |
| }; | |
| cdsp_sec_regions@46200000 { | |
| reg = <0x00 0x46200000 0x00 0x1e00000>; | |
| phandle = <0x83>; | |
| no-map; | |
| }; | |
| removed_region@60000000 { | |
| reg = <0x00 0x60000000 0x00 0x3900000>; | |
| phandle = <0x134>; | |
| no-map; | |
| }; | |
| }; | |
| memory { | |
| ddr_device_type = <0x07>; | |
| device_type = "memory"; | |
| reg = <0x00 0x40000000 0x00 0x3da00000 0x00 0xc0000000 0x00 0x80000000 0x00 0x80000000 0x00 0x40000000>; | |
| }; | |
| }; |
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