Created
November 4, 2025 10:45
-
-
Save TheGammaSqueeze/69ddf2254b7a9be2a0b7d23bd7c450be to your computer and use it in GitHub Desktop.
Ayn Thor - Running Kernel Device Tree - Android 13
This file has been truncated, but you can view the full file.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| /dts-v1/; | |
| / { | |
| #address-cells = <0x02>; | |
| model = "Qualcomm Technologies, Inc. KalamaP HDK"; | |
| qcom,board-id = <0x1001f 0x00>; | |
| #size-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| compatible = "qcom,kalamap-hdk", "qcom,kalamap", "qcom,hdk"; | |
| qcom,msm-id = <0x25b 0x20000>; | |
| sram@17D09400 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| compatible = "mmio-sram"; | |
| ranges = <0x00 0x00 0x00 0x17d09400 0x00 0x400>; | |
| reg = <0x00 0x17d09400 0x00 0x400>; | |
| phandle = <0x2fa>; | |
| scmi-shmem@0 { | |
| compatible = "arm,scmi-shmem"; | |
| reg = <0x00 0x00 0x00 0x400>; | |
| phandle = <0x3e>; | |
| }; | |
| }; | |
| mem-offline { | |
| offline-sizes = <0x02 0xc0000000 0x01 0x00>; | |
| granule = <0x400>; | |
| compatible = "qcom,mem-offline"; | |
| mboxes = <0x02 0x00>; | |
| }; | |
| soc { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| interrupt-parent = <0x01>; | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| phandle = <0x2fc>; | |
| modem2_etm0 { | |
| atid = <0x27>; | |
| qcom,inst-id = <0x0b>; | |
| coresight-name = "coresight-modem2-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x11e>; | |
| phandle = <0x18f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interconnect@320c0000 { | |
| #interconnect-cells = <0x01>; | |
| qcom,bcm-voters = <0x40>; | |
| compatible = "qcom,kalama-nsp_noc"; | |
| reg = <0x320c0000 0xe080>; | |
| phandle = <0x7a>; | |
| qcom,bcm-voter-names = "hlos"; | |
| }; | |
| qcom,ipe0@ac42000 { | |
| ipe0-vdd-supply = <0x4fe>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; | |
| reg-names = "ipe0_top"; | |
| reg-cam-base = <0x42000>; | |
| cell-index = <0x00>; | |
| clocks = <0x3b 0x56 0x3b 0x59 0x3b 0x5b 0x3b 0x58 0x3b 0x57 0x3b 0x5a 0x3b 0x17>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| cam_hw_pid = <0x0e 0x1f 0x0f>; | |
| compatible = "qcom,cam-ipe680"; | |
| src-clock-name = "ipe_nps_clk_src"; | |
| status = "ok"; | |
| reg = <0xac42000 0x18000>; | |
| regulator-names = "ipe0-vdd"; | |
| phandle = <0x5c8>; | |
| nrt-device; | |
| clock-rates = <0x00 0x00 0x00 0x1b1ebfc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; | |
| }; | |
| syscon@3d99504 { | |
| compatible = "syscon"; | |
| reg = <0x3d99504 0x04>; | |
| phandle = <0x2de>; | |
| }; | |
| funnel_ete { | |
| coresight-name = "coresight-funnel-ete"; | |
| compatible = "arm,coresight-static-funnel"; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1e9>; | |
| phandle = <0x1e0>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x1f0>; | |
| phandle = <0x1e7>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x1ee>; | |
| phandle = <0x1e5>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x1ec>; | |
| phandle = <0x1e3>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x1ea>; | |
| phandle = <0x1e1>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x1ef>; | |
| phandle = <0x1e6>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x1ed>; | |
| phandle = <0x1e4>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x1eb>; | |
| phandle = <0x1e2>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1e8>; | |
| phandle = <0x199>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| pmic-pon-log { | |
| nvmem-names = "pon_log0", "pon_log1"; | |
| compatible = "qcom,pmic-pon-log"; | |
| nvmem = <0x5fe 0x5ff>; | |
| }; | |
| cti@10961000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-gpu_isdb_cti"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10961000 0x1000>; | |
| phandle = <0x465>; | |
| }; | |
| tpdm@138c0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x42>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-apss-llm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x138c0000 0x1000>; | |
| phandle = <0x420>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x118>; | |
| phandle = <0x196>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@17100000 { | |
| #address-cells = <0x01>; | |
| #redistributor-regions = <0x01>; | |
| interrupts = <0x01 0x09 0x04>; | |
| #size-cells = <0x01>; | |
| redistributor-stride = <0x00 0x40000>; | |
| compatible = "arm,gic-v3"; | |
| ranges; | |
| #interrupt-cells = <0x03>; | |
| reg = <0x17100000 0x10000 0x17180000 0x200000>; | |
| phandle = <0x01>; | |
| interrupt-controller; | |
| msi-controller@17140000 { | |
| msi-controller; | |
| compatible = "arm,gic-v3-its"; | |
| reg = <0x17140000 0x20000>; | |
| phandle = <0x2fe>; | |
| #msi-cells = <0x01>; | |
| }; | |
| }; | |
| tpdm@10880000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x46>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-spss"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10880000 0x1000>; | |
| phandle = <0x41a>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x111>; | |
| phandle = <0x113>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| hwlock { | |
| syscon = <0x68 0x00 0x1000>; | |
| compatible = "qcom,tcsr-mutex"; | |
| phandle = <0x6a>; | |
| #hwlock-cells = <0x01>; | |
| }; | |
| display_gpio_regulator@2 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| pinctrl-names = "default"; | |
| regulator-boot-on; | |
| gpio = <0x33 0x66 0x00>; | |
| pinctrl-0 = <0x76c>; | |
| regulator-enable-ramp-delay = <0xe9>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "TS_VDDIO_1V8"; | |
| compatible = "qti-regulator-fixed"; | |
| qcom,proxy-consumer-enable; | |
| phandle = <0x76b>; | |
| proxy-supply = <0x76b>; | |
| }; | |
| tpdm@1000f000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x41>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-spdm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x1000f000 0x1000>; | |
| phandle = <0x415>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10c>; | |
| phandle = <0x1b6>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@12010000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-cpu0"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x12010000 0x1000>; | |
| phandle = <0x485>; | |
| trig-conns { | |
| arm,trig-out-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| cpu = <0x18>; | |
| arm,trig-in-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| }; | |
| }; | |
| tpdm@109c0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4b>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-dl-south"; | |
| compatible = "arm,primecell"; | |
| reg = <0x109c0000 0x1000>; | |
| phandle = <0x41c>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x114>; | |
| phandle = <0x176>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10c08000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-mm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10c08000 0x1000>; | |
| phandle = <0x16f>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xfd>; | |
| phandle = <0x141>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dcc_v2@100ff000 { | |
| dcc-ram-offset = <0x00>; | |
| reg-names = "dcc-base", "dcc-ram-base"; | |
| ll-reg-offsets = <0x34 0x3c 0x40 0x44 0x4c 0x50 0x68 0x6c 0x38 0xb4 0xbc 0xc0 0xc4 0xcc 0xd0 0xe8 0xec 0xb8 0x134 0x13c 0x140 0x144 0x14c 0x150 0x168 0x16c 0x138 0x1b4 0x1bc 0x1c0 0x1c4 0x1cc 0x1d0 0x1e8 0x1ec 0x1b8 0x234 0x23c 0x240 0x244 0x24c 0x250 0x268 0x26c 0x238 0x2b4 0x2bc 0x2c0 0x2c4 0x2cc 0x2d0 0x2e8 0x2ec 0x2b8 0x334 0x33c 0x340 0x344 0x34c 0x350 0x368 0x36c 0x338 0x3b4 0x3bc 0x3c0 0x3c4 0x3cc 0x3d0 0x3e8 0x3ec 0x3b8>; | |
| compatible = "qcom,dcc-v2"; | |
| per-ll-reg-cnt = <0x09>; | |
| reg = <0x100ff000 0x1000 0x10080000 0x18000>; | |
| phandle = <0x491>; | |
| qcom,transaction_timeout = <0x00>; | |
| link_list_0 { | |
| qcom,data-sink = "sram"; | |
| qcom,link-list = <0x00 0x185000 0x01 0x00 0x01 0x185000 0x01 0x00 0x00 0x185000 0x01 0x00 0x00 0x1084c000 0x01 0x01 0x00 0x10c06000 0x01 0x01 0x01 0x1084c000 0x00 0x01 0x01 0x10c06000 0x00 0x01 0x00 0x1084c000 0x01 0x01 0x00 0x10c06000 0x01 0x01 0x00 0x1fc4080 0x03 0x00 0x00 0x1fc4090 0x01 0x00 0x00 0x6802028 0x01 0x00 0x00 0x68b0404 0x02 0x00 0x00 0x68b0208 0x03 0x00 0x00 0x68b0228 0x03 0x00 0x00 0x68b0248 0x03 0x00 0x00 0x68b0268 0x03 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x32302028 0x01 0x00 0x00 0x323b0404 0x02 0x00 0x00 0x323b0208 0x03 0x00 0x00 0x323b0228 0x03 0x00 0x00 0x323b0248 0x03 0x00 0x00 0x323b0268 0x03 0x00 0x00 0x320a4404 0x02 0x00 0x00 0x320a4208 0x03 0x00 0x00 0x320a4228 0x03 0x00 0x00 0x320a4248 0x03 0x00 0x00 0x320a4268 0x03 0x00 0x00 0x4082028 0x01 0x00 0x00 0x4130404 0x02 0x00 0x00 0x4130208 0x03 0x00 0x00 0x4130228 0x03 0x00 0x00 0x4130248 0x03 0x00 0x00 0x4130268 0x03 0x00 0x00 0x4200404 0x02 0x00 0x00 0x4200208 0x03 0x00 0x00 0x4200228 0x03 0x00 0x00 0x4200248 0x03 0x00 0x00 0x4200268 0x03 0x00 0x00 0x1780005c 0x01 0x00 0x00 0x1781005c 0x01 0x00 0x00 0x1782005c 0x01 0x00 0x00 0x1783005c 0x01 0x00 0x00 0x1784005c 0x01 0x00 0x00 0x1785005c 0x01 0x00 0x00 0x1786005c 0x01 0x00 0x00 0x1787005c 0x01 0x00 0x00 0x1740003c 0x01 0x00 0x00 0x17600238 0x01 0x00 0x00 0x17600240 0x0b 0x00 0x00 0x17600530 0x01 0x00 0x00 0x1760051c 0x01 0x00 0x00 0x17600524 0x01 0x00 0x00 0x1760052c 0x01 0x00 0x00 0x17600518 0x01 0x00 0x00 0x17600520 0x01 0x00 0x00 0x17600528 0x01 0x00 0x00 0x17600404 0x03 0x00 0x00 0x1760041c 0x03 0x00 0x00 0x17600434 0x01 0x00 0x00 0x1760043c 0x01 0x00 0x00 0x17600440 0x01 0x00 0x00 0x17400438 0x01 0x00 0x00 0x17600044 0x01 0x00 0x00 0x17600500 0x01 0x00 0x00 0x17600504 0x05 0x00 0x00 0x17900908 0x01 0x00 0x00 0x17900c18 0x01 0x00 0x00 0x17901908 0x01 0x00 0x00 0x17901c18 0x01 0x00 0x00 0x17b90810 0x01 0x00 0x00 0x17b90c50 0x01 0x00 0x00 0x17b90814 0x01 0x00 0x00 0x17b90c54 0x01 0x00 0x00 0x17b90818 0x01 0x00 0x00 0x17b90c58 0x01 0x00 0x00 0x17b93a04 0x02 0x00 0x00 0x17ba0810 0x01 0x00 0x00 0x17ba0c50 0x01 0x00 0x00 0x17ba0814 0x01 0x00 0x00 0x17ba0c54 0x01 0x00 0x00 0x17ba0818 0x01 0x00 0x00 0x17ba0c58 0x01 0x00 0x00 0x17ba3a04 0x02 0x00 0x00 0x17b93000 0x50 0x00 0x00 0x17ba3000 0x50 0x00 0x00 0xc201244 0x01 0x00 0x00 0xc202244 0x01 0x00 0x00 0x17b00000 0x01 0x00 0x00 0x17a94030 0x01 0x00 0x00 0x17a9408c 0x01 0x00 0x01 0x17a9409c 0x78 0x00 0x01 0x17a9409c 0x00 0x00 0x01 0x17a94048 0x01 0x00 0x01 0x17a94090 0x00 0x00 0x01 0x17a94090 0x25 0x00 0x00 0x17a94098 0x01 0x00 0x01 0x17a94048 0x1d 0x00 0x01 0x17a94090 0x00 0x00 0x01 0x17a94090 0x25 0x00 0x00 0x17a94098 0x01 0x00 0x00 0x17a90030 0x01 0x00 0x00 0x17a9008c 0x01 0x00 0x01 0x17a9009c 0x78 0x00 0x01 0x17a9009c 0x00 0x00 0x01 0x17a90048 0x01 0x00 0x01 0x17a90090 0x00 0x00 0x01 0x17a90090 0x25 0x00 0x00 0x17a90098 0x01 0x00 0x01 0x17a90048 0x1d 0x00 0x01 0x17a90090 0x00 0x00 0x01 0x17a90090 0x25 0x00 0x00 0x17a90098 0x01 0x00 0x00 0x17a92030 0x01 0x00 0x00 0x17a9208c 0x01 0x00 0x01 0x17a9209c 0x78 0x00 0x01 0x17a9209c 0x00 0x00 0x01 0x17a92048 0x01 0x00 0x01 0x17a92090 0x00 0x00 0x01 0x17a92090 0x25 0x00 0x00 0x17a92098 0x01 0x00 0x01 0x17a92048 0x1d 0x00 0x01 0x17a92090 0x00 0x00 0x01 0x17a92090 0x25 0x00 0x00 0x17a92098 0x01 0x00 0x00 0x17a96030 0x01 0x00 0x00 0x17a9608c 0x01 0x00 0x01 0x17a9609c 0x78 0x00 0x01 0x17a9609c 0x00 0x00 0x01 0x17a96048 0x01 0x00 0x01 0x17a96090 0x00 0x00 0x01 0x17a96090 0x25 0x00 0x00 0x17a96098 0x01 0x00 0x01 0x17a96048 0x1d 0x00 0x01 0x17a96090 0x00 0x00 0x01 0x17a96090 0x25 0x00 0x00 0x17a96098 0x01 0x00 0x00 0x17d98024 0x01 0x00 0x00 0x13822000 0x01 0x01 0x00 0x221c20a4 0x01 0x00 0x00 0x1fc8000 0x01 0x00 0x00 0x17400038 0x01 0x00 0x00 0x17d91020 0x01 0x00 0x00 0x17d92020 0x01 0x00 0x00 0x17d93020 0x01 0x00 0x00 0x17d90020 0x01 0x00 0x00 0x17d9134c 0x01 0x00 0x00 0x17d9234c 0x01 0x00 0x00 0x17d9334c 0x01 0x00 0x00 0x17d9034c 0x01 0x00 0x00 0x17d91300 0x01 0x00 0x00 0x17d92300 0x01 0x00 0x00 0x17d93300 0x01 0x00 0x00 0x17d90300 0x01 0x00 0x00 0x24183040 0x01 0x00 0x00 0x24183048 0x01 0x00 0x00 0x24102010 0x01 0x00 0x00 0x24102020 0x06 0x00 0x00 0x24102410 0x01 0x00 0x00 0x24102420 0x06 0x00 0x00 0x24142010 0x01 0x00 0x00 0x24142020 0x06 0x00 0x00 0x24142410 0x01 0x00 0x00 0x24142420 0x06 0x00 0x00 0x24182010 0x01 0x00 0x00 0x24182020 0x06 0x00 0x00 0x24182410 0x01 0x00 0x00 0x24182420 0x06 0x00 0x00 0x24100810 0x01 0x00 0x00 0x24100838 0x01 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100838 0x01 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100838 0x01 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100838 0x01 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100830 0x02 0x00 0x00 0x24100808 0x02 0x00 0x00 0x24100c10 0x01 0x00 0x00 0x24100c38 0x01 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c38 0x01 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c38 0x01 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c38 0x01 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c30 0x02 0x00 0x00 0x24100c08 0x02 0x00 0x00 0x24140810 0x01 0x00 0x00 0x24140838 0x01 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140838 0x01 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140838 0x01 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140838 0x01 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140830 0x02 0x00 0x00 0x24140808 0x02 0x00 0x00 0x24140c10 0x01 0x00 0x00 0x24140c38 0x01 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c38 0x01 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c38 0x01 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c38 0x01 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c30 0x02 0x00 0x00 0x24140c08 0x02 0x00 0x00 0x24180010 0x01 0x00 0x00 0x24180038 0x01 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180038 0x01 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180038 0x01 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180038 0x01 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180030 0x02 0x00 0x00 0x24180008 0x02 0x00 0x00 0x24180410 0x01 0x00 0x00 0x24180438 0x01 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180438 0x01 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180438 0x01 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180438 0x01 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180430 0x02 0x00 0x00 0x24180408 0x02 0x00 0x00 0x24101018 0x01 0x00 0x00 0x24101008 0x01 0x00 0x00 0x24101010 0x02 0x00 0x00 0x24101010 0x02 0x00 0x00 0x24101010 0x02 0x00 0x00 0x24101010 0x02 0x00 0x00 0x24101098 0x01 0x00 0x00 0x24101088 0x01 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24101090 0x02 0x00 0x00 0x24141018 0x01 0x00 0x00 0x24141008 0x01 0x00 0x00 0x24141010 0x02 0x00 0x00 0x24141010 0x02 0x00 0x00 0x24141010 0x02 0x00 0x00 0x24141010 0x02 0x00 0x00 0x24141098 0x01 0x00 0x00 0x24141088 0x01 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24141090 0x02 0x00 0x00 0x24181018 0x01 0x00 0x00 0x24181008 0x01 0x00 0x00 0x24181010 0x02 0x00 0x00 0x24181010 0x02 0x00 0x00 0x24181010 0x02 0x00 0x00 0x24181098 0x01 0x00 0x00 0x24181088 0x01 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x24181090 0x02 0x00 0x00 0x17800010 0x01 0x00 0x00 0x17800024 0x01 0x00 0x00 0x17800038 0x01 0x00 0x00 0x1780003c 0x01 0x00 0x00 0x17800040 0x01 0x00 0x00 0x17800044 0x01 0x00 0x00 0x17800048 0x01 0x00 0x00 0x1780004c 0x01 0x00 0x00 0x17800058 0x01 0x00 0x00 0x1780005c 0x01 0x00 0x00 0x17800060 0x01 0x00 0x00 0x17800064 0x01 0x00 0x00 0x1780006c 0x01 0x00 0x00 0x178000f0 0x01 0x00 0x00 0x178000f4 0x01 0x00 0x00 0x17810010 0x01 0x00 0x00 0x17810024 0x01 0x00 0x00 0x17810038 0x01 0x00 0x00 0x1781003c 0x01 0x00 0x00 0x17810040 0x01 0x00 0x00 0x17810044 0x01 0x00 0x00 0x17810048 0x01 0x00 0x00 0x1781004c 0x01 0x00 0x00 0x17810058 0x01 0x00 0x00 0x1781005c 0x01 0x00 0x00 0x17810060 0x01 0x00 0x00 0x17810064 0x01 0x00 0x00 0x1781006c 0x01 0x00 0x00 0x178100f0 0x01 0x00 0x00 0x178100f4 0x01 0x00 0x00 0x17820010 0x01 0x00 0x00 0x17820024 0x01 0x00 0x00 0x17820038 0x01 0x00 0x00 0x1782003c 0x01 0x00 0x00 0x17820040 0x01 0x00 0x00 0x17820044 0x01 0x00 0x00 0x17820048 0x01 0x00 0x00 0x1782004c 0x01 0x00 0x00 0x17820058 0x01 0x00 0x00 0x1782005c 0x01 0x00 0x00 0x17820060 0x01 0x00 0x00 0x17820064 0x01 0x00 0x00 0x178200f0 0x01 0x00 0x00 0x178200f4 0x01 0x00 0x00 0x17830010 0x01 0x00 0x00 0x17830024 0x01 0x00 0x00 0x17830038 0x01 0x00 0x00 0x1783003c 0x01 0x00 0x00 0x17830040 0x01 0x00 0x00 0x17830044 0x01 0x00 0x00 0x17830048 0x01 0x00 0x00 0x1783004c 0x01 0x00 0x00 0x17830058 0x01 0x00 0x00 0x1783005c 0x01 0x00 0x00 0x17830060 0x01 0x00 0x00 0x17830064 0x01 0x00 0x00 0x178300f0 0x01 0x00 0x00 0x178300f4 0x01 0x00 0x00 0x17840010 0x01 0x00 0x00 0x17840024 0x01 0x00 0x00 0x17840038 0x01 0x00 0x00 0x1784003c 0x01 0x00 0x00 0x17840040 0x01 0x00 0x00 0x17840044 0x01 0x00 0x00 0x17840048 0x01 0x00 0x00 0x1784004c 0x01 0x00 0x00 0x17840058 0x01 0x00 0x00 0x1784005c 0x01 0x00 0x00 0x17840060 0x01 0x00 0x00 0x17840064 0x01 0x00 0x00 0x178400f0 0x01 0x00 0x00 0x178400f4 0x01 0x00 0x00 0x17850010 0x01 0x00 0x00 0x17850024 0x01 0x00 0x00 0x17850038 0x01 0x00 0x00 0x1785003c 0x01 0x00 0x00 0x17850040 0x01 0x00 0x00 0x17850044 0x01 0x00 0x00 0x17850048 0x01 0x00 0x00 0x1785004c 0x01 0x00 0x00 0x17850058 0x01 0x00 0x00 0x1785005c 0x01 0x00 0x00 0x17850060 0x01 0x00 0x00 0x17850064 0x01 0x00 0x00 0x178500f0 0x01 0x00 0x00 0x178500f4 0x01 0x00 0x00 0x17860010 0x01 0x00 0x00 0x17860024 0x01 0x00 0x00 0x17860038 0x01 0x00 0x00 0x1786003c 0x01 0x00 0x00 0x17860040 0x01 0x00 0x00 0x17860044 0x01 0x00 0x00 0x17860048 0x01 0x00 0x00 0x1786004c 0x01 0x00 0x00 0x17860058 0x01 0x00 0x00 0x1786005c 0x01 0x00 0x00 0x17860060 0x01 0x00 0x00 0x17860064 0x01 0x00 0x00 0x178600f0 0x01 0x00 0x00 0x178600f4 0x01 0x00 0x00 0x17870010 0x01 0x00 0x00 0x17870024 0x01 0x00 0x00 0x17870038 0x01 0x00 0x00 0x1787003c 0x01 0x00 0x00 0x17870040 0x01 0x00 0x00 0x17870044 0x01 0x00 0x00 0x17870048 0x01 0x00 0x00 0x1787004c 0x01 0x00 0x00 0x17870058 0x01 0x00 0x00 0x1787005c 0x01 0x00 0x00 0x17870060 0x01 0x00 0x00 0x17870064 0x01 0x00 0x00 0x178700f0 0x01 0x00 0x00 0x178700f4 0x01 0x00 0x00 0x178a0010 0x01 0x00 0x00 0x178a0024 0x01 0x00 0x00 0x178a0038 0x01 0x00 0x00 0x178a003c 0x01 0x00 0x00 0x178a0040 0x01 0x00 0x00 0x178a0044 0x01 0x00 0x00 0x178a0048 0x01 0x00 0x00 0x178a004c 0x01 0x00 0x00 0x178a006c 0x01 0x00 0x00 0x178a0070 0x01 0x00 0x00 0x178a0074 0x01 0x00 0x00 0x178a0078 0x01 0x00 0x00 0x178a007c 0x01 0x00 0x00 0x178a0084 0x01 0x00 0x00 0x178a00f4 0x01 0x00 0x00 0x178a00f8 0x01 0x00 0x00 0x178a00fc 0x01 0x00 0x00 0x178a0100 0x01 0x00 0x00 0x178a0104 0x01 0x00 0x00 0x178a0118 0x01 0x00 0x00 0x178a011c 0x01 0x00 0x00 0x178a0120 0x01 0x00 0x00 0x178a0124 0x01 0x00 0x00 0x178a0128 0x01 0x00 0x00 0x178a012c 0x01 0x00 0x00 0x178a0130 0x01 0x00 0x00 0x178a0134 0x01 0x00 0x00 0x178a0138 0x01 0x00 0x00 0x178a0158 0x01 0x00 0x00 0x178a015c 0x01 0x00 0x00 0x178a0160 0x01 0x00 0x00 0x178a0164 0x01 0x00 0x00 0x178a0168 0x01 0x00 0x00 0x178a0170 0x01 0x00 0x00 0x178a0174 0x01 0x00 0x00 0x178a0188 0x01 0x00 0x00 0x178a018c 0x01 0x00 0x00 0x178a0190 0x01 0x00 0x00 0x178a0194 0x01 0x00 0x00 0x178a0198 0x01 0x00 0x00 0x178a01ac 0x01 0x00 0x00 0x178a01b0 0x01 0x00 0x00 0x178a01b4 0x01 0x00 0x00 0x178a01b8 0x01 0x00 0x00 0x178a01bc 0x01 0x00 0x00 0x178a01c0 0x01 0x00 0x00 0x178a01c8 0x01 0x00 0x00 0x17880010 0x01 0x00 0x00 0x17880024 0x01 0x00 0x00 0x17880038 0x01 0x00 0x00 0x1788003c 0x01 0x00 0x00 0x17880040 0x01 0x00 0x00 0x17880044 0x01 0x00 0x00 0x17880048 0x01 0x00 0x00 0x1788004c 0x01 0x00 0x00 0x17890010 0x01 0x00 0x00 0x17890024 0x01 0x00 0x00 0x17890038 0x01 0x00 0x00 0x1789003c 0x01 0x00 0x00 0x17890040 0x01 0x00 0x00 0x17890044 0x01 0x00 0x00 0x17890048 0x01 0x00 0x00 0x1789004c 0x01 0x00 0x00 0x178a0204 0x01 0x00 0x00 0x178a0244 0x01 0x00 0x00 0x17e30000 0x01 0x00 0x00 0x17e30008 0x01 0x00 0x00 0x17e30010 0x01 0x00 0x00 0x17e80000 0x01 0x00 0x00 0x17e80008 0x01 0x00 0x00 0x17e80010 0x01 0x00 0x00 0x17f80000 0x01 0x00 0x00 0x17f80008 0x01 0x00 0x00 0x17f80010 0x01 0x00 0x00 0x18080000 0x01 0x00 0x00 0x18080008 0x01 0x00 0x00 0x18080010 0x01 0x00 0x00 0x18180000 0x01 0x00 0x00 0x18180008 0x01 0x00 0x00 0x18180010 0x01 0x00 0x00 0x18280000 0x01 0x00 0x00 0x18280008 0x01 0x00 0x00 0x18280010 0x01 0x00 0x00 0x18380000 0x01 0x00 0x00 0x18380008 0x01 0x00 0x00 0x18380010 0x01 0x00 0x00 0x18480000 0x01 0x00 0x00 0x18480008 0x01 0x00 0x00 0x18480010 0x01 0x00 0x00 0x18580000 0x01 0x00 0x00 0x18580008 0x01 0x00 0x00 0x18580010 0x01 0x00 0x00 0x2407701c 0x01 0x00 0x00 0x24077030 0x01 0x00 0x00 0x2408005c 0x01 0x00 0x00 0x240800c8 0x01 0x00 0x00 0x240800d4 0x01 0x00 0x00 0x240800e0 0x01 0x00 0x00 0x240800ec 0x01 0x00 0x00 0x240800f8 0x01 0x00 0x00 0x240801b4 0x01 0x00 0x00 0x240a80f8 0x01 0x00 0x00 0x240a80fc 0x01 0x00 0x00 0x240a8100 0x01 0x00 0x00 0x240a8104 0x01 0x00 0x00 0x240a8108 0x01 0x00 0x00 0x240a810c 0x01 0x00 0x00 0x240a8110 0x01 0x00 0x00 0x240a8178 0x01 0x00 0x00 0x240a817c 0x01 0x00 0x00 0x240a8180 0x01 0x00 0x00 0x240a8184 0x01 0x00 0x00 0x240a8198 0x01 0x00 0x00 0x240a81a4 0x01 0x00 0x00 0x240a81b0 0x01 0x00 0x00 0x240a81bc 0x01 0x00 0x00 0x240a81c8 0x01 0x00 0x00 0x240a81cc 0x01 0x00 0x00 0x240a81f4 0x01 0x00 0x00 0x240a8214 0x01 0x00 0x00 0x240a8290 0x01 0x00 0x00 0x240a8804 0x01 0x00 0x00 0x240a880c 0x01 0x00 0x00 0x240a8860 0x01 0x00 0x00 0x240a8864 0x01 0x00 0x00 0x240a8868 0x01 0x00 0x00 0x240ba28c 0x01 0x00 0x00 0x240ba294 0x01 0x00 0x00 0x240ba29c 0x01 0x00 0x00 0x24186100 0x01 0x00 0x00 0x24186104 0x01 0x00 0x00 0x24186108 0x01 0x00 0x00 0x2418610c 0x01 0x00 0x00 0x24188100 0x01 0x00 0x00 0x2418d100 0x01 0x00 0x00 0x24401e64 0x01 0x00 0x00 0x24401ea0 0x01 0x00 0x00 0x24403e64 0x01 0x00 0x00 0x24403ea0 0x01 0x00 0x00 0x2440527c 0x01 0x00 0x00 0x24405290 0x01 0x00 0x00 0x244054ec 0x01 0x00 0x00 0x244054f4 0x01 0x00 0x00 0x24405514 0x01 0x00 0x00 0x2440551c 0x01 0x00 0x00 0x24405524 0x01 0x00 0x00 0x24405548 0x01 0x00 0x00 0x24405550 0x01 0x00 0x00 0x24405558 0x01 0x00 0x00 0x244055b8 0x01 0x00 0x00 0x244055c0 0x01 0x00 0x00 0x244055ec 0x01 0x00 0x00 0x24405870 0x01 0x00 0x00 0x244058a0 0x01 0x00 0x00 0x244058a8 0x01 0x00 0x00 0x244058b0 0x01 0x00 0x00 0x244058b8 0x01 0x00 0x00 0x244058d8 0x01 0x00 0x00 0x244058dc 0x01 0x00 0x00 0x244058f4 0x01 0x00 0x00 0x244058fc 0x01 0x00 0x00 0x24405920 0x01 0x00 0x00 0x24405928 0x01 0x00 0x00 0x24405944 0x01 0x00 0x00 0x24406604 0x01 0x00 0x00 0x2440660c 0x01 0x00 0x00 0x24440310 0x01 0x00 0x00 0x24440400 0x01 0x00 0x00 0x24440404 0x01 0x00 0x00 0x24440410 0x01 0x00 0x00 0x24440414 0x01 0x00 0x00 0x24440418 0x01 0x00 0x00 0x24440428 0x01 0x00 0x00 0x24440430 0x01 0x00 0x00 0x24440440 0x01 0x00 0x00 0x24440448 0x01 0x00 0x00 0x244404a0 0x01 0x00 0x00 0x244404b0 0x01 0x00 0x00 0x244404b4 0x01 0x00 0x00 0x244404b8 0x01 0x00 0x00 0x244404d0 0x01 0x00 0x00 0x244404d4 0x01 0x00 0x00 0x2444341c 0x01 0x00 0x00 0x24445804 0x01 0x00 0x00 0x2444590c 0x01 0x00 0x00 0x24445a14 0x01 0x00 0x00 0x24445c1c 0x01 0x00 0x00 0x24445c38 0x01 0x00 0x00 0x24449100 0x01 0x00 0x00 0x24449110 0x01 0x00 0x00 0x24449120 0x01 0x00 0x00 0x24449180 0x01 0x00 0x00 0x24449184 0x01 0x00 0x00 0x24460618 0x01 0x00 0x00 0x24460684 0x01 0x00 0x00 0x2446068c 0x01 0x00 0x00 0x24481e64 0x01 0x00 0x00 0x24481ea0 0x01 0x00 0x00 0x24483e64 0x01 0x00 0x00 0x24483ea0 0x01 0x00 0x00 0x2448527c 0x01 0x00 0x00 0x24485290 0x01 0x00 0x00 0x244854ec 0x01 0x00 0x00 0x244854f4 0x01 0x00 0x00 0x24485514 0x01 0x00 0x00 0x2448551c 0x01 0x00 0x00 0x24485524 0x01 0x00 0x00 0x24485548 0x01 0x00 0x00 0x24485550 0x01 0x00 0x00 0x24485558 0x01 0x00 0x00 0x244855b8 0x01 0x00 0x00 0x244855c0 0x01 0x00 0x00 0x244855ec 0x01 0x00 0x00 0x24485870 0x01 0x00 0x00 0x244858a0 0x01 0x00 0x00 0x244858a8 0x01 0x00 0x00 0x244858b0 0x01 0x00 0x00 0x244858b8 0x01 0x00 0x00 0x244858d8 0x01 0x00 0x00 0x244858dc 0x01 0x00 0x00 0x244858f4 0x01 0x00 0x00 0x244858fc 0x01 0x00 0x00 0x24485920 0x01 0x00 0x00 0x24485928 0x01 0x00 0x00 0x24485944 0x01 0x00 0x00 0x24486604 0x01 0x00 0x00 0x2448660c 0x01 0x00 0x00 0x244c0310 0x01 0x00 0x00 0x244c0400 0x01 0x00 0x00 0x244c0404 0x01 0x00 0x00 0x244c0410 0x01 0x00 0x00 0x244c0414 0x01 0x00 0x00 0x244c0418 0x01 0x00 0x00 0x244c0428 0x01 0x00 0x00 0x244c0430 0x01 0x00 0x00 0x244c0440 0x01 0x00 0x00 0x244c0448 0x01 0x00 0x00 0x244c04a0 0x01 0x00 0x00 0x244c04b0 0x01 0x00 0x00 0x244c04b4 0x01 0x00 0x00 0x244c04b8 0x01 0x00 0x00 0x244c04d0 0x01 0x00 0x00 0x244c04d4 0x01 0x00 0x00 0x244c341c 0x01 0x00 0x00 0x244c5804 0x01 0x00 0x00 0x244c590c 0x01 0x00 0x00 0x244c5a14 0x01 0x00 0x00 0x244c5c1c 0x01 0x00 0x00 0x244c5c38 0x01 0x00 0x00 0x244c9100 0x01 0x00 0x00 0x244c9110 0x01 0x00 0x00 0x244c9120 0x01 0x00 0x00 0x244c9180 0x01 0x00 0x00 0x244c9184 0x01 0x00 0x00 0x244e0618 0x01 0x00 0x00 0x244e0684 0x01 0x00 0x00 0x244e068c 0x01 0x00 0x00 0x24601e64 0x01 0x00 0x00 0x24601ea0 0x01 0x00 0x00 0x24603e64 0x01 0x00 0x00 0x24603ea0 0x01 0x00 0x00 0x2460527c 0x01 0x00 0x00 0x24605290 0x01 0x00 0x00 0x246054ec 0x01 0x00 0x00 0x246054f4 0x01 0x00 0x00 0x24605514 0x01 0x00 0x00 0x2460551c 0x01 0x00 0x00 0x24605524 0x01 0x00 0x00 0x24605548 0x01 0x00 0x00 0x24605550 0x01 0x00 0x00 0x24605558 0x01 0x00 0x00 0x246055b8 0x01 0x00 0x00 0x246055c0 0x01 0x00 0x00 0x246055ec 0x01 0x00 0x00 0x24605870 0x01 0x00 0x00 0x246058a0 0x01 0x00 0x00 0x246058a8 0x01 0x00 0x00 0x246058b0 0x01 0x00 0x00 0x246058b8 0x01 0x00 0x00 0x246058d8 0x01 0x00 0x00 0x246058dc 0x01 0x00 0x00 0x246058f4 0x01 0x00 0x00 0x246058fc 0x01 0x00 0x00 0x24605920 0x01 0x00 0x00 0x24605928 0x01 0x00 0x00 0x24605944 0x01 0x00 0x00 0x24606604 0x01 0x00 0x00 0x2460660c 0x01 0x00 0x00 0x24640310 0x01 0x00 0x00 0x24640400 0x01 0x00 0x00 0x24640404 0x01 0x00 0x00 0x24640410 0x01 0x00 0x00 0x24640414 0x01 0x00 0x00 0x24640418 0x01 0x00 0x00 0x24640428 0x01 0x00 0x00 0x24640430 0x01 0x00 0x00 0x24640440 0x01 0x00 0x00 0x24640448 0x01 0x00 0x00 0x246404a0 0x01 0x00 0x00 0x246404b0 0x01 0x00 0x00 0x246404b4 0x01 0x00 0x00 0x246404b8 0x01 0x00 0x00 0x246404d0 0x01 0x00 0x00 0x246404d4 0x01 0x00 0x00 0x2464341c 0x01 0x00 0x00 0x24645804 0x01 0x00 0x00 0x2464590c 0x01 0x00 0x00 0x24645a14 0x01 0x00 0x00 0x24645c1c 0x01 0x00 0x00 0x24645c38 0x01 0x00 0x00 0x24649100 0x01 0x00 0x00 0x24649110 0x01 0x00 0x00 0x24649120 0x01 0x00 0x00 0x24649180 0x01 0x00 0x00 0x24649184 0x01 0x00 0x00 0x24660618 0x01 0x00 0x00 0x24660684 0x01 0x00 0x00 0x2466068c 0x01 0x00 0x00 0x24681e64 0x01 0x00 0x00 0x24681ea0 0x01 0x00 0x00 0x24683e64 0x01 0x00 0x00 0x24683ea0 0x01 0x00 0x00 0x2468527c 0x01 0x00 0x00 0x24685290 0x01 0x00 0x00 0x246854ec 0x01 0x00 0x00 0x246854f4 0x01 0x00 0x00 0x24685514 0x01 0x00 0x00 0x2468551c 0x01 0x00 0x00 0x24685524 0x01 0x00 0x00 0x24685548 0x01 0x00 0x00 0x24685550 0x01 0x00 0x00 0x24685558 0x01 0x00 0x00 0x246855b8 0x01 0x00 0x00 0x246855c0 0x01 0x00 0x00 0x246855ec 0x01 0x00 0x00 0x24685870 0x01 0x00 0x00 0x246858a0 0x01 0x00 0x00 0x246858a8 0x01 0x00 0x00 0x246858b0 0x01 0x00 0x00 0x246858b8 0x01 0x00 0x00 0x246858d8 0x01 0x00 0x00 0x246858dc 0x01 0x00 0x00 0x246858f4 0x01 0x00 0x00 0x246858fc 0x01 0x00 0x00 0x24685920 0x01 0x00 0x00 0x24685928 0x01 0x00 0x00 0x24685944 0x01 0x00 0x00 0x24686604 0x01 0x00 0x00 0x2468660c 0x01 0x00 0x00 0x246c0310 0x01 0x00 0x00 0x246c0400 0x01 0x00 0x00 0x246c0404 0x01 0x00 0x00 0x246c0410 0x01 0x00 0x00 0x246c0414 0x01 0x00 0x00 0x246c0418 0x01 0x00 0x00 0x246c0428 0x01 0x00 0x00 0x246c0430 0x01 0x00 0x00 0x246c0440 0x01 0x00 0x00 0x246c0448 0x01 0x00 0x00 0x246c04a0 0x01 0x00 0x00 0x246c04b0 0x01 0x00 0x00 0x246c04b4 0x01 0x00 0x00 0x246c04b8 0x01 0x00 0x00 0x246c04d0 0x01 0x00 0x00 0x246c04d4 0x01 0x00 0x00 0x246c341c 0x01 0x00 0x00 0x246c5804 0x01 0x00 0x00 0x246c590c 0x01 0x00 0x00 0x246c5a14 0x01 0x00 0x00 0x246c5c1c 0x01 0x00 0x00 0x246c5c38 0x01 0x00 0x00 0x246c9100 0x01 0x00 0x00 0x246c9110 0x01 0x00 0x00 0x246c9120 0x01 0x00 0x00 0x246c9180 0x01 0x00 0x00 0x246c9184 0x01 0x00 0x00 0x246e0618 0x01 0x00 0x00 0x246e0684 0x01 0x00 0x00 0x246e068c 0x01 0x00 0x00 0x24840310 0x01 0x00 0x00 0x24840400 0x01 0x00 0x00 0x24840404 0x01 0x00 0x00 0x24840410 0x01 0x00 0x00 0x24840414 0x01 0x00 0x00 0x24840418 0x01 0x00 0x00 0x24840428 0x01 0x00 0x00 0x24840430 0x01 0x00 0x00 0x24840440 0x01 0x00 0x00 0x24840448 0x01 0x00 0x00 0x248404a0 0x01 0x00 0x00 0x248404b0 0x01 0x00 0x00 0x248404b4 0x01 0x00 0x00 0x248404b8 0x01 0x00 0x00 0x248404d0 0x01 0x00 0x00 0x248404d4 0x01 0x00 0x00 0x2484341c 0x01 0x00 0x00 0x24845804 0x01 0x00 0x00 0x2484590c 0x01 0x00 0x00 0x24845a14 0x01 0x00 0x00 0x24845c1c 0x01 0x00 0x00 0x24845c38 0x01 0x00 0x00 0x24849100 0x01 0x00 0x00 0x24849110 0x01 0x00 0x00 0x24849120 0x01 0x00 0x00 0x24849180 0x01 0x00 0x00 0x24849184 0x01 0x00 0x00 0x24860618 0x01 0x00 0x00 0x24860684 0x01 0x00 0x00 0x2486068c 0x01 0x00 0x00 0x248c0310 0x01 0x00 0x00 0x248c0400 0x01 0x00 0x00 0x248c0404 0x01 0x00 0x00 0x248c0410 0x01 0x00 0x00 0x248c0414 0x01 0x00 0x00 0x248c0418 0x01 0x00 0x00 0x248c0428 0x01 0x00 0x00 0x248c0430 0x01 0x00 0x00 0x248c0440 0x01 0x00 0x00 0x248c0448 0x01 0x00 0x00 0x248c04a0 0x01 0x00 0x00 0x248c04b0 0x01 0x00 0x00 0x248c04b4 0x01 0x00 0x00 0x248c04b8 0x01 0x00 0x00 0x248c04d0 0x01 0x00 0x00 0x248c04d4 0x01 0x00 0x00 0x248c341c 0x01 0x00 0x00 0x248c5804 0x01 0x00 0x00 0x248c590c 0x01 0x00 0x00 0x248c5a14 0x01 0x00 0x00 0x248c5c1c 0x01 0x00 0x00 0x248c5c38 0x01 0x00 0x00 0x248c9100 0x01 0x00 0x00 0x248c9110 0x01 0x00 0x00 0x248c9120 0x01 0x00 0x00 0x248c9180 0x01 0x00 0x00 0x248c9184 0x01 0x00 0x00 0x248e0618 0x01 0x00 0x00 0x248e0684 0x01 0x00 0x00 0x248e068c 0x01 0x00 0x00 0x25020348 0x01 0x00 0x00 0x25020480 0x01 0x00 0x00 0x25022400 0x01 0x00 0x00 0x25023220 0x01 0x00 0x00 0x25023224 0x01 0x00 0x00 0x25023228 0x01 0x00 0x00 0x2502322c 0x01 0x00 0x00 0x25023258 0x01 0x00 0x00 0x2502325c 0x01 0x00 0x00 0x25023308 0x01 0x00 0x00 0x25023318 0x01 0x00 0x00 0x25038100 0x01 0x00 0x00 0x2503c030 0x01 0x00 0x00 0x25042044 0x01 0x00 0x00 0x25042048 0x01 0x00 0x00 0x2504204c 0x01 0x00 0x00 0x250420b0 0x01 0x00 0x00 0x25042104 0x01 0x00 0x00 0x25042114 0x01 0x00 0x00 0x25048004 0x01 0x00 0x00 0x25048008 0x01 0x00 0x00 0x2504800c 0x01 0x00 0x00 0x25048010 0x01 0x00 0x00 0x25048014 0x01 0x00 0x00 0x2504c030 0x01 0x00 0x00 0x25050020 0x01 0x00 0x00 0x2506004c 0x01 0x00 0x00 0x25060050 0x01 0x00 0x00 0x25060054 0x01 0x00 0x00 0x25060058 0x01 0x00 0x00 0x2506005c 0x01 0x00 0x00 0x25060060 0x01 0x00 0x00 0x25060064 0x01 0x00 0x00 0x25060068 0x01 0x00 0x00 0x25220348 0x01 0x00 0x00 0x25220480 0x01 0x00 0x00 0x25222400 0x01 0x00 0x00 0x25223220 0x01 0x00 0x00 0x25223224 0x01 0x00 0x00 0x25223228 0x01 0x00 0x00 0x2522322c 0x01 0x00 0x00 0x25223258 0x01 0x00 0x00 0x2522325c 0x01 0x00 0x00 0x25223308 0x01 0x00 0x00 0x25223318 0x01 0x00 0x00 0x25238100 0x01 0x00 0x00 0x2523c030 0x01 0x00 0x00 0x25242044 0x01 0x00 0x00 0x25242048 0x01 0x00 0x00 0x2524204c 0x01 0x00 0x00 0x252420b0 0x01 0x00 0x00 0x25242104 0x01 0x00 0x00 0x25242114 0x01 0x00 0x00 0x25248004 0x01 0x00 0x00 0x25248008 0x01 0x00 0x00 0x2524800c 0x01 0x00 0x00 0x25248010 0x01 0x00 0x00 0x25248014 0x01 0x00 0x00 0x2524c030 0x01 0x00 0x00 0x25250020 0x01 0x00 0x00 0x2526004c 0x01 0x00 0x00 0x25260050 0x01 0x00 0x00 0x25260054 0x01 0x00 0x00 0x25260058 0x01 0x00 0x00 0x2526005c 0x01 0x00 0x00 0x25260060 0x01 0x00 0x00 0x25260064 0x01 0x00 0x00 0x25260068 0x01 0x00 0x00 0x25420348 0x01 0x00 0x00 0x25420480 0x01 0x00 0x00 0x25422400 0x01 0x00 0x00 0x25423220 0x01 0x00 0x00 0x25423224 0x01 0x00 0x00 0x25423228 0x01 0x00 0x00 0x2542322c 0x01 0x00 0x00 0x25423258 0x01 0x00 0x00 0x2542325c 0x01 0x00 0x00 0x25423308 0x01 0x00 0x00 0x25423318 0x01 0x00 0x00 0x25438100 0x01 0x00 0x00 0x2543c030 0x01 0x00 0x00 0x25442044 0x01 0x00 0x00 0x25442048 0x01 0x00 0x00 0x2544204c 0x01 0x00 0x00 0x254420b0 0x01 0x00 0x00 0x25442104 0x01 0x00 0x00 0x25442114 0x01 0x00 0x00 0x25448004 0x01 0x00 0x00 0x25448008 0x01 0x00 0x00 0x2544800c 0x01 0x00 0x00 0x25448010 0x01 0x00 0x00 0x25448014 0x01 0x00 0x00 0x2544c030 0x01 0x00 0x00 0x25450020 0x01 0x00 0x00 0x2546004c 0x01 0x00 0x00 0x25460050 0x01 0x00 0x00 0x25460054 0x01 0x00 0x00 0x25460058 0x01 0x00 0x00 0x2546005c 0x01 0x00 0x00 0x25460060 0x01 0x00 0x00 0x25460064 0x01 0x00 0x00 0x25460068 0x01 0x00 0x00 0x25620348 0x01 0x00 0x00 0x25620480 0x01 0x00 0x00 0x25622400 0x01 0x00 0x00 0x25623220 0x01 0x00 0x00 0x25623224 0x01 0x00 0x00 0x25623228 0x01 0x00 0x00 0x2562322c 0x01 0x00 0x00 0x25623258 0x01 0x00 0x00 0x2562325c 0x01 0x00 0x00 0x25623308 0x01 0x00 0x00 0x25623318 0x01 0x00 0x00 0x25638100 0x01 0x00 0x00 0x2563c030 0x01 0x00 0x00 0x25642044 0x01 0x00 0x00 0x25642048 0x01 0x00 0x00 0x2564204c 0x01 0x00 0x00 0x256420b0 0x01 0x00 0x00 0x25642104 0x01 0x00 0x00 0x25642114 0x01 0x00 0x00 0x25648004 0x01 0x00 0x00 0x25648008 0x01 0x00 0x00 0x2564800c 0x01 0x00 0x00 0x25648010 0x01 0x00 0x00 0x25648014 0x01 0x00 0x00 0x2564c030 0x01 0x00 0x00 0x25650020 0x01 0x00 0x00 0x2566004c 0x01 0x00 0x00 0x25660050 0x01 0x00 0x00 0x25660054 0x01 0x00 0x00 0x25660058 0x01 0x00 0x00 0x2566005c 0x01 0x00 0x00 0x25660060 0x01 0x00 0x00 0x25660064 0x01 0x00 0x00 0x25660068 0x01 0x00 0x00 0x25820348 0x01 0x00 0x00 0x25820480 0x01 0x00 0x00 0x25822400 0x01 0x00 0x00 0x25823220 0x01 0x00 0x00 0x25823224 0x01 0x00 0x00 0x25823228 0x01 0x00 0x00 0x2582322c 0x01 0x00 0x00 0x25823258 0x01 0x00 0x00 0x2582325c 0x01 0x00 0x00 0x25823308 0x01 0x00 0x00 0x25823318 0x01 0x00 0x00 0x25838100 0x01 0x00 0x00 0x2583c030 0x01 0x00 0x00 0x25842044 0x01 0x00 0x00 0x25842048 0x01 0x00 0x00 0x2584204c 0x01 0x00 0x00 0x258420b0 0x01 0x00 0x00 0x25842104 0x01 0x00 0x00 0x25842114 0x01 0x00 0x00 0x25848004 0x01 0x00 0x00 0x25848008 0x01 0x00 0x00 0x2584800c 0x01 0x00 0x00 0x25848010 0x01 0x00 0x00 0x25848014 0x01 0x00 0x00 0x2584c030 0x01 0x00 0x00 0x25850020 0x01 0x00 0x00 0x2586004c 0x01 0x00 0x00 0x25860050 0x01 0x00 0x00 0x25860054 0x01 0x00 0x00 0x25860058 0x01 0x00 0x00 0x2586005c 0x01 0x00 0x00 0x25860060 0x01 0x00 0x00 0x25860064 0x01 0x00 0x00 0x25860068 0x01 0x00 0x00 0x25a20348 0x01 0x00 0x00 0x25a20480 0x01 0x00 0x00 0x25a22400 0x01 0x00 0x00 0x25a23220 0x01 0x00 0x00 0x25a23224 0x01 0x00 0x00 0x25a23228 0x01 0x00 0x00 0x25a2322c 0x01 0x00 0x00 0x25a23258 0x01 0x00 0x00 0x25a2325c 0x01 0x00 0x00 0x25a23308 0x01 0x00 0x00 0x25a23318 0x01 0x00 0x00 0x25a38100 0x01 0x00 0x00 0x25a3c030 0x01 0x00 0x00 0x25a42044 0x01 0x00 0x00 0x25a42048 0x01 0x00 0x00 0x25a4204c 0x01 0x00 0x00 0x25a420b0 0x01 0x00 0x00 0x25a42104 0x01 0x00 0x00 0x25a42114 0x01 0x00 0x00 0x25a48004 0x01 0x00 0x00 0x25a48008 0x01 0x00 0x00 0x25a4800c 0x01 0x00 0x00 0x25a48010 0x01 0x00 0x00 0x25a48014 0x01 0x00 0x00 0x25a4c030 0x01 0x00 0x00 0x25a50020 0x01 0x00 0x00 0x25a6004c 0x01 0x00 0x00 0x25a60050 0x01 0x00 0x00 0x25a60054 0x01 0x00 0x00 0x25a60058 0x01 0x00 0x00 0x25a6005c 0x01 0x00 0x00 0x25a60060 0x01 0x00 0x00 0x25a60064 0x01 0x00 0x00 0x25a60068 0x01 0x00 0x00 0x250a002c 0x01 0x00 0x00 0x250a009c 0x01 0x00 0x00 0x250a00a0 0x01 0x00 0x00 0x250a00a8 0x01 0x00 0x00 0x250a00ac 0x01 0x00 0x00 0x250a00b0 0x01 0x00 0x00 0x250a00b8 0x01 0x00 0x00 0x250a00c0 0x01 0x00 0x00 0x250a00c4 0x01 0x00 0x00 0x250a00cc 0x01 0x00 0x00 0x250a00d0 0x01 0x00 0x00 0x250a00d4 0x01 0x00 0x00 0x250a00d8 0x01 0x00 0x00 0x250a00e0 0x01 0x00 0x00 0x250a00e8 0x01 0x00 0x00 0x250a00f0 0x01 0x00 0x00 0x250a00f0 0x01 0x00 0x00 0x250a0100 0x01 0x00 0x00 0x250a0108 0x01 0x00 0x00 0x250a0110 0x01 0x00 0x00 0x250a0118 0x01 0x00 0x00 0x250a0120 0x01 0x00 0x00 0x250a0128 0x01 0x00 0x00 0x250a1010 0x01 0x00 0x00 0x250a1070 0x01 0x00 0x00 0x250a3004 0x01 0x00 0x00 0x254a002c 0x01 0x00 0x00 0x254a009c 0x01 0x00 0x00 0x254a00a0 0x01 0x00 0x00 0x254a00a8 0x01 0x00 0x00 0x254a00ac 0x01 0x00 0x00 0x254a00b0 0x01 0x00 0x00 0x254a00b8 0x01 0x00 0x00 0x254a00c0 0x01 0x00 0x00 0x254a00c4 0x01 0x00 0x00 0x254a00cc 0x01 0x00 0x00 0x254a00d0 0x01 0x00 0x00 0x254a00d4 0x01 0x00 0x00 0x254a00d8 0x01 0x00 0x00 0x254a00e0 0x01 0x00 0x00 0x254a00e8 0x01 0x00 0x00 0x254a00f0 0x01 0x00 0x00 0x254a00f0 0x01 0x00 0x00 0x254a0100 0x01 0x00 0x00 0x254a0108 0x01 0x00 0x00 0x254a0110 0x01 0x00 0x00 0x254a0118 0x01 0x00 0x00 0x254a0120 0x01 0x00 0x00 0x254a0128 0x01 0x00 0x00 0x254a1010 0x01 0x00 0x00 0x254a1070 0x01 0x00 0x00 0x254a3004 0x01 0x00 0x00 0x252a002c 0x01 0x00 0x00 0x252a009c 0x01 0x00 0x00 0x252a00a0 0x01 0x00 0x00 0x252a00a8 0x01 0x00 0x00 0x252a00ac 0x01 0x00 0x00 0x252a00b0 0x01 0x00 0x00 0x252a00b8 0x01 0x00 0x00 0x252a00c0 0x01 0x00 0x00 0x252a00c4 0x01 0x00 0x00 0x252a00cc 0x01 0x00 0x00 0x252a00d0 0x01 0x00 0x00 0x252a00d4 0x01 0x00 0x00 0x252a00d8 0x01 0x00 0x00 0x252a00e0 0x01 0x00 0x00 0x252a00e8 0x01 0x00 0x00 0x252a00f0 0x01 0x00 0x00 0x252a00f0 0x01 0x00 0x00 0x252a0100 0x01 0x00 0x00 0x252a0108 0x01 0x00 0x00 0x252a0110 0x01 0x00 0x00 0x252a0118 0x01 0x00 0x00 0x252a0120 0x01 0x00 0x00 0x252a0128 0x01 0x00 0x00 0x252a1010 0x01 0x00 0x00 0x252a1070 0x01 0x00 0x00 0x252a3004 0x01 0x00 0x00 0x256a002c 0x01 0x00 0x00 0x256a009c 0x01 0x00 0x00 0x256a00a0 0x01 0x00 0x00 0x256a00a8 0x01 0x00 0x00 0x256a00ac 0x01 0x00 0x00 0x256a00b0 0x01 0x00 0x00 0x256a00b8 0x01 0x00 0x00 0x256a00c0 0x01 0x00 0x00 0x256a00c4 0x01 0x00 0x00 0x256a00cc 0x01 0x00 0x00 0x256a00d0 0x01 0x00 0x00 0x256a00d4 0x01 0x00 0x00 0x256a00d8 0x01 0x00 0x00 0x256a00e0 0x01 0x00 0x00 0x256a00e8 0x01 0x00 0x00 0x256a00f0 0x01 0x00 0x00 0x256a00f0 0x01 0x00 0x00 0x256a0100 0x01 0x00 0x00 0x256a0108 0x01 0x00 0x00 0x256a0110 0x01 0x00 0x00 0x256a0118 0x01 0x00 0x00 0x256a0120 0x01 0x00 0x00 0x256a0128 0x01 0x00 0x00 0x256a1010 0x01 0x00 0x00 0x256a1070 0x01 0x00 0x00 0x256a3004 0x01 0x00 0x00 0x25076020 0x01 0x00 0x00 0x25076024 0x01 0x00 0x00 0x25076028 0x01 0x00 0x00 0x25076034 0x01 0x00 0x00 0x25076038 0x01 0x00 0x00 0x25076040 0x01 0x00 0x00 0x25076058 0x01 0x00 0x00 0x25076060 0x01 0x00 0x00 0x25076064 0x01 0x00 0x00 0x25076200 0x01 0x00 0x00 0x25077020 0x01 0x00 0x00 0x25077030 0x01 0x00 0x00 0x25077034 0x01 0x00 0x00 0x25077038 0x01 0x00 0x00 0x2507703c 0x01 0x00 0x00 0x25077040 0x01 0x00 0x00 0x25077044 0x01 0x00 0x00 0x25077048 0x01 0x00 0x00 0x2507704c 0x01 0x00 0x00 0x25077050 0x01 0x00 0x00 0x25077054 0x01 0x00 0x00 0x25077058 0x01 0x00 0x00 0x2507705c 0x01 0x00 0x00 0x25077060 0x01 0x00 0x00 0x25077064 0x01 0x00 0x00 0x25077068 0x01 0x00 0x00 0x2507706c 0x01 0x00 0x00 0x25077070 0x01 0x00 0x00 0x25077074 0x01 0x00 0x00 0x25077078 0x01 0x00 0x00 0x2507707c 0x01 0x00 0x00 0x25077084 0x01 0x00 0x00 0x25077090 0x01 0x00 0x00 0x25077094 0x01 0x00 0x00 0x25077098 0x01 0x00 0x00 0x2507709c 0x01 0x00 0x00 0x250770a0 0x01 0x00 0x00 0x25077218 0x01 0x00 0x00 0x2507721c 0x01 0x00 0x00 0x25077220 0x01 0x00 0x00 0x25077224 0x01 0x00 0x00 0x25077228 0x01 0x00 0x00 0x2507722c 0x01 0x00 0x00 0x25077230 0x01 0x00 0x00 0x25077234 0x01 0x00 0x00 0x25476020 0x01 0x00 0x00 0x25476024 0x01 0x00 0x00 0x25476028 0x01 0x00 0x00 0x25476034 0x01 0x00 0x00 0x25476038 0x01 0x00 0x00 0x25476040 0x01 0x00 0x00 0x25476058 0x01 0x00 0x00 0x25476060 0x01 0x00 0x00 0x25476064 0x01 0x00 0x00 0x25476200 0x01 0x00 0x00 0x25477020 0x01 0x00 0x00 0x25477030 0x01 0x00 0x00 0x25477034 0x01 0x00 0x00 0x25477038 0x01 0x00 0x00 0x2547703c 0x01 0x00 0x00 0x25477040 0x01 0x00 0x00 0x25477044 0x01 0x00 0x00 0x25477048 0x01 0x00 0x00 0x2547704c 0x01 0x00 0x00 0x25477050 0x01 0x00 0x00 0x25477054 0x01 0x00 0x00 0x25477058 0x01 0x00 0x00 0x2547705c 0x01 0x00 0x00 0x25477060 0x01 0x00 0x00 0x25477064 0x01 0x00 0x00 0x25477068 0x01 0x00 0x00 0x2547706c 0x01 0x00 0x00 0x25477070 0x01 0x00 0x00 0x25477074 0x01 0x00 0x00 0x25477078 0x01 0x00 0x00 0x2547707c 0x01 0x00 0x00 0x25477084 0x01 0x00 0x00 0x25477090 0x01 0x00 0x00 0x25477094 0x01 0x00 0x00 0x25477098 0x01 0x00 0x00 0x2547709c 0x01 0x00 0x00 0x254770a0 0x01 0x00 0x00 0x25477218 0x01 0x00 0x00 0x2547721c 0x01 0x00 0x00 0x25477220 0x01 0x00 0x00 0x25477224 0x01 0x00 0x00 0x25477228 0x01 0x00 0x00 0x2547722c 0x01 0x00 0x00 0x25477230 0x01 0x00 0x00 0x25477234 0x01 0x00 0x00 0x25276020 0x01 0x00 0x00 0x25276024 0x01 0x00 0x00 0x25276028 0x01 0x00 0x00 0x25276034 0x01 0x00 0x00 0x25276038 0x01 0x00 0x00 0x25276040 0x01 0x00 0x00 0x25276058 0x01 0x00 0x00 0x25276060 0x01 0x00 0x00 0x25276064 0x01 0x00 0x00 0x25276200 0x01 0x00 0x00 0x25277020 0x01 0x00 0x00 0x25277030 0x01 0x00 0x00 0x25277034 0x01 0x00 0x00 0x25277038 0x01 0x00 0x00 0x2527703c 0x01 0x00 0x00 0x25277040 0x01 0x00 0x00 0x25277044 0x01 0x00 0x00 0x25277048 0x01 0x00 0x00 0x2527704c 0x01 0x00 0x00 0x25277050 0x01 0x00 0x00 0x25277054 0x01 0x00 0x00 0x25277058 0x01 0x00 0x00 0x2527705c 0x01 0x00 0x00 0x25277060 0x01 0x00 0x00 0x25277064 0x01 0x00 0x00 0x25277068 0x01 0x00 0x00 0x2527706c 0x01 0x00 0x00 0x25277070 0x01 0x00 0x00 0x25277074 0x01 0x00 0x00 0x25277078 0x01 0x00 0x00 0x2527707c 0x01 0x00 0x00 0x25277084 0x01 0x00 0x00 0x25277090 0x01 0x00 0x00 0x25277094 0x01 0x00 0x00 0x25277098 0x01 0x00 0x00 0x2527709c 0x01 0x00 0x00 0x252770a0 0x01 0x00 0x00 0x25277218 0x01 0x00 0x00 0x2527721c 0x01 0x00 0x00 0x25277220 0x01 0x00 0x00 0x25277224 0x01 0x00 0x00 0x25277228 0x01 0x00 0x00 0x2527722c 0x01 0x00 0x00 0x25277230 0x01 0x00 0x00 0x25277234 0x01 0x00 0x00 0x25676020 0x01 0x00 0x00 0x25676024 0x01 0x00 0x00 0x25676028 0x01 0x00 0x00 0x25676034 0x01 0x00 0x00 0x25676038 0x01 0x00 0x00 0x25676040 0x01 0x00 0x00 0x25676058 0x01 0x00 0x00 0x25676060 0x01 0x00 0x00 0x25676064 0x01 0x00 0x00 0x25676200 0x01 0x00 0x00 0x25677020 0x01 0x00 0x00 0x25677030 0x01 0x00 0x00 0x25677034 0x01 0x00 0x00 0x25677038 0x01 0x00 0x00 0x2567703c 0x01 0x00 0x00 0x25677040 0x01 0x00 0x00 0x25677044 0x01 0x00 0x00 0x25677048 0x01 0x00 0x00 0x2567704c 0x01 0x00 0x00 0x25677050 0x01 0x00 0x00 0x25677054 0x01 0x00 0x00 0x25677058 0x01 0x00 0x00 0x2567705c 0x01 0x00 0x00 0x25677060 0x01 0x00 0x00 0x25677064 0x01 0x00 0x00 0x25677068 0x01 0x00 0x00 0x2567706c 0x01 0x00 0x00 0x25677070 0x01 0x00 0x00 0x25677074 0x01 0x00 0x00 0x25677078 0x01 0x00 0x00 0x2567707c 0x01 0x00 0x00 0x25677084 0x01 0x00 0x00 0x25677090 0x01 0x00 0x00 0x25677094 0x01 0x00 0x00 0x25677098 0x01 0x00 0x00 0x2567709c 0x01 0x00 0x00 0x256770a0 0x01 0x00 0x00 0x25677218 0x01 0x00 0x00 0x2567721c 0x01 0x00 0x00 0x25677220 0x01 0x00 0x00 0x25677224 0x01 0x00 0x00 0x25677228 0x01 0x00 0x00 0x2567722c 0x01 0x00 0x00 0x25677230 0x01 0x00 0x00 0x25677234 0x01 0x00 0x00 0x250a6008 0x01 0x00 0x00 0x250a600c 0x01 0x00 0x00 0x250a6010 0x01 0x00 0x00 0x250a7008 0x01 0x00 0x00 0x250a700c 0x01 0x00 0x00 0x250a7010 0x01 0x00 0x00 0x254a6008 0x01 0x00 0x00 0x254a600c 0x01 0x00 0x00 0x254a6010 0x01 0x00 0x00 0x254a7008 0x01 0x00 0x00 0x254a700c 0x01 0x00 0x00 0x254a7010 0x01 0x00 0x00 0x252a6008 0x01 0x00 0x00 0x252a600c 0x01 0x00 0x00 0x252a6010 0x01 0x00 0x00 0x252a7008 0x01 0x00 0x00 0x252a700c 0x01 0x00 0x00 0x252a7010 0x01 0x00 0x00 0x256a6008 0x01 0x00 0x00 0x256a600c 0x01 0x00 0x00 0x256a6010 0x01 0x00 0x00 0x256a7008 0x01 0x00 0x00 0x256a700c 0x01 0x00 0x00 0x256a7010 0x01 0x00 0x00 0x2507718c 0x01 0x00 0x00 0x250771b0 0x01 0x00 0x00 0x25077204 0x01 0x00 0x00 0x25077208 0x01 0x00 0x00 0x2507720c 0x01 0x00 0x00 0x25077210 0x01 0x00 0x00 0x25077214 0x01 0x00 0x00 0x25023210 0x01 0x00 0x00 0x25025010 0x01 0x00 0x00 0x25025000 0x01 0x00 0x00 0x25040064 0x01 0x00 0x00 0x25040070 0x01 0x00 0x00 0x25040074 0x01 0x00 0x00 0x25040078 0x01 0x00 0x00 0x2504007c 0x01 0x00 0x00 0x25040080 0x01 0x00 0x00 0x2504002c 0x01 0x00 0x00 0x25040030 0x01 0x00 0x00 0x25040034 0x01 0x00 0x00 0x25040038 0x01 0x00 0x00 0x25040048 0x01 0x00 0x00 0x2504004c 0x01 0x00 0x00 0x25040050 0x01 0x00 0x00 0x25040054 0x01 0x00 0x00 0x25040058 0x01 0x00 0x00 0x25040060 0x01 0x00 0x00 0x2547718c 0x01 0x00 0x00 0x254771b0 0x01 0x00 0x00 0x25477204 0x01 0x00 0x00 0x25477208 0x01 0x00 0x00 0x2547720c 0x01 0x00 0x00 0x25477210 0x01 0x00 0x00 0x25477214 0x01 0x00 0x00 0x25423210 0x01 0x00 0x00 0x25425010 0x01 0x00 0x00 0x25425000 0x01 0x00 0x00 0x25440064 0x01 0x00 0x00 0x25440070 0x01 0x00 0x00 0x25440074 0x01 0x00 0x00 0x25440078 0x01 0x00 0x00 0x2544007c 0x01 0x00 0x00 0x25440080 0x01 0x00 0x00 0x2544002c 0x01 0x00 0x00 0x25440030 0x01 0x00 0x00 0x25440034 0x01 0x00 0x00 0x25440038 0x01 0x00 0x00 0x25440048 0x01 0x00 0x00 0x2544004c 0x01 0x00 0x00 0x25440050 0x01 0x00 0x00 0x25440054 0x01 0x00 0x00 0x25440058 0x01 0x00 0x00 0x25440060 0x01 0x00 0x00 0x2527718c 0x01 0x00 0x00 0x252771b0 0x01 0x00 0x00 0x25277204 0x01 0x00 0x00 0x25277208 0x01 0x00 0x00 0x2527720c 0x01 0x00 0x00 0x25277210 0x01 0x00 0x00 0x25277214 0x01 0x00 0x00 0x25223210 0x01 0x00 0x00 0x25225010 0x01 0x00 0x00 0x25225000 0x01 0x00 0x00 0x25240064 0x01 0x00 0x00 0x25240070 0x01 0x00 0x00 0x25240074 0x01 0x00 0x00 0x25240078 0x01 0x00 0x00 0x2524007c 0x01 0x00 0x00 0x25240080 0x01 0x00 0x00 0x2524002c 0x01 0x00 0x00 0x25240030 0x01 0x00 0x00 0x25240034 0x01 0x00 0x00 0x25240038 0x01 0x00 0x00 0x25240048 0x01 0x00 0x00 0x2524004c 0x01 0x00 0x00 0x25240050 0x01 0x00 0x00 0x25240054 0x01 0x00 0x00 0x25240058 0x01 0x00 0x00 0x25240060 0x01 0x00 0x00 0x2567718c 0x01 0x00 0x00 0x256771b0 0x01 0x00 0x00 0x25677204 0x01 0x00 0x00 0x25677208 0x01 0x00 0x00 0x2567720c 0x01 0x00 0x00 0x25677210 0x01 0x00 0x00 0x25677214 0x01 0x00 0x00 0x25623210 0x01 0x00 0x00 0x25625010 0x01 0x00 0x00 0x25625000 0x01 0x00 0x00 0x25640064 0x01 0x00 0x00 0x25640070 0x01 0x00 0x00 0x25640074 0x01 0x00 0x00 0x25640078 0x01 0x00 0x00 0x2564007c 0x01 0x00 0x00 0x25640080 0x01 0x00 0x00 0x2564002c 0x01 0x00 0x00 0x25640030 0x01 0x00 0x00 0x25640034 0x01 0x00 0x00 0x25640038 0x01 0x00 0x00 0x25640048 0x01 0x00 0x00 0x2564004c 0x01 0x00 0x00 0x25640050 0x01 0x00 0x00 0x25640054 0x01 0x00 0x00 0x25640058 0x01 0x00 0x00 0x25640060 0x01 0x00 0x00 0x250a9004 0x01 0x00 0x00 0x250a9010 0x01 0x00 0x00 0x250a9014 0x01 0x00 0x00 0x250a9018 0x01 0x00 0x00 0x250a9020 0x01 0x00 0x00 0x250a9024 0x01 0x00 0x00 0x250a9028 0x01 0x00 0x00 0x250a9030 0x01 0x00 0x00 0x250a9034 0x01 0x00 0x00 0x250a9038 0x01 0x00 0x00 0x250a9040 0x01 0x00 0x00 0x250a9044 0x01 0x00 0x00 0x250a9048 0x01 0x00 0x00 0x250a9050 0x01 0x00 0x00 0x250a9054 0x01 0x00 0x00 0x250a9058 0x01 0x00 0x00 0x250aa004 0x01 0x00 0x00 0x250aa010 0x01 0x00 0x00 0x250aa014 0x01 0x00 0x00 0x250aa018 0x01 0x00 0x00 0x250aa020 0x01 0x00 0x00 0x250aa024 0x01 0x00 0x00 0x250aa028 0x01 0x00 0x00 0x250aa030 0x01 0x00 0x00 0x250aa034 0x01 0x00 0x00 0x250aa038 0x01 0x00 0x00 0x250aa040 0x01 0x00 0x00 0x250aa044 0x01 0x00 0x00 0x250aa048 0x01 0x00 0x00 0x250aa050 0x01 0x00 0x00 0x250aa054 0x01 0x00 0x00 0x250aa058 0x01 0x00 0x00 0x250b001c 0x01 0x00 0x00 0x250b101c 0x01 0x00 0x00 0x250b201c 0x01 0x00 0x00 0x250b301c 0x01 0x00 0x00 0x250b401c 0x01 0x00 0x00 0x250b501c 0x01 0x00 0x00 0x250b601c 0x01 0x00 0x00 0x250b701c 0x01 0x00 0x00 0x250b801c 0x01 0x00 0x00 0x250b901c 0x01 0x00 0x00 0x250ba01c 0x01 0x00 0x00 0x250bb01c 0x01 0x00 0x00 0x250bc01c 0x01 0x00 0x00 0x250bd01c 0x01 0x00 0x00 0x250be01c 0x01 0x00 0x00 0x250bf01c 0x01 0x00 0x00 0x254a9004 0x01 0x00 0x00 0x254a9010 0x01 0x00 0x00 0x254a9014 0x01 0x00 0x00 0x254a9018 0x01 0x00 0x00 0x254a9020 0x01 0x00 0x00 0x254a9024 0x01 0x00 0x00 0x254a9028 0x01 0x00 0x00 0x254a9030 0x01 0x00 0x00 0x254a9034 0x01 0x00 0x00 0x254a9038 0x01 0x00 0x00 0x254a9040 0x01 0x00 0x00 0x254a9044 0x01 0x00 0x00 0x254a9048 0x01 0x00 0x00 0x254a9050 0x01 0x00 0x00 0x254a9054 0x01 0x00 0x00 0x254a9058 0x01 0x00 0x00 0x254aa004 0x01 0x00 0x00 0x254aa010 0x01 0x00 0x00 0x254aa014 0x01 0x00 0x00 0x254aa018 0x01 0x00 0x00 0x254aa020 0x01 0x00 0x00 0x254aa024 0x01 0x00 0x00 0x254aa028 0x01 0x00 0x00 0x254aa030 0x01 0x00 0x00 0x254aa034 0x01 0x00 0x00 0x254aa038 0x01 0x00 0x00 0x254aa040 0x01 0x00 0x00 0x254aa044 0x01 0x00 0x00 0x254aa048 0x01 0x00 0x00 0x254aa050 0x01 0x00 0x00 0x254aa054 0x01 0x00 0x00 0x254aa058 0x01 0x00 0x00 0x254b001c 0x01 0x00 0x00 0x254b101c 0x01 0x00 0x00 0x254b201c 0x01 0x00 0x00 0x254b301c 0x01 0x00 0x00 0x254b401c 0x01 0x00 0x00 0x254b501c 0x01 0x00 0x00 0x254b601c 0x01 0x00 0x00 0x254b701c 0x01 0x00 0x00 0x254b801c 0x01 0x00 0x00 0x254b901c 0x01 0x00 0x00 0x254ba01c 0x01 0x00 0x00 0x254bb01c 0x01 0x00 0x00 0x254bc01c 0x01 0x00 0x00 0x254bd01c 0x01 0x00 0x00 0x254be01c 0x01 0x00 0x00 0x254bf01c 0x01 0x00 0x00 0x252a9004 0x01 0x00 0x00 0x252a9010 0x01 0x00 0x00 0x252a9014 0x01 0x00 0x00 0x252a9018 0x01 0x00 0x00 0x252a9020 0x01 0x00 0x00 0x252a9024 0x01 0x00 0x00 0x252a9028 0x01 0x00 0x00 0x252a9030 0x01 0x00 0x00 0x252a9034 0x01 0x00 0x00 0x252a9038 0x01 0x00 0x00 0x252a9040 0x01 0x00 0x00 0x252a9044 0x01 0x00 0x00 0x252a9048 0x01 0x00 0x00 0x252a9050 0x01 0x00 0x00 0x252a9054 0x01 0x00 0x00 0x252a9058 0x01 0x00 0x00 0x252aa004 0x01 0x00 0x00 0x252aa010 0x01 0x00 0x00 0x252aa014 0x01 0x00 0x00 0x252aa018 0x01 0x00 0x00 0x252aa020 0x01 0x00 0x00 0x252aa024 0x01 0x00 0x00 0x252aa028 0x01 0x00 0x00 0x252aa030 0x01 0x00 0x00 0x252aa034 0x01 0x00 0x00 0x252aa038 0x01 0x00 0x00 0x252aa040 0x01 0x00 0x00 0x252aa044 0x01 0x00 0x00 0x252aa048 0x01 0x00 0x00 0x252aa050 0x01 0x00 0x00 0x252aa054 0x01 0x00 0x00 0x252aa058 0x01 0x00 0x00 0x252b001c 0x01 0x00 0x00 0x252b101c 0x01 0x00 0x00 0x252b201c 0x01 0x00 0x00 0x252b301c 0x01 0x00 0x00 0x252b401c 0x01 0x00 0x00 0x252b501c 0x01 0x00 0x00 0x252b601c 0x01 0x00 0x00 0x252b701c 0x01 0x00 0x00 0x252b801c 0x01 0x00 0x00 0x252b901c 0x01 0x00 0x00 0x252ba01c 0x01 0x00 0x00 0x252bb01c 0x01 0x00 0x00 0x252bc01c 0x01 0x00 0x00 0x252bd01c 0x01 0x00 0x00 0x252be01c 0x01 0x00 0x00 0x252bf01c 0x01 0x00 0x00 0x256a9004 0x01 0x00 0x00 0x256a9010 0x01 0x00 0x00 0x256a9014 0x01 0x00 0x00 0x256a9018 0x01 0x00 0x00 0x256a9020 0x01 0x00 0x00 0x256a9024 0x01 0x00 0x00 0x256a9028 0x01 0x00 0x00 0x256a9030 0x01 0x00 0x00 0x256a9034 0x01 0x00 0x00 0x256a9038 0x01 0x00 0x00 0x256a9040 0x01 0x00 0x00 0x256a9044 0x01 0x00 0x00 0x256a9048 0x01 0x00 0x00 0x256a9050 0x01 0x00 0x00 0x256a9054 0x01 0x00 0x00 0x256a9058 0x01 0x00 0x00 0x256aa004 0x01 0x00 0x00 0x256aa010 0x01 0x00 0x00 0x256aa014 0x01 0x00 0x00 0x256aa018 0x01 0x00 0x00 0x256aa020 0x01 0x00 0x00 0x256aa024 0x01 0x00 0x00 0x256aa028 0x01 0x00 0x00 0x256aa030 0x01 0x00 0x00 0x256aa034 0x01 0x00 0x00 0x256aa038 0x01 0x00 0x00 0x256aa040 0x01 0x00 0x00 0x256aa044 0x01 0x00 0x00 0x256aa048 0x01 0x00 0x00 0x256aa050 0x01 0x00 0x00 0x256aa054 0x01 0x00 0x00 0x256aa058 0x01 0x00 0x00 0x256b001c 0x01 0x00 0x00 0x256b101c 0x01 0x00 0x00 0x256b201c 0x01 0x00 0x00 0x256b301c 0x01 0x00 0x00 0x256b401c 0x01 0x00 0x00 0x256b501c 0x01 0x00 0x00 0x256b601c 0x01 0x00 0x00 0x256b701c 0x01 0x00 0x00 0x256b801c 0x01 0x00 0x00 0x256b901c 0x01 0x00 0x00 0x256ba01c 0x01 0x00 0x00 0x256bb01c 0x01 0x00 0x00 0x256bc01c 0x01 0x00 0x00 0x256bd01c 0x01 0x00 0x00 0x256be01c 0x01 0x00 0x00 0x256bf01c 0x01 0x00 0x00 0x32302028 0x01 0x00 0x00 0x320a4404 0x01 0x00 0x00 0x320a4408 0x01 0x00 0x00 0x323b0404 0x01 0x00 0x00 0x323b0408 0x01 0x00>; | |
| qcom,curr-link-list = <0x06>; | |
| }; | |
| link_list_1 { | |
| qcom,data-sink = "sram"; | |
| qcom,link-list = <0x00 0x240e0010 0x01 0x00 0x00 0x240e0020 0x08 0x00 0x00 0x240e0248 0x01 0x00 0x00 0x245f0010 0x01 0x00 0x00 0x245f0020 0x08 0x00 0x00 0x245f0248 0x01 0x00 0x00 0x247f0010 0x01 0x00 0x00 0x247f0020 0x08 0x00 0x00 0x247f0248 0x01 0x00 0x00 0x24330010 0x01 0x00 0x00 0x24330020 0x08 0x00 0x00 0x24330248 0x01 0x00 0x00 0x240e1018 0x01 0x00 0x00 0x240e1008 0x01 0x00 0x02 0x09 0x00 0x00 0x00 0x240e1010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x245f2018 0x01 0x00 0x00 0x245f2008 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x245f2010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x247f2018 0x01 0x00 0x00 0x247f2008 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x247f2010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x24331018 0x01 0x00 0x00 0x24331008 0x01 0x00 0x02 0x08 0x00 0x00 0x00 0x24331010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x6802028 0x01 0x00 0x00 0x68b0408 0x01 0x00 0x00 0x68b0404 0x01 0x00 0x00 0x7200408 0x01 0x00 0x00 0x7200404 0x01 0x00 0x00 0x1780010 0x01 0x00 0x00 0x1780020 0x08 0x00 0x00 0x1780248 0x01 0x00 0x00 0x1782018 0x01 0x00 0x00 0x1782008 0x01 0x00 0x02 0x0c 0x00 0x00 0x00 0x1782010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1783018 0x01 0x00 0x00 0x1783008 0x01 0x00 0x02 0x11 0x00 0x00 0x00 0x1783010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1680010 0x01 0x00 0x00 0x1680020 0x08 0x00 0x00 0x1681048 0x01 0x00 0x00 0x1682018 0x01 0x00 0x00 0x1682008 0x01 0x00 0x02 0x06 0x00 0x00 0x00 0x1682010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e0010 0x01 0x00 0x00 0x16e0020 0x08 0x00 0x00 0x16e0248 0x01 0x00 0x00 0x16e1018 0x01 0x00 0x00 0x16e1008 0x01 0x00 0x02 0x04 0x00 0x00 0x00 0x16e1010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e1098 0x01 0x00 0x00 0x16e1088 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x16e1090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e1118 0x01 0x00 0x00 0x16e1108 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x16e1110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1700010 0x01 0x00 0x00 0x1700020 0x08 0x00 0x00 0x1700248 0x01 0x00 0x00 0x1701018 0x01 0x00 0x00 0x1701008 0x01 0x00 0x02 0x04 0x00 0x00 0x00 0x1701010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1701098 0x01 0x00 0x00 0x1701088 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1701090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1701118 0x01 0x00 0x00 0x1701108 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1701110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1600010 0x01 0x00 0x00 0x1600020 0x08 0x00 0x00 0x1600248 0x02 0x00 0x00 0x1600258 0x01 0x00 0x00 0x1602018 0x01 0x00 0x00 0x1602008 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1602010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602098 0x01 0x00 0x00 0x1602088 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602118 0x01 0x00 0x00 0x1602108 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1602110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602198 0x01 0x00 0x00 0x1602188 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1602190 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602218 0x01 0x00 0x00 0x1602208 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602210 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602298 0x01 0x00 0x00 0x1602288 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602290 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1500010 0x01 0x00 0x00 0x1500020 0x08 0x00 0x00 0x1500248 0x01 0x00 0x00 0x1500448 0x01 0x00 0x00 0x1502018 0x01 0x00 0x00 0x1502008 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1502010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1502098 0x01 0x00 0x00 0x1502088 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1502090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x17100104 0x1d 0x00 0x00 0x17100204 0x1d 0x00 0x00 0x17100384 0x1d 0x00 0x00 0x178a0250 0x01 0x00 0x00 0x178a0254 0x01 0x00 0x00 0x178a025c 0x01 0x00 0x00 0xb281024 0x01 0x00 0x00 0xbde1034 0x01 0x00 0x00 0xb201020 0x02 0x00 0x00 0xb211020 0x02 0x00 0x00 0xb221020 0x02 0x00 0x00 0xb231020 0x02 0x00 0x00 0xb204520 0x01 0x00 0x00 0x17a00010 0x01 0x00 0x00 0x17a10010 0x01 0x00 0x00 0x17a20010 0x01 0x00 0x00 0x17a30010 0x01 0x00 0x00 0x17a00030 0x01 0x00 0x00 0x17a10030 0x01 0x00 0x00 0x17a20030 0x01 0x00 0x00 0x17a30030 0x01 0x00 0x00 0x17a00038 0x01 0x00 0x00 0x17a10038 0x01 0x00 0x00 0x17a20038 0x01 0x00 0x00 0x17a30038 0x01 0x00 0x00 0x17a00040 0x01 0x00 0x00 0x17a10040 0x01 0x00 0x00 0x17a20040 0x01 0x00 0x00 0x17a30040 0x01 0x00 0x00 0x17a00048 0x01 0x00 0x00 0x17a00400 0x03 0x00 0x00 0x17a10400 0x03 0x00 0x00 0x17a20400 0x03 0x00 0x00 0x17a30400 0x03 0x00 0x00 0xc230000 0x06 0x00 0x00 0x17d10200 0x100 0x00 0x00 0x17120000 0x01 0x00 0x00 0x17120008 0x01 0x00 0x00 0x17120010 0x01 0x00 0x00 0x17120018 0x01 0x00 0x00 0x17120020 0x01 0x00 0x00 0x17120028 0x01 0x00 0x00 0x17120040 0x01 0x00 0x00 0x17120048 0x01 0x00 0x00 0x17120050 0x01 0x00 0x00 0x17120058 0x01 0x00 0x00 0x17120060 0x01 0x00 0x00 0x17120068 0x01 0x00 0x00 0x17120080 0x01 0x00 0x00 0x17120088 0x01 0x00 0x00 0x17120090 0x01 0x00 0x00 0x17120098 0x01 0x00 0x00 0x171200a0 0x01 0x00 0x00 0x171200a8 0x01 0x00 0x00 0x171200c0 0x01 0x00 0x00 0x171200c8 0x01 0x00 0x00 0x171200d0 0x01 0x00 0x00 0x171200d8 0x01 0x00 0x00 0x171200e0 0x01 0x00 0x00 0x171200e8 0x01 0x00 0x00 0x17120100 0x01 0x00 0x00 0x17120108 0x01 0x00 0x00 0x17120110 0x01 0x00 0x00 0x17120118 0x01 0x00 0x00 0x17120120 0x01 0x00 0x00 0x17120128 0x01 0x00 0x00 0x17120140 0x01 0x00 0x00 0x17120148 0x01 0x00 0x00 0x17120150 0x01 0x00 0x00 0x17120158 0x01 0x00 0x00 0x17120160 0x01 0x00 0x00 0x17120168 0x01 0x00 0x00 0x17120180 0x01 0x00 0x00 0x17120188 0x01 0x00 0x00 0x17120190 0x01 0x00 0x00 0x17120198 0x01 0x00 0x00 0x171201a0 0x01 0x00 0x00 0x171201a8 0x01 0x00 0x00 0x171201c0 0x01 0x00 0x00 0x171201c8 0x01 0x00 0x00 0x171201d0 0x01 0x00 0x00 0x171201d8 0x01 0x00 0x00 0x171201e0 0x01 0x00 0x00 0x171201e8 0x01 0x00 0x00 0x17120200 0x01 0x00 0x00 0x17120208 0x01 0x00 0x00 0x17120210 0x01 0x00 0x00 0x17120218 0x01 0x00 0x00 0x17120220 0x01 0x00 0x00 0x17120228 0x01 0x00 0x00 0x17120240 0x01 0x00 0x00 0x17120248 0x01 0x00 0x00 0x17120250 0x01 0x00 0x00 0x17120258 0x01 0x00 0x00 0x17120260 0x01 0x00 0x00 0x17120268 0x01 0x00 0x00 0x17120280 0x01 0x00 0x00 0x17120288 0x01 0x00 0x00 0x17120290 0x01 0x00 0x00 0x17120298 0x01 0x00 0x00 0x171202a0 0x01 0x00 0x00 0x171202a8 0x01 0x00 0x00 0x171202c0 0x01 0x00 0x00 0x171202c8 0x01 0x00 0x00 0x171202d0 0x01 0x00 0x00 0x171202d8 0x01 0x00 0x00 0x171202e0 0x01 0x00 0x00 0x171202e8 0x01 0x00 0x00 0x17120300 0x01 0x00 0x00 0x17120308 0x01 0x00 0x00 0x17120310 0x01 0x00 0x00 0x17120318 0x01 0x00 0x00 0x17120320 0x01 0x00 0x00 0x17120328 0x01 0x00 0x00 0x17120340 0x01 0x00 0x00 0x17120348 0x01 0x00 0x00 0x17120350 0x01 0x00 0x00 0x17120358 0x01 0x00 0x00 0x17120360 0x01 0x00 0x00 0x17120368 0x01 0x00 0x00 0x17120380 0x01 0x00 0x00 0x17120388 0x01 0x00 0x00 0x17120390 0x01 0x00 0x00 0x17120398 0x01 0x00 0x00 0x171203a0 0x01 0x00 0x00 0x171203a8 0x01 0x00 0x00 0x171203c0 0x01 0x00 0x00 0x171203c8 0x01 0x00 0x00 0x171203d0 0x01 0x00 0x00 0x171203d8 0x01 0x00 0x00 0x171203e0 0x01 0x00 0x00 0x171203e8 0x01 0x00 0x00 0x17120400 0x01 0x00 0x00 0x17120408 0x01 0x00 0x00 0x17120410 0x01 0x00 0x00 0x17120418 0x01 0x00 0x00 0x17120420 0x01 0x00 0x00 0x17120428 0x01 0x00 0x00 0x17120440 0x01 0x00 0x00 0x17120448 0x01 0x00 0x00 0x17120450 0x01 0x00 0x00 0x17120458 0x01 0x00 0x00 0x17120460 0x01 0x00 0x00 0x17120468 0x01 0x00 0x00 0x17120480 0x01 0x00 0x00 0x17120488 0x01 0x00 0x00 0x17120490 0x01 0x00 0x00 0x17120498 0x01 0x00 0x00 0x171204a0 0x01 0x00 0x00 0x171204a8 0x01 0x00 0x00 0x171204c0 0x01 0x00 0x00 0x171204c8 0x01 0x00 0x00 0x171204d0 0x01 0x00 0x00 0x171204d8 0x01 0x00 0x00 0x171204e0 0x01 0x00 0x00 0x171204e8 0x01 0x00 0x00 0x17120500 0x01 0x00 0x00 0x17120508 0x01 0x00 0x00 0x17120510 0x01 0x00 0x00 0x17120518 0x01 0x00 0x00 0x17120520 0x01 0x00 0x00 0x17120528 0x01 0x00 0x00 0x17120540 0x01 0x00 0x00 0x17120548 0x01 0x00 0x00 0x17120550 0x01 0x00 0x00 0x17120558 0x01 0x00 0x00 0x17120560 0x01 0x00 0x00 0x17120568 0x01 0x00 0x00 0x17120580 0x01 0x00 0x00 0x17120588 0x01 0x00 0x00 0x17120590 0x01 0x00 0x00 0x17120598 0x01 0x00 0x00 0x171205a0 0x01 0x00 0x00 0x171205a8 0x01 0x00 0x00 0x171205c0 0x01 0x00 0x00 0x171205c8 0x01 0x00 0x00 0x171205d0 0x01 0x00 0x00 0x171205d8 0x01 0x00 0x00 0x171205e0 0x01 0x00 0x00 0x171205e8 0x01 0x00 0x00 0x17120600 0x01 0x00 0x00 0x17120608 0x01 0x00 0x00 0x17120610 0x01 0x00 0x00 0x17120618 0x01 0x00 0x00 0x17120620 0x01 0x00 0x00 0x17120628 0x01 0x00 0x00 0x17120640 0x01 0x00 0x00 0x17120648 0x01 0x00 0x00 0x17120650 0x01 0x00 0x00 0x17120658 0x01 0x00 0x00 0x17120660 0x01 0x00 0x00 0x17120668 0x01 0x00 0x00 0x17120680 0x01 0x00 0x00 0x17120688 0x01 0x00 0x00 0x17120690 0x01 0x00 0x00 0x17120698 0x01 0x00 0x00 0x171206a0 0x01 0x00 0x00 0x171206a8 0x01 0x00 0x00 0x171206c0 0x01 0x00 0x00 0x171206c8 0x01 0x00 0x00 0x171206d0 0x01 0x00 0x00 0x171206d8 0x01 0x00 0x00 0x171206e0 0x01 0x00 0x00 0x171206e8 0x01 0x00 0x00 0x1712e000 0x01 0x00 0x00 0x110004 0x01 0x00 0x00 0x110008 0x01 0x00 0x00 0x11003c 0x01 0x00 0x00 0x110040 0x01 0x00 0x00 0x110044 0x01 0x00 0x00 0x11015c 0x01 0x00 0x00 0x110160 0x01 0x00 0x00 0x110464 0x01 0x00 0x00 0x110468 0x01 0x00 0x00 0x176040 0x01 0x00>; | |
| qcom,curr-link-list = <0x04>; | |
| }; | |
| }; | |
| qcom,gdsc@19e000 { | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2a>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x00>; | |
| regulator-name = "gcc_ufs_mem_phy_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x19e000 0x04>; | |
| phandle = <0x504>; | |
| }; | |
| cti@10d31000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-ddr_ch13_dl_cti_0"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x10d31000 0x1000>; | |
| phandle = <0x463>; | |
| }; | |
| qcom,chd { | |
| label = "core"; | |
| qcom,chd-percpu-info = <0x18 0x17800058 0x17800060 0x19 0x17810058 0x17810060 0x1a 0x17820058 0x17820060 0x1b 0x17830058 0x17830060 0x1c 0x17840058 0x17840060 0x1d 0x17850058 0x17850060 0x1e 0x17860058 0x17860060 0x1f 0x17870058 0x17870060>; | |
| compatible = "qcom,core-hang-detect"; | |
| }; | |
| funnel@10c0a000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-multimedia"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10c0a000 0x1000>; | |
| phandle = <0x437>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x13f>; | |
| phandle = <0x13e>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x141>; | |
| phandle = <0xfd>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x140>; | |
| phandle = <0xfc>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x142>; | |
| phandle = <0x167>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,csid-lite1@acce000 { | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; | |
| reg-names = "csid-lite"; | |
| reg-cam-base = <0xce000>; | |
| cell-index = <0x04>; | |
| interrupts = <0x00 0x178 0x01>; | |
| clocks = <0x3b 0x50 0x3b 0x55 0x3b 0x54 0x3b 0x53 0x3b 0x51 0x3b 0x16>; | |
| rt-wrapper-base = <0xca000>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| compatible = "qcom,csid-lite780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "ife_lite_csid_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "csid-lite1"; | |
| reg = <0xacce000 0xa00>; | |
| regulator-names = "gdsc"; | |
| phandle = <0x5c2>; | |
| shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; | |
| clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; | |
| }; | |
| cti@1098b000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-turing_q6_cti"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x1098b000 0x1000>; | |
| phandle = <0x46b>; | |
| }; | |
| tgu@10b0e000 { | |
| arm,primecell-periphid = <0xbb999>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tgu-base"; | |
| clocks = <0x4e>; | |
| tgu-regs = <0x04>; | |
| tgu-steps = <0x03>; | |
| coresight-name = "coresight-tgu-ipcb"; | |
| tgu-conditions = <0x04>; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b0e000 0x1000>; | |
| phandle = <0x48e>; | |
| tgu-timer-counters = <0x08>; | |
| }; | |
| funnel@10cc5000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-tmess"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10cc5000 0x1000>; | |
| phandle = <0x445>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x17e>; | |
| phandle = <0x17d>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x17f>; | |
| phandle = <0x185>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| pcie_1_pipe_clk { | |
| clock-output-names = "pcie_1_pipe_clk"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x57>; | |
| }; | |
| qcom,cam-cdm-intf { | |
| cdm-client-names = "vfe", "jpegdma", "jpegenc"; | |
| num-hw-cdm = <0x01>; | |
| cell-index = <0x00>; | |
| label = "cam-cdm-intf"; | |
| compatible = "qcom,cam-cdm-intf"; | |
| status = "ok"; | |
| }; | |
| cti@12050000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-cpu4"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x12050000 0x1000>; | |
| phandle = <0x48a>; | |
| trig-conns { | |
| arm,trig-out-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| cpu = <0x1c>; | |
| arm,trig-in-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| }; | |
| }; | |
| interconnect@7400000 { | |
| #interconnect-cells = <0x01>; | |
| qcom,bcm-voters = <0x40>; | |
| compatible = "qcom,kalama-lpass_lpiaon_noc"; | |
| reg = <0x7400000 0x19080>; | |
| phandle = <0x357>; | |
| qcom,bcm-voter-names = "hlos"; | |
| }; | |
| qcom,mdss_dsi_ctrl1@ae96000 { | |
| clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; | |
| reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; | |
| cell-index = <0x01>; | |
| interrupts = <0x05 0x00>; | |
| clocks = <0x3c 0x08 0x3c 0x09 0x3c 0x0b 0x3c 0x44 0x3c 0x45 0x3c 0x3a 0x46 0x00>; | |
| interrupt-parent = <0x752>; | |
| label = "dsi-ctrl-1"; | |
| vdda-1p2-supply = <0x31>; | |
| compatible = "qcom,dsi-ctrl-hw-v2.7"; | |
| frame-threshold-time-us = <0x320>; | |
| reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; | |
| phandle = <0x757>; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x41a0>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| }; | |
| }; | |
| }; | |
| qcom,ife-lite1@acce000 { | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; | |
| reg-names = "ife-lite"; | |
| reg-cam-base = <0xce000>; | |
| cell-index = <0x04>; | |
| interrupts = <0x00 0x179 0x01>; | |
| clocks = <0x3b 0x50 0x3b 0x54 0x3b 0x53 0x3b 0x52 0x3b 0x51 0x3b 0x16>; | |
| rt-wrapper-base = <0xca000>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| cam_hw_pid = <0x1c>; | |
| compatible = "qcom,vfe-lite780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "ife_lite_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "ife-lite1"; | |
| reg = <0xacce000 0x2800>; | |
| regulator-names = "gdsc"; | |
| phandle = <0x5c3>; | |
| shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; | |
| clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; | |
| }; | |
| tpda@109c1000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x01 0x20 0x02 0x20>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpda-dl_south"; | |
| qcom,dsb-elem-size = <0x04 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x4b>; | |
| reg = <0x109c1000 0x1000>; | |
| phandle = <0x442>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x174>; | |
| phandle = <0x121>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x176>; | |
| phandle = <0x114>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x175>; | |
| phandle = <0x10f>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x177>; | |
| phandle = <0x178>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| syscon@152020 { | |
| compatible = "syscon"; | |
| reg = <0x152020 0x04>; | |
| phandle = <0x2db>; | |
| }; | |
| snoc { | |
| atid = <0x7d>; | |
| qcom,dummy-source; | |
| coresight-name = "coresight-snoc"; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x414>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10b>; | |
| phandle = <0x1b9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,ife2@ac80000 { | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; | |
| clocks-option = <0x3b 0x4d>; | |
| reg-names = "ife", "cam_camnoc"; | |
| clock-rates-option = <0x2367b880>; | |
| reg-cam-base = <0x80000 0x19000>; | |
| cell-index = <0x02>; | |
| interrupts = <0x00 0x2b0 0x01>; | |
| clocks = <0x3b 0x4f 0x3b 0x4c 0x3b 0x4b 0x3b 0x15>; | |
| ife2-supply = <0x4fd>; | |
| rt-wrapper-base = <0x62000>; | |
| ubwc-static-cfg = <0x1026 0x1036>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| cam_hw_pid = <0x12 0x16 0x1a 0x0a>; | |
| compatible = "qcom,vfe780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "ife_2_clk_src"; | |
| status = "ok"; | |
| clock-names-option = "ife_dsp_clk"; | |
| interrupt-names = "ife2"; | |
| reg = <0xac80000 0xf000 0xac19000 0xa080>; | |
| regulator-names = "gdsc", "ife2"; | |
| phandle = <0x5bf>; | |
| clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; | |
| }; | |
| vote_lpass_core_hw { | |
| qcom,codec-ext-clk-src = <0x09>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x517>; | |
| }; | |
| qcom,gdsc@139004 { | |
| qcom,gds-timeout = <0x5dc>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x00>; | |
| regulator-name = "gcc_usb30_prim_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| qcom,proxy-consumer-enable; | |
| reg = <0x139004 0x04>; | |
| phandle = <0x2b3>; | |
| proxy-supply = <0x2b3>; | |
| }; | |
| qcom,cam_smmu { | |
| force_cache_allocs; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| need_shared_buffer_padding; | |
| compatible = "qcom,msm-cam-smmu", "simple-bus"; | |
| status = "ok"; | |
| expanded_memory; | |
| msm_cam_smmu_ife { | |
| iommus = <0x4c 0x800 0x20>; | |
| dma-coherent; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| multiple-client-devices; | |
| qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; | |
| cam-smmu-label = "ife", "sfe"; | |
| qcom,iommu-faults = "stall-disable", "non-fatal"; | |
| iova-mem-map { | |
| phandle = <0x589>; | |
| iova-mem-region-io { | |
| iova-region-len = <0x0f 0xffe00000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = <0x00 0x100000>; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_icp { | |
| iommus = <0x4c 0x1800 0xc0 0x4c 0x1820 0x00>; | |
| dma-coherent; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| qcom,iommu-dma-addr-pool = <0x00 0xf8c00000 0x0f 0x7300000>; | |
| cam-smmu-label = "icp"; | |
| qcom,iommu-faults = "stall-disable", "non-fatal"; | |
| iova-mem-map { | |
| phandle = <0x58b>; | |
| iova-mem-qdss-region { | |
| iova-region-len = <0x00 0x100000>; | |
| qdss-phy-addr = <0x16790000>; | |
| iova-region-name = "qdss"; | |
| status = "ok"; | |
| iova-region-id = <0x05>; | |
| iova-region-start = <0x00 0xc0700000>; | |
| }; | |
| iova-mem-region-io { | |
| iova-region-len = <0x0f 0x7300000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = <0x00 0xf8c00000>; | |
| }; | |
| iova-mem-region-fwuncached-region { | |
| iova-region-len = <0x00 0x700000>; | |
| iova-region-name = "fw_uncached"; | |
| status = "ok"; | |
| iova-region-id = <0x06>; | |
| iova-region-start = <0x00 0xc0000000>; | |
| }; | |
| iova-mem-region-shared { | |
| iova-region-len = <0x00 0x38400000>; | |
| iova-region-name = "shared"; | |
| status = "ok"; | |
| iova-region-id = <0x01>; | |
| iova-region-start = <0x00 0xc0800000>; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_jpeg { | |
| iommus = <0x4c 0x18a0 0x00>; | |
| dma-coherent; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; | |
| cam-smmu-label = "jpeg"; | |
| qcom,iommu-faults = "stall-disable", "non-fatal"; | |
| iova-mem-map { | |
| phandle = <0x58a>; | |
| iova-mem-region-io { | |
| iova-region-len = <0x00 0xffe00000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = <0x00 0x100000>; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_cdm { | |
| iommus = <0x4c 0x1860 0x00>; | |
| dma-coherent; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| multiple-client-devices; | |
| qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; | |
| cam-smmu-label = "rt-cdm"; | |
| qcom,iommu-faults = "stall-disable", "non-fatal"; | |
| iova-mem-map { | |
| phandle = <0x58c>; | |
| iova-mem-region-io { | |
| iova-region-len = <0x00 0xffe00000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = <0x00 0x100000>; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_secure { | |
| qcom,secure-cb; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| cam-smmu-label = "cam-secure"; | |
| }; | |
| }; | |
| qcom,gpi-dma@800000 { | |
| iommus = <0x4c 0x436 0x00>; | |
| qcom,gpi-ee-offset = <0x10000>; | |
| qcom,gpii-mask = <0x3e>; | |
| dma-coherent; | |
| qcom,static-gpii-mask = <0x01>; | |
| reg-names = "gpi-top"; | |
| interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04 0x00 0x24e 0x04 0x00 0x24f 0x04 0x00 0x250 0x04 0x00 0x251 0x04 0x00 0x252 0x04 0x00 0x253 0x04 0x00 0x254 0x04 0x00 0x255 0x04 0x00 0x256 0x04 0x00 0x257 0x04>; | |
| qcom,ev-factor = <0x02>; | |
| compatible = "qcom,gpi-dma"; | |
| status = "ok"; | |
| qcom,iommu-dma-addr-pool = <0x100000 0x100000>; | |
| qcom,max-num-gpii = <0x0c>; | |
| reg = <0x800000 0x60000>; | |
| phandle = <0x24c>; | |
| #dma-cells = <0x05>; | |
| }; | |
| ipcc-self-ping-adsp { | |
| interrupts-extended = <0x4f 0x03 0x03 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x3fa>; | |
| mboxes = <0x4f 0x03 0x03>; | |
| }; | |
| qcom,smmu_sde_unsec_cb { | |
| iommus = <0x4c 0x1c00 0x02>; | |
| dma-coherent; | |
| compatible = "qcom,smmu_sde_unsec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x74a>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-earlymap; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_5_out { | |
| qcom,smem-state-names = "rdbg-smp2p-out"; | |
| compatible = "qcom,smp2p-interrupt-rdbg-5-out"; | |
| qcom,smem-states = <0x2d4 0x00>; | |
| }; | |
| qcom,gdsc@add5004 { | |
| qcom,retain-regs; | |
| regulator-name = "cam_cc_camss_top_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "disabled"; | |
| reg = <0xadd5004 0x04>; | |
| phandle = <0x4f9>; | |
| }; | |
| qcom,devfreq-cdev { | |
| qcom,devfreq = <0xde>; | |
| compatible = "qcom,devfreq-cdev"; | |
| }; | |
| interconnect@1600000 { | |
| #interconnect-cells = <0x01>; | |
| qcom,bcm-voters = <0x40>; | |
| compatible = "qcom,kalama-cnoc_cfg"; | |
| reg = <0x1600000 0x6200>; | |
| phandle = <0x62>; | |
| qcom,bcm-voter-names = "hlos"; | |
| }; | |
| tpdm@10b0b000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-swao-prio-2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b0b000 0x1000>; | |
| phandle = <0x409>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf4>; | |
| phandle = <0x1c8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,ipcc@408000 { | |
| interrupts = <0x00 0xe5 0x04>; | |
| #mbox-cells = <0x02>; | |
| compatible = "qcom,ipcc"; | |
| #interrupt-cells = <0x03>; | |
| reg = <0x408000 0x1000>; | |
| phandle = <0x4f>; | |
| interrupt-controller; | |
| }; | |
| tmc@10048000 { | |
| iommus = <0x4c 0x4c0 0x20>; | |
| arm,primecell-periphid = <0xbb961>; | |
| dma-coherent; | |
| arm,scatter-gather; | |
| csr-irqctrl-offset = <0x6c>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tmc-base", "bam-base"; | |
| qcom,sw-usb; | |
| csr-atid-offset = <0xf8>; | |
| byte-cntr-class-name = "coresight-tmc-etr-stream"; | |
| interrupts = <0x00 0x10e 0x01>; | |
| clocks = <0x4e>; | |
| byte-cntr-name = "byte-cntr"; | |
| coresight-name = "coresight-tmc-etr"; | |
| compatible = "arm,primecell"; | |
| interrupt-names = "byte-cntr-irq"; | |
| qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; | |
| reg = <0x10048000 0x1000 0x10064000 0x16000>; | |
| phandle = <0x45b>; | |
| coresight-csr = <0x1dc>; | |
| qcom,mem_support; | |
| qcom,iommu-dma = "bypass"; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1dd>; | |
| phandle = <0x1da>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@16b004 { | |
| qcom,collapse-vote = <0x2db 0x00>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x27>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x00>; | |
| regulator-name = "gcc_pcie_0_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x16b004 0x04>; | |
| phandle = <0x2c2>; | |
| }; | |
| ete0 { | |
| atid = <0x01>; | |
| qcom,skip-power-up; | |
| cpu = <0x18>; | |
| coresight-name = "coresight-ete0"; | |
| phy-cpu = <0x00>; | |
| compatible = "arm,embedded-trace-extension"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1e0>; | |
| phandle = <0x1e9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_pll_codes { | |
| label = "dsi_pll_codes"; | |
| reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x753>; | |
| }; | |
| cti@10b21000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-ddr_dl2_lpi"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10b21000 0x1000>; | |
| phandle = <0x46d>; | |
| }; | |
| funnel@10963000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-gfx"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10963000 0x1000>; | |
| phandle = <0x434>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x5d5>; | |
| phandle = <0x5d4>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x5d6>; | |
| phandle = <0x5d3>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x137>; | |
| phandle = <0x139>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tsens0@c271000 { | |
| #qcom,sensors = <0x10>; | |
| interrupts = <0x00 0x1fa 0x04 0x00 0x280 0x04>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,tsens-v2"; | |
| interrupt-names = "uplow", "critical"; | |
| reg = <0xc271000 0x1ff 0xc222000 0x1ff>; | |
| phandle = <0xa0>; | |
| }; | |
| qcom,guestvm_loader@f3c00000 { | |
| qcom,unisolate-timeout-ms = <0x2ee0>; | |
| memory-region = <0x84>; | |
| qcom,pas-id = <0x1c>; | |
| compatible = "qcom,guestvm-loader"; | |
| qcom,vmid = <0x2d>; | |
| qcom,isolate-cpus; | |
| qcom,reserved-cpus = <0x05 0x06>; | |
| qcom,firmware-name = "trustedvm"; | |
| }; | |
| tlmm-vm-test { | |
| qcom,master; | |
| tlmm-vm-gpio-list = <0x33 0x56 0x00 0x33 0x57 0x00 0x33 0x85 0x00 0x33 0x89 0x00 0x33 0x2c 0x00 0x33 0x2d 0x00 0x33 0x2e 0x00 0x33 0x2f 0x00 0x33 0x18 0x00 0x33 0x19 0x00 0x33 0x5b 0x00 0x33 0x38 0x00 0x33 0x39 0x00 0x33 0x3a 0x00 0x33 0x3b 0x00 0x33 0x0d 0x00 0x33 0x30 0x00>; | |
| compatible = "qcom,tlmm-vm-test"; | |
| }; | |
| qcom,pmic_glink_log { | |
| qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; | |
| compatible = "qcom,pmic-glink"; | |
| qcom,charger_ulog_glink { | |
| compatible = "qcom,charger-ulog-glink"; | |
| }; | |
| qcom,battery_debug { | |
| compatible = "qcom,battery-debug"; | |
| }; | |
| qcom,spmi_glink_debug { | |
| #address-cells = <0x01>; | |
| depends-on-supply = <0xe7>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-glink-debug"; | |
| spmi@0 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| qcom,pm8550b-debug@7 { | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x07 0x00>; | |
| }; | |
| }; | |
| spmi@1 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x01>; | |
| qcom,smb1394-debug@9 { | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x09 0x00>; | |
| phandle = <0xe8>; | |
| }; | |
| qcom,smb1394-debug@b { | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0b 0x00>; | |
| }; | |
| qcom,smb1398-debug@d { | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0d 0x00>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@af09000 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x28>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x0f>; | |
| regulator-name = "disp_cc_mdss_core_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| qcom,proxy-consumer-enable; | |
| reg = <0xaf09000 0x04>; | |
| phandle = <0x2da>; | |
| proxy-supply = <0x2da>; | |
| }; | |
| qcom,cci2@ac17000 { | |
| pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; | |
| pinctrl-2 = <0x540 0x541>; | |
| pctrl-idx-mapping = <0x00 0x01>; | |
| pinctrl-0 = <0x53c 0x53d>; | |
| clock-names = "cci_2_clk_src", "cci_2_clk"; | |
| reg-names = "cci"; | |
| reg-cam-base = <0x17000>; | |
| cell-index = <0x02>; | |
| interrupts = <0x00 0x1ac 0x01>; | |
| clocks = <0x3b 0x0d 0x3b 0x0c>; | |
| gdscr-supply = <0x2d9>; | |
| pctrl-map-names = "m0", "m1"; | |
| clock-cntl-level = "lowsvs"; | |
| pinctrl-3 = <0x542 0x543>; | |
| compatible = "qcom,cci", "simple-bus"; | |
| src-clock-name = "cci_2_clk_src"; | |
| pinctrl-1 = <0x53e 0x53f>; | |
| status = "ok"; | |
| interrupt-names = "CCI2"; | |
| reg = <0xac17000 0x1000>; | |
| regulator-names = "gdscr"; | |
| phandle = <0x584>; | |
| clock-rates = <0x23c3460 0x00>; | |
| qcom,i2c_custom_mode { | |
| hw-tsu-sto = <0x11>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x03>; | |
| hw-thigh = <0x10>; | |
| hw-tlow = <0x16>; | |
| status = "ok"; | |
| hw-thd-dat = <0x10>; | |
| hw-tsu-sta = <0x12>; | |
| hw-scl-stretch-en = <0x01>; | |
| phandle = <0x587>; | |
| hw-tbuf = <0x18>; | |
| hw-thd-sta = <0x0f>; | |
| }; | |
| qcom,cam-sensor4 { | |
| rgltr-max-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x55e 0x56c>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x04>; | |
| gpio-req-tbl-num = <0x00 0x01 0x02>; | |
| sensor-position-yaw = <0x00>; | |
| clocks = <0x3b 0x67>; | |
| rgltr-load-current = <0x1770 0x6ed70 0x00 0x1304c 0x19258>; | |
| actuator-src = <0x73e>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x334>; | |
| gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4", "CAM_STANDBY"; | |
| cam_vaf-supply = <0x33e>; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x04>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x339>; | |
| gpio-standby = <0x02>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80>; | |
| sensor-position-roll = <0x5a>; | |
| pinctrl-1 = <0x55f 0x56d>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00 0x00>; | |
| gpios = <0x33 0x68 0x00 0x33 0x78 0x00 0x33 0x06 0x00>; | |
| }; | |
| qcom,i2c_standard_mode { | |
| hw-tsu-sto = <0xcc>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0xc9>; | |
| hw-tlow = <0xae>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0xe7>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x585>; | |
| hw-tbuf = <0xe3>; | |
| hw-thd-sta = <0xa2>; | |
| }; | |
| qcom,cam-sensor5 { | |
| rgltr-max-voltage = <0x1b7740 0x00 0x2ab980>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x562 0x56e>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x05>; | |
| gpio-req-tbl-num = <0x00 0x01 0x02>; | |
| sensor-position-yaw = <0xb4>; | |
| clocks = <0x3b 0x6d>; | |
| rgltr-load-current = <0x25d78 0x00 0x1304c>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x337>; | |
| gpio-req-tbl-label = "CAMIF_MCLK7", "CAM_RESET5", "CAM_STANDBY"; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x05>; | |
| clock-cntl-level = "nominal"; | |
| gpio-standby = <0x02>; | |
| cci-master = <0x01>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x00 0x2ab980>; | |
| sensor-position-roll = <0x5a>; | |
| pinctrl-1 = <0x563 0x56f>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_clk", "cam_vana"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00 0x00>; | |
| gpios = <0x33 0x6b 0x00 0x33 0x6d 0x00 0x33 0x46 0x00>; | |
| }; | |
| qcom,i2c_fast_plus_mode { | |
| hw-tsu-sto = <0x11>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x03>; | |
| hw-thigh = <0x10>; | |
| hw-tlow = <0x16>; | |
| status = "ok"; | |
| hw-thd-dat = <0x10>; | |
| hw-tsu-sta = <0x12>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x588>; | |
| hw-tbuf = <0x18>; | |
| hw-thd-sta = <0x0f>; | |
| }; | |
| qcom,i2c_fast_mode { | |
| hw-tsu-sto = <0x28>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0x26>; | |
| hw-tlow = <0x38>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0x28>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x586>; | |
| hw-tbuf = <0x3e>; | |
| hw-thd-sta = <0x23>; | |
| }; | |
| qcom,eeprom5 { | |
| cam_v_custom1-supply = <0x33d>; | |
| rgltr-max-voltage = <0x1b7740 0x14a140 0x00 0x2ab980 0x326a40 0x36ee80>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| cam_v_custom2-supply = <0x65c>; | |
| pinctrl-0 = <0x560 0x56e>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x05>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| clocks = <0x3b 0x69>; | |
| rgltr-load-current = <0x25d78 0xa6040 0x00 0xc350 0x7530 0x2625a0>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x33a>; | |
| gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x31f>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x124f80 0x00 0x2ab980 0x326a40 0x36ee80>; | |
| pinctrl-1 = <0x561 0x56f>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; | |
| phandle = <0x747>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x33 0x69 0x00 0x33 0x45 0x00>; | |
| }; | |
| qcom,actuator3 { | |
| rgltr-max-voltage = <0x2d2a80>; | |
| cell-index = <0x03>; | |
| rgltr-load-current = <0x19258>; | |
| rgltr-cntrl-support; | |
| cam_vaf-supply = <0x33e>; | |
| cci-master = <0x00>; | |
| compatible = "qcom,actuator"; | |
| rgltr-min-voltage = <0x2d2a80>; | |
| status = "disabled"; | |
| regulator-names = "cam_vaf"; | |
| phandle = <0x73e>; | |
| }; | |
| }; | |
| dload_mode { | |
| compatible = "qcom,dload-mode"; | |
| }; | |
| tpdm@10d20000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-ddr-ch02"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10d20000 0x1000>; | |
| phandle = <0x153>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf7>; | |
| phandle = <0x145>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| syscon@240ba000 { | |
| compatible = "syscon"; | |
| reg = <0x240ba000 0x54>; | |
| phandle = <0x60>; | |
| }; | |
| funnel@109c2000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-dl_south"; | |
| compatible = "arm,primecell"; | |
| reg = <0x109c2000 0x1000>; | |
| phandle = <0x443>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x178>; | |
| phandle = <0x177>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x179>; | |
| phandle = <0x1bd>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,rt-cdm3@ac28000 { | |
| clock-names = "cam_cc_cpas_ahb_clk"; | |
| reg-names = "rt-cdm3"; | |
| fifo-depths = <0x40 0x00 0x00 0x00>; | |
| reg-cam-base = <0x28000>; | |
| cdm-client-names = "ife3"; | |
| cell-index = <0x03>; | |
| interrupts = <0x00 0x15c 0x01>; | |
| clocks = <0x3b 0x0f>; | |
| label = "rt-cdm"; | |
| clock-cntl-level = "turbo"; | |
| cam_hw_pid = <0x18>; | |
| compatible = "qcom,cam-rt-cdm2_1"; | |
| gdsc-supply = <0x2d9>; | |
| status = "ok"; | |
| interrupt-names = "rt-cdm3"; | |
| reg = <0xac28000 0x400>; | |
| regulator-names = "gdsc"; | |
| cam-hw-mid = <0x00>; | |
| nrt-device; | |
| single-context-cdm; | |
| clock-rates = <0x00>; | |
| config-fifo; | |
| }; | |
| display_gpio_regulator@0 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| pinctrl-names = "default"; | |
| regulator-boot-on; | |
| gpio = <0x33 0x46 0x00>; | |
| pinctrl-0 = <0x767>; | |
| regulator-enable-ramp-delay = <0x64>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "display_panel_vddio_1v8"; | |
| compatible = "qti-regulator-fixed"; | |
| qcom,proxy-consumer-enable; | |
| phandle = <0x75f>; | |
| proxy-supply = <0x75f>; | |
| }; | |
| bamdma@6C04000 { | |
| qcom,num-ees = <0x02>; | |
| reg-names = "bam", "bam_remote_mem"; | |
| interrupts = <0x00 0xa4 0x04>; | |
| num-channels = <0x1f>; | |
| qcom,controlled-remotely; | |
| compatible = "qcom,bam-v1.7.0"; | |
| reg = <0x6c04000 0x20000 0x6c8b000 0x1000>; | |
| phandle = <0x26>; | |
| qcom,ee = <0x01>; | |
| #dma-cells = <0x01>; | |
| }; | |
| qcom,gdsc@adf03b8 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x06>; | |
| regulator-name = "cam_cc_ipe_0_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xadf03b8 0x04>; | |
| phandle = <0x4fe>; | |
| }; | |
| qcom,bwmon-ddr@24091000 { | |
| reg-names = "base"; | |
| interrupts = <0x00 0x51 0x04>; | |
| compatible = "qcom,bwmon5"; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,count-unit = <0x10000>; | |
| reg = <0x24091000 0x1000>; | |
| phandle = <0x3f1>; | |
| qcom,target-dev = <0x96>; | |
| }; | |
| interconnect@24100000 { | |
| #interconnect-cells = <0x01>; | |
| qcom,bcm-voters = <0x40 0x41 0x42 0x43 0x44>; | |
| compatible = "qcom,kalama-gem_noc"; | |
| reg = <0x24100000 0xbb800>; | |
| phandle = <0x61>; | |
| qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2"; | |
| }; | |
| qcom,csiphy5@acee000 { | |
| csi-vdd-1p2-supply = <0x31>; | |
| rgltr-max-voltage = <0x00 0x124f80 0xe7ef0>; | |
| csi-vdd-0p9-supply = <0x30>; | |
| clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0xee000>; | |
| cell-index = <0x05>; | |
| interrupts = <0x00 0x59 0x01>; | |
| clocks = <0x3b 0x1b 0x3b 0x37 0x3b 0x2a 0x3b 0x29>; | |
| rgltr-load-current = <0x00 0x4650 0x7dc8>; | |
| gdscr-supply = <0x2d9>; | |
| rgltr-cntrl-support; | |
| clock-cntl-level = "lowsvs", "nominal"; | |
| compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; | |
| rgltr-min-voltage = <0x00 0x124f80 0xd59f8>; | |
| src-clock-name = "csi5phytimer_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "CSIPHY5"; | |
| reg = <0xacee000 0x2000>; | |
| regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; | |
| phandle = <0x577>; | |
| shared-clks = <0x01 0x00 0x00 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; | |
| }; | |
| qcom,pcie0_msi@0x17110040 { | |
| interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>; | |
| interrupt-parent = <0x01>; | |
| msi-controller; | |
| compatible = "qcom,pci-msi"; | |
| status = "disabled"; | |
| reg = <0x17110040 0x00>; | |
| phandle = <0x4c8>; | |
| }; | |
| qcom,msm-adsp-notify { | |
| compatible = "qcom,adsp-notify"; | |
| status = "ok"; | |
| phandle = <0x51c>; | |
| qcom,rproc-handle = <0x23>; | |
| }; | |
| cti@10b4b000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-lpass_q6_cti"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10b4b000 0x1000>; | |
| phandle = <0x472>; | |
| }; | |
| vote_lpass_audio_hw { | |
| qcom,codec-ext-clk-src = <0x0b>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x518>; | |
| }; | |
| qcom,rimps@17400000 { | |
| #address-cells = <0x02>; | |
| interrupts = <0x00 0x3e 0x04>; | |
| #size-cells = <0x02>; | |
| #mbox-cells = <0x01>; | |
| compatible = "qcom,rimps"; | |
| reg = <0x17400000 0x10 0x17d90000 0x2000>; | |
| phandle = <0x3d>; | |
| }; | |
| gh-secure-vm-loader@1 { | |
| memory-region = <0x86>; | |
| qcom,pas-id = <0x22>; | |
| compatible = "qcom,gh-secure-vm-loader"; | |
| qcom,vmid = <0x31>; | |
| qcom,firmware-name = "oemvm"; | |
| virtio-backends = <0x90>; | |
| }; | |
| cti@1080b000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-mss_q6_cti"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x1080b000 0x1000>; | |
| phandle = <0x47a>; | |
| }; | |
| hsphy@88e3000 { | |
| usb-repeater = <0x616>; | |
| qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; | |
| clock-names = "ref_clk_src", "ref_clk"; | |
| reg-names = "eusb2_phy_base", "eud_enable_reg", "eud_detect_reg"; | |
| resets = <0x45 0x14>; | |
| clocks = <0x46 0x1b 0x5e 0x04>; | |
| vdd-supply = <0x30>; | |
| dummy-supply = <0x616>; | |
| compatible = "qcom,usb-snps-eusb2-phy"; | |
| vdda12-supply = <0x31>; | |
| reg = <0x88e3000 0x154 0x88e2000 0x04 0xc276000 0x04>; | |
| phandle = <0x2b5>; | |
| reset-names = "phy_reset"; | |
| }; | |
| qcom,audio-pkt-core-platform { | |
| compatible = "qcom,audio-pkt-core-platform"; | |
| phandle = <0x51a>; | |
| }; | |
| qcom,camera-flash3 { | |
| cell-index = <0x03>; | |
| torch-source = <0x61f 0x620>; | |
| switch-source = <0x625>; | |
| compatible = "qcom,camera-flash"; | |
| status = "ok"; | |
| phandle = <0x742>; | |
| flash-source = <0x61b 0x61c>; | |
| }; | |
| trust_ui_vm_virt_be1@10 { | |
| qcom,vm = <0x8c>; | |
| qcom,label = <0x10>; | |
| phandle = <0x8e>; | |
| }; | |
| qseecom@c1700000 { | |
| qcom,hlos-num-ce-hw-instances = <0x01>; | |
| qseecom_mem = <0x47>; | |
| qseecom_ta_mem = <0x48>; | |
| memory-region = <0x47>; | |
| qcom,qsee-reentrancy-support = <0x02>; | |
| compatible = "qcom,qseecom"; | |
| qcom,no-clock-support; | |
| qcom,disk-encrypt-pipe-pair = <0x02>; | |
| qcom,appsbl-qseecom-support; | |
| qcom,qsee-ce-hw-instance = <0x00>; | |
| user_contig_mem = <0x49>; | |
| phandle = <0x35a>; | |
| qcom,commonlib64-loaded-by-uefi; | |
| qcom,hlos-ce-hw-instance = <0x00>; | |
| }; | |
| qcom,llcc-l3-vote { | |
| phandle = <0x9e>; | |
| qcom,target-dev = <0x9a>; | |
| qcom,secondary-map = <0x493e0 0x493e0 0x71c50 0x79e00 0x927c0 0x96000 0xc4c70 0xb2200 0xe3c88 0xce400 0x104410 0xe5b00>; | |
| }; | |
| tgu@10b10000 { | |
| arm,primecell-periphid = <0xbb999>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tgu-base"; | |
| clocks = <0x4e>; | |
| tgu-regs = <0x09>; | |
| tgu-steps = <0x03>; | |
| coresight-name = "coresight-tgu-spmi1"; | |
| tgu-conditions = <0x04>; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b10000 0x1000>; | |
| phandle = <0x490>; | |
| tgu-timer-counters = <0x08>; | |
| }; | |
| interconnect@1680000 { | |
| #interconnect-cells = <0x01>; | |
| qcom,bcm-voters = <0x40>; | |
| compatible = "qcom,kalama-system_noc"; | |
| reg = <0x1680000 0x1d080>; | |
| phandle = <0xeb>; | |
| qcom,bcm-voter-names = "hlos"; | |
| }; | |
| cti@10b13000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-cortex_m3"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10b13000 0x1000>; | |
| phandle = <0x46f>; | |
| }; | |
| ufs_phy_tx_symbol_0_clk { | |
| clock-output-names = "ufs_phy_tx_symbol_0_clk"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x5a>; | |
| }; | |
| cluster-device { | |
| power-domains = <0x20>; | |
| compatible = "qcom,lpm-cluster-dev"; | |
| }; | |
| qcom,kgsl-iommu@3da0000 { | |
| vddcx-supply = <0xea>; | |
| compatible = "qcom,kgsl-smmu-v2"; | |
| reg = <0x3da0000 0x40000>; | |
| phandle = <0x5d7>; | |
| gfx3d_user { | |
| iommus = <0xee 0x00 0x00>; | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x5d8>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| gfx3d_lpac { | |
| iommus = <0xee 0x01 0x00>; | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x5d9>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| gfx3d_secure { | |
| iommus = <0xee 0x02 0x00>; | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x5da>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| }; | |
| qcom,ipa@3e00000 { | |
| qcom,use-ipa-tethering-bridge; | |
| qcom,ipa-hw-mode = <0x00>; | |
| qcom,svs2 = <0x00 0x00 0x00 0x13d620 0x00 0x12c00>; | |
| qcom,turbo = <0x36ee80 0x00 0x36ee80 0x53ec60 0x00 0x61a80>; | |
| qcom,ipa-hw-ver = <0x18>; | |
| firmware-names = "ipa_fws"; | |
| qcom,nominal = <0x249f00 0x00 0x249f00 0x53ec60 0x00 0x61a80>; | |
| qcom,smmu-fast-map; | |
| interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa"; | |
| qcom,ipa-cfg-offset = <0x140000>; | |
| pas-ids = <0x0f>; | |
| qcom,svs = <0x124f80 0x00 0x124f80 0x2ab980 0x00 0x249f0>; | |
| clock-names = "core_clk"; | |
| interconnects = <0x4a 0x28 0x61 0x22e 0x4b 0x03 0x4b 0x200 0x61 0x02 0x62 0x212>; | |
| qcom,ulso-ip-id-max-linux-val = <0xffff>; | |
| reg-names = "ipa-base", "gsi-base"; | |
| qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; | |
| qcom,no-vote = <0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,throughput-threshold = <0x7d0 0xfa0 0x1f40>; | |
| qcom,ipa-config-is-apq-no-uc-load; | |
| interrupts = <0x00 0x28e 0x04 0x00 0x1b0 0x04>; | |
| clocks = <0x46 0x0c>; | |
| qcom,ulso-supported; | |
| qcom,platform-type = <0x02>; | |
| qcom,non-tn-collection-on-crash; | |
| qcom,ipa-config-is-apq-dma; | |
| qcom,register-collection-on-crash; | |
| qcom,ulso-ip-id-min-windows-val = <0x00>; | |
| qcom,ipa-config-is-auto; | |
| qcom,tx-poll; | |
| qcom,interconnect,num-paths = <0x03>; | |
| qcom,interconnect,num-cases = <0x05>; | |
| memory-regions = <0x2e4>; | |
| qcom,arm-smmu; | |
| status = "disabled"; | |
| qcom,ulso-ip-id-max-windows-val = <0x7fff>; | |
| interrupt-names = "ipa-irq", "gsi-irq"; | |
| qcom,ulso-ip-id-min-linux-val = <0x00>; | |
| qcom,mhi-event-ring-id-limits = <0x09 0x0b>; | |
| qcom,use-64-bit-dma-mask; | |
| reg = <0x3e00000 0x84000 0x3e04000 0xfc000>; | |
| phandle = <0x507>; | |
| qcom,ee = <0x00>; | |
| qcom,testbus-collection-on-crash; | |
| qcom,entire-ipa-block-size = <0x200000>; | |
| qcom,scaling-exceptions; | |
| qcom,ipa-gpi-event-rp-ddr; | |
| qcom,ipa-endp-delay-wa-v2; | |
| qcom,max_num_smmu_cb = <0x01>; | |
| ipa_smmu_ap { | |
| iommus = <0x4c 0x4a0 0x00>; | |
| qcom,additional-mapping = <0x146a8000 0x146a8000 0x2000>; | |
| qcom,ipa-q6-smem-size = <0xb000>; | |
| compatible = "qcom,ipa-smmu-ap-cb"; | |
| qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; | |
| phandle = <0x508>; | |
| qcom,iommu-dma = "bypass"; | |
| }; | |
| }; | |
| clock-controller@0 { | |
| qcom,gpucc = <0x5d>; | |
| qcom,tcsrcc = <0x5e>; | |
| clock-names = "xo_clk_src", "camcc", "dispcc", "gcc", "gpucc", "tcsrcc", "videocc"; | |
| clocks = <0x46 0x00 0x3b 0x00 0x3c 0x00 0x45 0x00 0x5d 0x00 0x5e 0x00 0x5f 0x00>; | |
| #clock-cells = <0x01>; | |
| qcom,gcc = <0x45>; | |
| qcom,dispcc = <0x3c>; | |
| compatible = "qcom,kalama-debugcc"; | |
| qcom,mccc = <0x60>; | |
| phandle = <0x3df>; | |
| qcom,videocc = <0x5f>; | |
| qcom,apsscc = <0x5c>; | |
| qcom,camcc = <0x3b>; | |
| }; | |
| funnel@10b23000 { | |
| coresight-name = "coresight-funnel-ddr-lpi"; | |
| compatible = "arm,coresight-static-funnel"; | |
| phandle = <0x431>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x12f>; | |
| phandle = <0x125>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x130>; | |
| phandle = <0x1cc>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| replicator@1004e000 { | |
| arm,primecell-periphid = <0xbb909>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "replicator-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-replicator_etr"; | |
| compatible = "arm,primecell"; | |
| reg = <0x1004e000 0x1000>; | |
| phandle = <0x45a>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1d9>; | |
| phandle = <0x1d8>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1da>; | |
| phandle = <0x1dd>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x1db>; | |
| phandle = <0x1de>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@adf052c { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x06>; | |
| regulator-name = "cam_cc_sbi_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xadf052c 0x04>; | |
| phandle = <0x4ff>; | |
| }; | |
| qcom,mdss_dsi_ctrl0@ae94000 { | |
| clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; | |
| reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; | |
| cell-index = <0x00>; | |
| interrupts = <0x04 0x00>; | |
| clocks = <0x3c 0x04 0x3c 0x05 0x3c 0x07 0x3c 0x42 0x3c 0x43 0x3c 0x38 0x46 0x00>; | |
| interrupt-parent = <0x752>; | |
| label = "dsi-ctrl-0"; | |
| vdda-1p2-supply = <0x31>; | |
| compatible = "qcom,dsi-ctrl-hw-v2.7"; | |
| frame-threshold-time-us = <0x320>; | |
| reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; | |
| phandle = <0x74f>; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x41a0>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| }; | |
| }; | |
| }; | |
| qcom,qsee_ipc_irq_bridge { | |
| compatible = "qcom,qsee-ipc-irq-bridge"; | |
| qcom,qsee-ipc-irq-spss { | |
| qcom,dev-name = "qsee_ipc_irq_spss"; | |
| interrupts = <0x10 0x01 0x01>; | |
| interrupt-parent = <0x4f>; | |
| label = "spss"; | |
| }; | |
| }; | |
| qcom,icp { | |
| ubwc-ipe-write-cfg = <0x161ef 0x1620f>; | |
| ubwc-bps-write-cfg = <0x161ef 0x1620f>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; | |
| fw_name = "CAMERA_ICP"; | |
| reg-names = "icp_csr", "icp_cirq", "icp_wd0"; | |
| reg-cam-base = <0x1000 0x1800 0x4000>; | |
| cell-index = <0x00>; | |
| memory-region = <0x2f0>; | |
| interrupts = <0x00 0x1cf 0x01>; | |
| clocks = <0x3b 0x3e 0x3b 0x40 0x3b 0x3f 0x3b 0x8b>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| cam_hw_pid = <0x0c>; | |
| qos-val = <0x808>; | |
| compatible = "qcom,cam-icp_v2"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "icp_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "icp"; | |
| reg = <0xac01000 0x400 0xac01800 0x400 0xac04000 0x1000>; | |
| regulator-names = "gdsc"; | |
| phandle = <0x5c7>; | |
| nrt-device; | |
| icp-version = <0x200>; | |
| clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; | |
| ubwc-ipe-fetch-cfg = <0x707b 0x7083>; | |
| ubwc-bps-fetch-cfg = <0x707b 0x7083>; | |
| }; | |
| tpdm@10003000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x41>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| qcom,hw-enable-check; | |
| coresight-name = "coresight-tpdm-dcc"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10003000 0x1000>; | |
| phandle = <0x417>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10e>; | |
| phandle = <0x1b7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| reboot_reason { | |
| nvmem-cells = <0x5fc>; | |
| compatible = "qcom,reboot-reason"; | |
| nvmem-cell-names = "restart_reason"; | |
| }; | |
| qcom,gpi-dma@a00000 { | |
| iommus = <0x4c 0xb6 0x00>; | |
| qcom,gpi-ee-offset = <0x10000>; | |
| qcom,gpii-mask = <0x1e>; | |
| dma-coherent; | |
| qcom,static-gpii-mask = <0x01>; | |
| reg-names = "gpi-top"; | |
| interrupts = <0x00 0x117 0x04 0x00 0x118 0x04 0x00 0x119 0x04 0x00 0x11a 0x04 0x00 0x11b 0x04 0x00 0x11c 0x04 0x00 0x125 0x04 0x00 0x126 0x04 0x00 0x127 0x04 0x00 0x128 0x04 0x00 0x129 0x04 0x00 0x12a 0x04>; | |
| qcom,ev-factor = <0x02>; | |
| compatible = "qcom,gpi-dma"; | |
| status = "ok"; | |
| qcom,iommu-dma-addr-pool = <0x100000 0x100000>; | |
| qcom,max-num-gpii = <0x0c>; | |
| reg = <0xa00000 0x60000>; | |
| phandle = <0x201>; | |
| #dma-cells = <0x05>; | |
| }; | |
| qcom,cvp@ab00000 { | |
| qcom,allowed-clock-rates = <0x14dc9380 0x1ad27480 0x1dcd6500 0x20c85580>; | |
| qcom,ipcc-reg = <0x400000 0x100000>; | |
| pas-id = <0x1a>; | |
| qcom,gcc-reg = <0x110000 0x40000>; | |
| clock-names = "gcc_video_axi1", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; | |
| clock-ids = <0xa9 0x0a 0x07 0x08>; | |
| resets = <0x45 0x22 0x5f 0x05>; | |
| memory-region = <0x2bc>; | |
| interrupts = <0x00 0xea 0x04>; | |
| cvp-supply = <0x2ba>; | |
| clocks = <0x45 0xa9 0x5f 0x0a 0x5f 0x07 0x5f 0x08>; | |
| cvp,firmware-name = "evass"; | |
| qcom,reg-presets = <0xb0088 0x00>; | |
| cvp-core-supply = <0x2bb>; | |
| compatible = "qcom,msm-cvp", "qcom,kalama-cvp"; | |
| status = "ok"; | |
| reg = <0xab00000 0x100000>; | |
| phandle = <0x509>; | |
| qcom,proxy-clock-names = "gcc_video_axi1", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; | |
| reset-names = "cvp_axi_reset", "cvp_core_reset"; | |
| qcom,clock-configs = <0x00 0x00 0x00 0x01>; | |
| cache-slice-names = "cvp"; | |
| reset-power-status = <0x02 0x02>; | |
| qcom,msm-cvp,mem_cdsp { | |
| memory-region = <0x2bd>; | |
| compatible = "qcom,msm-cvp,mem-cdsp"; | |
| }; | |
| cvp_non_secure_cb { | |
| iommus = <0x4c 0x1920 0x00>; | |
| dma-coherent; | |
| label = "cvp_hlos"; | |
| compatible = "qcom,msm-cvp,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; | |
| buffer-types = <0xfff>; | |
| qcom,iommu-faults = "non-fatal"; | |
| }; | |
| cvp_bus_ddr { | |
| qcom,bus-governor = "performance"; | |
| label = "cvp-ddr"; | |
| compatible = "qcom,msm-cvp,bus"; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-master = <0x1f>; | |
| qcom,bus-range-kbps = <0x3e8 0x63af88>; | |
| }; | |
| cvp_secure_pixel_cb { | |
| iommus = <0x4c 0x1923 0x00>; | |
| label = "cvp_sec_pixel"; | |
| compatible = "qcom,msm-cvp,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; | |
| buffer-types = <0x106>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| cvp_secure_nonpixel_cb { | |
| iommus = <0x4c 0x1924 0x00>; | |
| label = "cvp_sec_nonpixel"; | |
| compatible = "qcom,msm-cvp,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; | |
| buffer-types = <0x741>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0b>; | |
| }; | |
| cvp_cnoc { | |
| qcom,bus-governor = "performance"; | |
| label = "cvp-cnoc"; | |
| compatible = "qcom,msm-cvp,bus"; | |
| qcom,bus-slave = <0x227>; | |
| qcom,bus-master = <0x02>; | |
| qcom,bus-range-kbps = <0x3e8 0x3e8>; | |
| }; | |
| }; | |
| cti@10982000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-turing_dl_cti_0"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x10982000 0x1000>; | |
| phandle = <0x46a>; | |
| }; | |
| qcom,csid1@acb9000 { | |
| clock-control-debugfs = "true"; | |
| clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; | |
| reg-names = "csid", "csid_top"; | |
| reg-cam-base = <0xb9000 0xb6000>; | |
| cell-index = <0x01>; | |
| interrupts = <0x00 0x25b 0x01>; | |
| clocks = <0x3b 0x30 0x3b 0x2f 0x3b 0x31>; | |
| rt-wrapper-base = <0x62000>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| compatible = "qcom,csid780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "csid_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "csid1"; | |
| reg = <0xacb9000 0xd00 0xacb6000 0x1000>; | |
| regulator-names = "gdsc"; | |
| phandle = <0x5bc>; | |
| shared-clks = <0x01 0x00 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; | |
| }; | |
| cti@10813000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-mss_vq6_cti"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10813000 0x1000>; | |
| phandle = <0x47b>; | |
| }; | |
| syscon@3d99058 { | |
| compatible = "syscon"; | |
| reg = <0x3d99058 0x04>; | |
| phandle = <0x2df>; | |
| }; | |
| qcom,cpu-voltage-cdev { | |
| compatible = "qcom,cc-cooling-devices"; | |
| thermal-cluster-1-2 { | |
| qcom,cluster1 = <0x1f>; | |
| phandle = <0x4d9>; | |
| qcom,cluster0 = <0x1b 0x1c 0x1d 0x1e>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| funnel@10d22000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-ddr_ch02"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10d22000 0x1000>; | |
| phandle = <0x439>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x145>; | |
| phandle = <0xf7>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x146>; | |
| phandle = <0x14e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cpu-vendor-hooks { | |
| compatible = "qcom,cpu-vendor-hooks"; | |
| phandle = <0x358>; | |
| }; | |
| tpdm@10c29000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-ipcc"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10c29000 0x1000>; | |
| phandle = <0x412>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x109>; | |
| phandle = <0x1a8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cpufreq-hw-debug { | |
| qcom,freq-hw-domain = <0x06 0x00 0x06 0x01 0x06 0x02>; | |
| compatible = "qcom,cpufreq-hw-epss-debug"; | |
| }; | |
| qcom,mmrm { | |
| mmrm-client-info = <0x01 0x42 0x1dc18c0 0x3a3d7 0x01 0x01 0x47 0x1dc1893 0x3a3d7 0x01 0x01 0x4c 0x1dc1893 0x3a3d7 0x01 0x01 0x30 0x1c5aad 0x00 0x03 0x01 0x8f 0xe90f5c 0x3ee14 0x01 0x01 0x92 0xe90f5c 0x3ee14 0x01 0x01 0x58 0x54b5c29 0xf0f5c 0x01 0x01 0x02 0x1cb3d71 0x14a3d 0x01 0x01 0x52 0x1649ab 0x4e56 0x02 0x01 0x5e 0xa199a 0x47ae 0x04 0x01 0x05 0x2cb852 0x5ee14 0x01 0x01 0x55 0x370a4 0x00 0x02 0x01 0x40 0x420c5 0x00 0x01 0x01 0x1b 0x4ccd 0x00 0x0a 0x01 0x20 0x1604 0x00 0x01 0x01 0x22 0x1604 0x00 0x01 0x01 0x24 0x1604 0x00 0x01 0x01 0x26 0x1604 0x00 0x01 0x01 0x28 0x1604 0x00 0x01 0x01 0x2a 0x1604 0x00 0x01 0x01 0x2c 0x1604 0x00 0x01 0x01 0x2e 0x1604 0x00 0x01 0x01 0x09 0x00 0x00 0x01 0x01 0x0b 0x00 0x00 0x01 0x01 0x0d 0x00 0x00 0x01 0x01 0x96 0xeb92 0x00 0x01 0x01 0x3c 0x76e3 0x00 0x01 0x01 0x1e 0x50000 0x00 0x01 0x02 0x08 0x3f0c000 0x7451f 0x01 0x03 0x3e 0x15a999a 0x30000 0x01 0x03 0x10 0xdb333 0xccd 0x01 0x04 0x03 0xd1bd71 0x76b85 0x01>; | |
| mm-rail-fact-volt = <0x926c 0xa0c5 0xaf1b 0xba5e 0xcccd>; | |
| scaling-fact-leak = <0x9c0f 0xa4034 0xbf72b 0xd7ef3 0x108639>; | |
| mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo"; | |
| compatible = "qcom,msm-mmrm", "qcom,kalama-mmrm"; | |
| status = "okay"; | |
| mmrm-peak-threshold = <0x2710>; | |
| phandle = <0x5d2>; | |
| scaling-fact-dyn = <0x9c0f 0xbe0e 0xe3eb 0x10474 0x13f5c>; | |
| }; | |
| qcom,memshare { | |
| compatible = "qcom,memshare"; | |
| qcom,client_2 { | |
| qcom,peripheral-size = <0x00>; | |
| qcom,client-id = <0x02>; | |
| label = "modem"; | |
| compatible = "qcom,memshare-peripheral"; | |
| }; | |
| qcom,client_5 { | |
| qcom,peripheral-size = <0x00>; | |
| qcom,client-id = <0x06>; | |
| qcom,shared; | |
| qcom,allocate-on-request; | |
| label = "modem"; | |
| compatible = "qcom,memshare-peripheral"; | |
| phandle = <0x3dd>; | |
| }; | |
| qcom,client_3 { | |
| qcom,peripheral-size = <0x00>; | |
| qcom,client-id = <0x01>; | |
| qcom,allocate-on-request; | |
| label = "modem"; | |
| compatible = "qcom,memshare-peripheral"; | |
| phandle = <0x3db>; | |
| }; | |
| qcom,client_1 { | |
| qcom,peripheral-size = <0x00>; | |
| qcom,client-id = <0x00>; | |
| label = "modem"; | |
| qcom,allocate-boot-time; | |
| compatible = "qcom,memshare-peripheral"; | |
| }; | |
| qcom,client_4 { | |
| qcom,peripheral-size = <0x00>; | |
| qcom,client-id = <0x05>; | |
| qcom,shared; | |
| memory-region = <0x53>; | |
| qcom,allocate-on-request; | |
| label = "modem"; | |
| compatible = "qcom,memshare-peripheral"; | |
| phandle = <0x3dc>; | |
| }; | |
| }; | |
| funnel@1080d000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base-dummy", "funnel-base-real"; | |
| qcom,duplicate-funnel; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-modem_q6_dup"; | |
| compatible = "arm,primecell"; | |
| reg = <0x1080d000 0x1000 0x1080c000 0x1000>; | |
| phandle = <0x449>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x18a>; | |
| phandle = <0x11d>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x18b>; | |
| phandle = <0x18c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@10004000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpda-qdss"; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x41>; | |
| reg = <0x10004000 0x1000>; | |
| phandle = <0x450>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1b7>; | |
| phandle = <0x10e>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x1b6>; | |
| phandle = <0x10c>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1b8>; | |
| phandle = <0x1bb>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,spmi@c42d000 { | |
| #address-cells = <0x02>; | |
| reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; | |
| qcom,channel = <0x00>; | |
| cell-index = <0x00>; | |
| #size-cells = <0x00>; | |
| interrupts-extended = <0x51 0x01 0x04>; | |
| compatible = "qcom,spmi-pmic-arb"; | |
| #interrupt-cells = <0x04>; | |
| qcom,bus-id = <0x00>; | |
| interrupt-names = "periph_irq"; | |
| reg = <0xc42d000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4c0000 0x10000>; | |
| phandle = <0xe6>; | |
| qcom,ee = <0x00>; | |
| interrupt-controller; | |
| qcom,pm8550vs@4 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| status = "ok"; | |
| reg = <0x04 0x00>; | |
| phandle = <0x63d>; | |
| pinctrl@8800 { | |
| gpio-controller; | |
| compatible = "qcom,pm8550vs-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x8800>; | |
| phandle = <0x63e>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| }; | |
| pm8550vs-e-temp-alarm@a00 { | |
| interrupts = <0x04 0x0a 0x00 0x03>; | |
| io-channels = <0x5e6 0x403>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0xa00>; | |
| phandle = <0x5f4>; | |
| io-channel-names = "thermal"; | |
| }; | |
| }; | |
| qcom,pm8010@d { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| status = "disabled"; | |
| reg = <0x0d 0x00>; | |
| phandle = <0x65b>; | |
| pm8010-n-temp-alarm@2400 { | |
| interrupts = <0x0d 0x24 0x00 0x03>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| status = "disabled"; | |
| reg = <0x2400>; | |
| phandle = <0x5fb>; | |
| }; | |
| }; | |
| qcom,pm8550vs@2 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x02 0x00>; | |
| phandle = <0x638>; | |
| pm8550vs-c-temp-alarm@a00 { | |
| interrupts = <0x02 0x0a 0x00 0x03>; | |
| io-channels = <0x5e6 0x203>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0xa00>; | |
| phandle = <0x5f2>; | |
| io-channel-names = "thermal"; | |
| }; | |
| pinctrl@8800 { | |
| gpio-controller; | |
| compatible = "qcom,pm8550vs-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x8800>; | |
| phandle = <0x639>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| qcom,pmk8550@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x00 0x00>; | |
| sdam@7100 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x7100>; | |
| phandle = <0x651>; | |
| restart@48 { | |
| bits = <0x01 0x07>; | |
| reg = <0x48 0x01>; | |
| phandle = <0x5fc>; | |
| }; | |
| }; | |
| pon_hlos@1300 { | |
| reg-names = "pon_hlos", "pon_pbs"; | |
| compatible = "qcom,pm8998-pon"; | |
| reg = <0x1300 0x800>; | |
| resin { | |
| interrupts = <0x00 0x13 0x06 0x03>; | |
| compatible = "qcom,pmk8350-resin"; | |
| linux,code = <0x72>; | |
| }; | |
| pwrkey { | |
| interrupts = <0x00 0x13 0x07 0x03>; | |
| compatible = "qcom,pmk8350-pwrkey"; | |
| linux,code = <0x74>; | |
| }; | |
| }; | |
| sdam@7400 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x7400>; | |
| phandle = <0x5fe>; | |
| }; | |
| sdam@9a00 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x9a00>; | |
| phandle = <0x655>; | |
| sqm-timer@b8 { | |
| reg = <0xb8 0x02>; | |
| phandle = <0x656>; | |
| }; | |
| }; | |
| sdam@9800 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x9800>; | |
| phandle = <0x654>; | |
| }; | |
| sdam@7c00 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x7c00>; | |
| phandle = <0x652>; | |
| }; | |
| sdam@9d00 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x9d00>; | |
| phandle = <0x5ec>; | |
| }; | |
| sdam@7000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x7000>; | |
| phandle = <0x64f>; | |
| smb1510_present@5d { | |
| bits = <0x05 0x05>; | |
| reg = <0x5d 0x01>; | |
| phandle = <0x650>; | |
| }; | |
| ocp-log@76 { | |
| reg = <0x76 0x06>; | |
| phandle = <0x600>; | |
| }; | |
| }; | |
| pinctrl@b800 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x5f6>; | |
| gpio-controller; | |
| compatible = "qcom,pmk8550-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0xb800>; | |
| phandle = <0x657>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| lcd_backlight_ctrl { | |
| lcd_backlight_ctrl_active { | |
| input-disable; | |
| function = "func3"; | |
| pins = "gpio5"; | |
| qcom,drive-strength = <0x02>; | |
| bias-disable; | |
| output-high; | |
| phandle = <0x5f8>; | |
| power-source = <0x00>; | |
| }; | |
| lcd_backlight_ctrl_default { | |
| input-disable; | |
| function = "func3"; | |
| pins = "gpio5"; | |
| qcom,drive-strength = <0x02>; | |
| bias-disable; | |
| phandle = <0x5f7>; | |
| output-enable; | |
| power-source = <0x00>; | |
| }; | |
| lcd_backlight_ctrl_suspend { | |
| input-disable; | |
| function = "func3"; | |
| pins = "gpio5"; | |
| qcom,drive-strength = <0x02>; | |
| bias-disable; | |
| phandle = <0x5f9>; | |
| power-source = <0x00>; | |
| output-low; | |
| }; | |
| }; | |
| alt_sleep_clk { | |
| alt_sleep_clk_default { | |
| input-disable; | |
| function = "func1"; | |
| pins = "gpio3"; | |
| bias-disable; | |
| phandle = <0x5f6>; | |
| output-enable; | |
| power-source = <0x00>; | |
| }; | |
| }; | |
| }; | |
| sdam@8500 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x8500>; | |
| phandle = <0x5e8>; | |
| }; | |
| vadc@9000 { | |
| io-channel-ranges; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; | |
| #io-channel-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,spmi-adc5-gen3"; | |
| interrupt-names = "adc-sdam0", "adc-sdam1"; | |
| reg = <0x9000 0x9100>; | |
| phandle = <0x5e6>; | |
| smb139x_1_iin_smb { | |
| label = "smb139x_1_iin_smb"; | |
| reg = <0x919>; | |
| }; | |
| pm8550vs_e_die_temp { | |
| label = "pm8550vs_e_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x403>; | |
| }; | |
| pm8550b_chg_temp { | |
| label = "pm8550b_chg_temp"; | |
| reg = <0x710>; | |
| }; | |
| pm8550_amux5_volt { | |
| label = "pm8550_amux5_volt"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x108>; | |
| }; | |
| pm8550b_vref_1p25 { | |
| label = "pm8550b_vref_1p25"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x701>; | |
| }; | |
| pm8550b_vbat_sns_qbg { | |
| label = "pm8550b_vbat_sns_qbg"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x78f>; | |
| }; | |
| pm8550b_lite_die_temp { | |
| label = "pm8550b_lite_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x718>; | |
| }; | |
| pmk8550_vref_1p25 { | |
| label = "pmk8550_vref_1p25"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x01>; | |
| }; | |
| pm8550_amux4_volt { | |
| label = "pm8550_amux4_volt"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x107>; | |
| }; | |
| pmk8550_die_temp { | |
| label = "pmk8550_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x03>; | |
| }; | |
| pm8550vs_g_die_temp { | |
| label = "pm8550vs_g_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x603>; | |
| }; | |
| smb139x_1_ichg_smb { | |
| label = "smb139x_1_ichg_smb"; | |
| reg = <0x91b>; | |
| }; | |
| smb139x_2_iin_smb { | |
| label = "smb139x_2_iin_smb"; | |
| reg = <0xb19>; | |
| }; | |
| pm8550b_offset_ref { | |
| label = "pm8550b_offset_ref"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x700>; | |
| }; | |
| pm8550_die_temp { | |
| label = "pm8550_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x103>; | |
| }; | |
| pm8550vs_c_die_temp { | |
| label = "pm8550vs_c_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x203>; | |
| }; | |
| pm8550b_vph_pwr { | |
| label = "pm8550b_vph_pwr"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x78e>; | |
| }; | |
| smb139x_1_smb_temp { | |
| label = "smb139x_1_smb_temp"; | |
| reg = <0x906>; | |
| }; | |
| pmk8550_offset_ref { | |
| label = "pmk8550_offset_ref"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x00>; | |
| }; | |
| smb139x_2_ichg_smb { | |
| label = "smb139x_2_ichg_smb"; | |
| reg = <0xb1b>; | |
| }; | |
| pm8550_amux2_volt { | |
| label = "pm8550_amux2_volt"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x105>; | |
| }; | |
| pm8550_vref_1p25 { | |
| label = "pm8550_vref_1p25"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x101>; | |
| }; | |
| pm8550b_wls_therm { | |
| qcom,adc-tm-type = <0x01>; | |
| label = "pm8550b_wls_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x749>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| pmk8550_xo_therm { | |
| qcom,adc-tm-type = <0x01>; | |
| label = "pmk8550_xo_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x44>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| pm8550_vph_pwr { | |
| label = "pm8550_vph_pwr"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x18e>; | |
| }; | |
| pm8550b_usb_therm { | |
| qcom,adc-tm-type = <0x01>; | |
| label = "pm8550b_usb_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x747>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| pm8550vs_d_die_temp { | |
| label = "pm8550vs_d_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x303>; | |
| }; | |
| smb139x_2_smb_temp { | |
| label = "smb139x_2_smb_temp"; | |
| reg = <0xb06>; | |
| }; | |
| pm8550ve_die_temp { | |
| label = "pm8550ve_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x503>; | |
| }; | |
| pm8550_offset_ref { | |
| label = "pm8550_offset_ref"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x100>; | |
| }; | |
| pm8550b_ichg_fb { | |
| label = "pm8550b_ichg_fb"; | |
| reg = <0x7a1>; | |
| }; | |
| pm8550b_die_temp { | |
| label = "pm8550b_die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x703>; | |
| }; | |
| pm8550b_iin_fb { | |
| label = "pm8550b_iin_fb"; | |
| reg = <0x717>; | |
| }; | |
| }; | |
| rtc@6100 { | |
| reg-names = "rtc", "alarm"; | |
| interrupts = <0x00 0x62 0x01 0x01>; | |
| compatible = "qcom,pmk8350-rtc"; | |
| reg = <0x6100 0x6200>; | |
| phandle = <0x659>; | |
| }; | |
| sdam@8400 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x8400>; | |
| phandle = <0x5e7>; | |
| }; | |
| pwms@e800 { | |
| pinctrl-names = "default", "active", "suspend"; | |
| qcom,num-lpg-channels = <0x01>; | |
| pinctrl-2 = <0x5f9>; | |
| qcom,tick-duration-us = <0x1e78>; | |
| pinctrl-0 = <0x5f7>; | |
| reg-names = "lpg-base"; | |
| nvmem-names = "lpg_chan_sdam", "lut_sdam"; | |
| #pwm-cells = <0x02>; | |
| compatible = "qcom,pwm-lpg"; | |
| pinctrl-1 = <0x5f8>; | |
| nvmem = <0x5e7 0x5e8>; | |
| qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; | |
| reg = <0xe800>; | |
| qcom,lut-sdam-base = <0x45>; | |
| phandle = <0x658>; | |
| lpg@1 { | |
| qcom,ramp-pattern-repeat; | |
| qcom,ramp-step-ms = <0x64>; | |
| qcom,ramp-low-index = <0x00>; | |
| qcom,ramp-high-index = <0x13>; | |
| qcom,lpg-sdam-base = <0x48>; | |
| qcom,lpg-chan-id = <0x01>; | |
| }; | |
| }; | |
| sdam@7500 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x7500>; | |
| phandle = <0x5ff>; | |
| }; | |
| sdam@7d00 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0x7d00>; | |
| phandle = <0x653>; | |
| }; | |
| }; | |
| qcom,pm8550ve_f@5 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x05 0x00>; | |
| pm8550ve-f-temp-alarm@a00 { | |
| interrupts = <0x05 0x0a 0x00 0x03>; | |
| io-channels = <0x5e6 0x503>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0xa00>; | |
| phandle = <0x5f1>; | |
| io-channel-names = "thermal"; | |
| }; | |
| pinctrl@8800 { | |
| gpio-controller; | |
| compatible = "qcom,pm8550ve-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x8800>; | |
| phandle = <0x634>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| qcom,pm8550vs@3 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| status = "ok"; | |
| reg = <0x03 0x00>; | |
| phandle = <0x63a>; | |
| pm8550vs-d-temp-alarm@a00 { | |
| interrupts = <0x03 0x0a 0x00 0x03>; | |
| io-channels = <0x5e6 0x303>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0xa00>; | |
| phandle = <0x5f3>; | |
| io-channel-names = "thermal"; | |
| }; | |
| pinctrl@8800 { | |
| gpio-controller; | |
| compatible = "qcom,pm8550vs-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x8800>; | |
| phandle = <0x63b>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| eusb2_repeater_reset { | |
| eusb2_repeater_reset_default { | |
| function = "normal"; | |
| pins = "gpio4"; | |
| qcom,drive-strength = <0x02>; | |
| bias-disable; | |
| phandle = <0x63c>; | |
| output-enable; | |
| power-source = <0x01>; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,pm8010@c { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| status = "disabled"; | |
| reg = <0x0c 0x00>; | |
| phandle = <0x65a>; | |
| pm8010-m-temp-alarm@2400 { | |
| interrupts = <0x0c 0x24 0x00 0x03>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| status = "disabled"; | |
| reg = <0x2400>; | |
| phandle = <0x5fa>; | |
| }; | |
| }; | |
| qcom,pm8550@1 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x01 0x00>; | |
| bcl@4700 { | |
| qcom,pmic7-threshold; | |
| interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,bcl-v5"; | |
| interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; | |
| reg = <0x4700 0x100>; | |
| phandle = <0x5eb>; | |
| }; | |
| qcom,flash_led@ee00 { | |
| interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; | |
| compatible = "qcom,pm8350c-flash-led"; | |
| status = "ok"; | |
| interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; | |
| reg = <0xee00>; | |
| phandle = <0x61a>; | |
| qcom,thermal-derate-current = <0xc8 0x1f4>; | |
| qcom,flash_3 { | |
| qcom,led-name = "led:flash_3"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x03>; | |
| qcom,duration-ms = <0x500>; | |
| label = "flash"; | |
| phandle = <0x61e>; | |
| qcom,default-led-trigger = "flash3_trigger"; | |
| qcom,max-current-ma = <0x5dc>; | |
| }; | |
| qcom,torch_2 { | |
| qcom,led-name = "led:torch_2"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x02>; | |
| label = "torch"; | |
| phandle = <0x621>; | |
| qcom,default-led-trigger = "torch2_trigger"; | |
| qcom,max-current-ma = <0x1f4>; | |
| }; | |
| qcom,flash_1 { | |
| qcom,led-name = "led:flash_1"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x01>; | |
| qcom,duration-ms = <0x500>; | |
| label = "flash"; | |
| phandle = <0x61c>; | |
| qcom,default-led-trigger = "flash1_trigger"; | |
| qcom,max-current-ma = <0x5dc>; | |
| }; | |
| qcom,torch_0 { | |
| qcom,led-name = "led:torch_0"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x00>; | |
| label = "torch"; | |
| phandle = <0x61f>; | |
| qcom,default-led-trigger = "torch0_trigger"; | |
| qcom,max-current-ma = <0x1f4>; | |
| }; | |
| qcom,led_switch_1 { | |
| qcom,led-name = "led:switch_1"; | |
| qcom,led-mask = <0x06>; | |
| label = "switch"; | |
| phandle = <0x624>; | |
| qcom,default-led-trigger = "switch1_trigger"; | |
| qcom,symmetry-en; | |
| }; | |
| qcom,torch_3 { | |
| qcom,led-name = "led:torch_3"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x03>; | |
| label = "torch"; | |
| phandle = <0x622>; | |
| qcom,default-led-trigger = "torch3_trigger"; | |
| qcom,max-current-ma = <0x1f4>; | |
| }; | |
| qcom,flash_2 { | |
| qcom,led-name = "led:flash_2"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x02>; | |
| qcom,duration-ms = <0x500>; | |
| label = "flash"; | |
| phandle = <0x61d>; | |
| qcom,default-led-trigger = "flash2_trigger"; | |
| qcom,max-current-ma = <0x5dc>; | |
| }; | |
| qcom,torch_1 { | |
| qcom,led-name = "led:torch_1"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x01>; | |
| label = "torch"; | |
| phandle = <0x620>; | |
| qcom,default-led-trigger = "torch1_trigger"; | |
| qcom,max-current-ma = <0x1f4>; | |
| }; | |
| qcom,flash_0 { | |
| qcom,led-name = "led:flash_0"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x00>; | |
| qcom,duration-ms = <0x500>; | |
| label = "flash"; | |
| phandle = <0x61b>; | |
| qcom,default-led-trigger = "flash0_trigger"; | |
| qcom,max-current-ma = <0x5dc>; | |
| }; | |
| qcom,led_switch_2 { | |
| qcom,led-name = "led:switch_2"; | |
| qcom,led-mask = <0x0f>; | |
| label = "switch"; | |
| phandle = <0x625>; | |
| qcom,default-led-trigger = "switch2_trigger"; | |
| qcom,symmetry-en; | |
| }; | |
| qcom,led_switch_0 { | |
| qcom,led-name = "led:switch_0"; | |
| qcom,led-mask = <0x09>; | |
| label = "switch"; | |
| phandle = <0x623>; | |
| qcom,default-led-trigger = "switch0_trigger"; | |
| qcom,symmetry-en; | |
| }; | |
| }; | |
| pm8550-temp-alarm@a00 { | |
| interrupts = <0x01 0x0a 0x00 0x03>; | |
| io-channels = <0x5e6 0x103>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0xa00>; | |
| phandle = <0x5ea>; | |
| io-channel-names = "thermal"; | |
| }; | |
| pwms@eb00 { | |
| qcom,num-lpg-channels = <0x01>; | |
| reg-names = "lpg-base"; | |
| #pwm-cells = <0x02>; | |
| compatible = "qcom,pwm-lpg"; | |
| reg = <0xeb00>; | |
| phandle = <0x613>; | |
| }; | |
| qcom,leds@ef00 { | |
| compatible = "qcom,tri-led"; | |
| reg = <0xef00>; | |
| phandle = <0x619>; | |
| green { | |
| linux,default-trigger = "timer"; | |
| label = "green"; | |
| led-sources = <0x01>; | |
| pwms = <0x5e9 0x01 0xf4240>; | |
| }; | |
| red { | |
| linux,default-trigger = "timer"; | |
| label = "red"; | |
| led-sources = <0x00>; | |
| pwms = <0x5e9 0x00 0xf4240>; | |
| }; | |
| blue { | |
| linux,default-trigger = "timer"; | |
| label = "blue"; | |
| led-sources = <0x02>; | |
| pwms = <0x5e9 0x02 0xf4240>; | |
| }; | |
| }; | |
| pinctrl@8800 { | |
| gpio-controller; | |
| compatible = "qcom,pm8550-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x8800>; | |
| phandle = <0x5fd>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| pwm_out { | |
| pwm_out_default { | |
| input-disable; | |
| function = "func1"; | |
| pins = "gpio8"; | |
| bias-disable; | |
| phandle = <0x614>; | |
| output-enable; | |
| power-source = <0x01>; | |
| output-low; | |
| }; | |
| }; | |
| key_vol_up { | |
| key_vol_up_default { | |
| function = "normal"; | |
| pins = "gpio6"; | |
| phandle = <0x612>; | |
| bias-pull-up; | |
| power-source = <0x01>; | |
| input-enable; | |
| }; | |
| }; | |
| sd_card_det { | |
| sd_card_det_default { | |
| function = "normal"; | |
| pins = "gpio12"; | |
| phandle = <0x611>; | |
| output-disable; | |
| bias-pull-up; | |
| power-source = <0x01>; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| pwms@e800 { | |
| qcom,num-lpg-channels = <0x03>; | |
| qcom,tick-duration-us = <0x1e78>; | |
| reg-names = "lpg-base"; | |
| nvmem-names = "lpg_chan_sdam", "lut_sdam"; | |
| #pwm-cells = <0x02>; | |
| compatible = "qcom,pwm-lpg"; | |
| nvmem = <0x5e7 0x5e8>; | |
| qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; | |
| reg = <0xe800>; | |
| qcom,lut-sdam-base = <0x45>; | |
| phandle = <0x5e9>; | |
| lpg@2 { | |
| qcom,ramp-pattern-repeat; | |
| qcom,ramp-step-ms = <0x64>; | |
| qcom,ramp-low-index = <0x00>; | |
| qcom,ramp-high-index = <0x13>; | |
| qcom,lpg-sdam-base = <0x56>; | |
| qcom,lpg-chan-id = <0x02>; | |
| }; | |
| lpg@3 { | |
| qcom,ramp-pattern-repeat; | |
| qcom,ramp-step-ms = <0x64>; | |
| qcom,ramp-low-index = <0x00>; | |
| qcom,ramp-high-index = <0x13>; | |
| qcom,lpg-sdam-base = <0x64>; | |
| qcom,lpg-chan-id = <0x03>; | |
| }; | |
| lpg@1 { | |
| qcom,ramp-pattern-repeat; | |
| qcom,ramp-step-ms = <0x64>; | |
| qcom,ramp-low-index = <0x00>; | |
| qcom,ramp-high-index = <0x13>; | |
| qcom,lpg-sdam-base = <0x48>; | |
| qcom,lpg-chan-id = <0x01>; | |
| }; | |
| }; | |
| }; | |
| qcom,pm8550b@7 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x07 0x00>; | |
| bcl@4700 { | |
| qcom,pmic7-threshold; | |
| interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,bcl-v5"; | |
| interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; | |
| reg = <0x4700 0x100>; | |
| phandle = <0x5ef>; | |
| }; | |
| eusb2-repeater@fd00 { | |
| vdd18-supply = <0x30f>; | |
| qcom,param-override-seq = <0x07 0x51 0x03 0x54 0x03 0x57 0x06 0x53>; | |
| vdd3-supply = <0x308>; | |
| compatible = "qcom,pmic-eusb2-repeater"; | |
| reg = <0xfd00>; | |
| phandle = <0x616>; | |
| }; | |
| pm8550b-temp-alarm@a00 { | |
| interrupts = <0x07 0x0a 0x00 0x03>; | |
| io-channels = <0x5e6 0x703>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0xa00>; | |
| phandle = <0x5ed>; | |
| io-channel-names = "thermal"; | |
| }; | |
| pinctrl@8800 { | |
| gpio-controller; | |
| compatible = "qcom,pm8550b-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x8800>; | |
| phandle = <0x62a>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| }; | |
| pm8550b-temp-alarm-lite@c00 { | |
| interrupts = <0x07 0x0c 0x00 0x03>; | |
| io-channels = <0x5e6 0x718>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0xc00>; | |
| phandle = <0x5ee>; | |
| io-channel-names = "thermal"; | |
| }; | |
| qcom,hv-haptics@f000 { | |
| qcom,brake-pattern = [ff 3f 1f]; | |
| qcom,brake-mode = <0x01>; | |
| nvmem-names = "hap_cfg_sdam"; | |
| qcom,vmax-mv = <0x514>; | |
| interrupts = <0x07 0xf0 0x01 0x01>; | |
| qcom,lra-period-us = <0x16f8>; | |
| compatible = "qcom,hv-haptics"; | |
| status = "ok"; | |
| nvmem = <0x5ec>; | |
| qcom,brake-sig-shape = <0x01>; | |
| interrupt-names = "fifo-empty"; | |
| reg = <0xf000 0xf100 0xf200>; | |
| phandle = <0x62b>; | |
| qcom,drv-sig-shape = <0x01>; | |
| effect_0 { | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,effect-id = <0x00>; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x514>; | |
| qcom,wf-pattern-data = <0x11f 0x00 0x00 0x13f 0x00 0x00 0x15f 0x00 0x00 0x17f 0x00 0x00 0x17f 0x00 0x00 0x15f 0x00 0x00 0x13f 0x00 0x00 0x11f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_4 { | |
| qcom,primitive-id = <0x04>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0xff 0x00 0x00 0x7f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_2 { | |
| qcom,primitive-id = <0x02>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0xff 0x00 0x00 0x7f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| effect_5 { | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,effect-id = <0x05>; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x514>; | |
| qcom,wf-pattern-data = <0x11f 0x00 0x00 0x13f 0x00 0x00 0x15f 0x00 0x00 0x17f 0x00 0x00 0x17f 0x00 0x00 0x15f 0x00 0x00 0x13f 0x00 0x00 0x11f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_0 { | |
| qcom,primitive-id = <0x00>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| effect_3 { | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,effect-id = <0x03>; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x514>; | |
| qcom,wf-pattern-data = <0x1f 0x00 0x00 0x3f 0x00 0x00 0x5f 0x00 0x00 0x7f 0x00 0x00 0x17f 0x00 0x00 0x15f 0x00 0x00 0x13f 0x00 0x00 0x11f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_7 { | |
| qcom,primitive-id = <0x07>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0xff 0x00 0x00 0x7f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| effect_1 { | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,effect-id = <0x01>; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x514>; | |
| qcom,wf-pattern-data = <0x1f 0x00 0x00 0x3f 0x00 0x00 0x5f 0x00 0x00 0x7f 0x00 0x00 0x17f 0x00 0x00 0x15f 0x00 0x00 0x13f 0x00 0x00 0x11f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_5 { | |
| qcom,primitive-id = <0x05>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0xff 0x00 0x00 0x7f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_3 { | |
| qcom,primitive-id = <0x03>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0xff 0x00 0x00 0x7f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_1 { | |
| qcom,primitive-id = <0x01>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0xff 0x00 0x00 0x7f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| qcom,hap-swr-slave-reg { | |
| regulator-name = "hap-swr-slave-reg"; | |
| phandle = <0x62c>; | |
| }; | |
| effect_4 { | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,effect-id = <0x04>; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x514>; | |
| qcom,wf-pattern-data = <0x1f 0x00 0x00 0x3f 0x00 0x00 0x5f 0x00 0x00 0x7f 0x00 0x00 0x17f 0x00 0x00 0x15f 0x00 0x00 0x13f 0x00 0x00 0x11f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_8 { | |
| qcom,primitive-id = <0x08>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0xff 0x00 0x00 0x7f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| effect_2 { | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,effect-id = <0x02>; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x514>; | |
| qcom,wf-pattern-data = <0x1f 0x00 0x00 0x3f 0x00 0x00 0x5f 0x00 0x00 0x7f 0x00 0x00 0x17f 0x00 0x00 0x15f 0x00 0x00 0x13f 0x00 0x00 0x11f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| primitive_6 { | |
| qcom,primitive-id = <0x06>; | |
| qcom,wf-brake-pattern = [00 00 00]; | |
| qcom,wf-pattern-period-us = <0x16f8>; | |
| qcom,wf-vmax-mv = <0x960>; | |
| qcom,wf-pattern-data = <0xff 0x00 0x00 0x7f 0x00 0x00>; | |
| qcom,wf-auto-res-disable; | |
| }; | |
| }; | |
| bcl-soc { | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,msm-bcl-soc"; | |
| phandle = <0x5f0>; | |
| }; | |
| }; | |
| qcom,pm8550vs@6 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| status = "ok"; | |
| reg = <0x06 0x00>; | |
| phandle = <0x63f>; | |
| pinctrl@8800 { | |
| gpio-controller; | |
| compatible = "qcom,pm8550vs-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x8800>; | |
| phandle = <0x640>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| }; | |
| pm8550vs-g-temp-alarm@a00 { | |
| interrupts = <0x06 0x0a 0x00 0x03>; | |
| io-channels = <0x5e6 0x603>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0xa00>; | |
| phandle = <0x5f5>; | |
| io-channel-names = "thermal"; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@abf804c { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0xa7>; | |
| regulator-name = "video_cc_mvs0c_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xabf804c 0x04>; | |
| phandle = <0x2e3>; | |
| }; | |
| qcom,jpegenc0@ac2a000 { | |
| cam_hw_rd_mid = <0x00>; | |
| clock-names = "jpegenc_clk_src", "jpegenc_clk"; | |
| reg-names = "jpegenc_hw", "cam_camnoc"; | |
| reg-cam-base = <0x2a000 0x19000>; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x174 0x01>; | |
| clocks = <0x3b 0x5e 0x3b 0x5d>; | |
| clock-cntl-level = "nominal"; | |
| cam_hw_pid = <0x11 0x13>; | |
| compatible = "qcom,cam_jpeg_enc_780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "jpegenc_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "jpeg_enc0"; | |
| reg = <0xac2a000 0x1000 0xac19000 0xa080>; | |
| regulator-names = "gdsc"; | |
| phandle = <0x5ca>; | |
| nrt-device; | |
| shared-clks = <0x01 0x00>; | |
| clock-rates = <0x23c34600 0x00>; | |
| cam_hw_wr_mid = <0x01>; | |
| }; | |
| qcom,smp2p_sleepstate { | |
| interrupts = <0x00 0x00>; | |
| interrupt-parent = <0x6d>; | |
| compatible = "qcom,smp2p-sleepstate"; | |
| interrupt-names = "smp2p-sleepstate-in"; | |
| qcom,smem-states = <0x6c 0x00>; | |
| }; | |
| qcom,camera-flash1 { | |
| cell-index = <0x01>; | |
| torch-source = <0x61f 0x620>; | |
| switch-source = <0x625>; | |
| compatible = "qcom,camera-flash"; | |
| status = "ok"; | |
| phandle = <0x73a>; | |
| flash-source = <0x61b 0x61c>; | |
| }; | |
| qcom,csiphy4@acec000 { | |
| csi-vdd-1p2-supply = <0x31>; | |
| rgltr-max-voltage = <0x00 0x124f80 0xe1d48>; | |
| csi-vdd-0p9-supply = <0x30>; | |
| clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0xec000>; | |
| cell-index = <0x04>; | |
| interrupts = <0x00 0x7a 0x01>; | |
| clocks = <0x3b 0x1b 0x3b 0x36 0x3b 0x28 0x3b 0x27>; | |
| rgltr-load-current = <0x00 0x48a8 0x940c>; | |
| gdscr-supply = <0x2d9>; | |
| rgltr-cntrl-support; | |
| clock-cntl-level = "lowsvs", "nominal"; | |
| compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; | |
| rgltr-min-voltage = <0x00 0x124f80 0xd59f8>; | |
| src-clock-name = "csi4phytimer_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "CSIPHY4"; | |
| reg = <0xacec000 0x2000>; | |
| regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; | |
| phandle = <0x576>; | |
| shared-clks = <0x01 0x00 0x00 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; | |
| }; | |
| qcom,cnss-qca-converged { | |
| reg-names = "smmu_iova_ipa"; | |
| qcom,converged-dt; | |
| compatible = "qcom,cnss-qca-converged"; | |
| reg = <0xb0000000 0x10000>; | |
| phandle = <0x5e3>; | |
| qcom,wlan-sw-ctrl-gpio = <0x33 0x53 0x00>; | |
| chip_cfg@1 { | |
| qcom,sw-ctrl-gpio = <0x33 0x52 0x00>; | |
| qcom,vdd-wlan-aon-config = <0xef420 0xef420 0x00 0x00 0x01>; | |
| pinctrl-names = "wlan_en_active", "wlan_en_sleep"; | |
| qcom,vreg_pdc_map = "s4e", "rf", "l15B", "rf", "l3g", "rf", "s4g", "rf", "s6g", "rf", "s2g", "bb", "s5g", "bb"; | |
| qcom,icc-path-count = <0x02>; | |
| interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; | |
| qcom,vdd-wlan-config = <0xf4240 0xf4240 0x00 0x00 0x01>; | |
| pinctrl-0 = <0x5de>; | |
| interconnects = <0xed 0x2d 0xed 0x236 0x61 0x19 0x4b 0x200>; | |
| vdd-wlan-dig-supply = <0x316>; | |
| qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; | |
| qcom,wlan; | |
| vdd-wlan-aon-supply = <0x31d>; | |
| qcom,wlan-rc-num = <0x00>; | |
| vdd-wlan-rfa1-supply = <0x321>; | |
| supported-ids = <0x1107>; | |
| qcom,bt-en-gpio = <0x33 0x51 0x00>; | |
| vdd-wlan-rfa2-supply = <0x31f>; | |
| qcom,vdd-wlan-rfa1-config = <0x1cfde0 0x1cfde0 0x00 0x00 0x01>; | |
| qcom,bus-bw-cfg-count = <0x09>; | |
| qcom,vdd-wlan-io-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; | |
| vdd-wlan-io-supply = <0x30f>; | |
| qcom,vdd-wlan-rfa2-config = <0x149970 0x149970 0x00 0x00 0x01>; | |
| qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s4e.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s4e.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s4g.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s4g.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6g.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6g.v, dwnval: 1820}", "{class: wlan_pdc, ss: rf, res: s2g.m, enable: 0}", "{class: wlan_pdc, ss: rf, res: s2g.v, enable: 0}", "{class: wlan_pdc, ss: bb, res: pdc, enable: 1}", "{class: wlan_pdc, ss: bb, res: s2g.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2g.v, dwnval: 800}", "{class: wlan_pdc, ss: bb, res: s5g.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s5g.v, dwnval: 420}"; | |
| pinctrl-1 = <0x5df>; | |
| wlan-en-gpio = <0x33 0x50 0x00>; | |
| qcom,wlan-ramdump-dynamic = <0x780000>; | |
| mboxes = <0x02 0x00>; | |
| qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2g", "VDD095_PMU", "s5g", "VDD_PMU_AON_I", "s4e", "VDD095_PMU_BT", "s4e", "VDD09_PMU_RFA_I", "s4e", "VDD13_PMU_PCIE_I", "s4g", "VDD13_PMU_RFA_I", "s4g", "VDD19_PMU_PCIE_I", "s6g", "VDD19_PMU_RFA_I", "s6g"; | |
| vdd-wlan-supply = <0x320>; | |
| qcom,vdd-wlan-dig-config = <0xe7ef0 0xe7ef0 0x00 0x00 0x01>; | |
| cnss-enable-self-recovery; | |
| use-pm-domain; | |
| qcom,wlan-cbc-enabled; | |
| }; | |
| chip_cfg@0 { | |
| qcom,sw-ctrl-gpio = <0x33 0x52 0x00>; | |
| qcom,vdd-wlan-aon-config = <0xf7120 0xf7120 0x00 0x00 0x01>; | |
| pinctrl-names = "wlan_en_active", "wlan_en_sleep"; | |
| qcom,icc-path-count = <0x02>; | |
| interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; | |
| pinctrl-0 = <0x5de>; | |
| interconnects = <0xed 0x2e 0xed 0x236 0x61 0x19 0x4b 0x200>; | |
| vdd-wlan-dig-supply = <0x316>; | |
| qcom,rc-ep-short-channel; | |
| qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x186a0 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600 0x186a0 0x216600>; | |
| qcom,wlan; | |
| vdd-wlan-aon-supply = <0x31d>; | |
| qcom,wlan-rc-num = <0x01>; | |
| vdd-wlan-rfa1-supply = <0x321>; | |
| supported-ids = <0x1103>; | |
| qcom,bt-en-gpio = <0x33 0x51 0x00>; | |
| vdd-wlan-rfa2-supply = <0x31f>; | |
| qcom,vdd-wlan-rfa1-config = <0x1cfde0 0x1cfde0 0x00 0x00 0x01>; | |
| qcom,bus-bw-cfg-count = <0x0a>; | |
| qcom,vdd-wlan-io-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; | |
| vdd-wlan-io-supply = <0x30f>; | |
| qcom,vdd-wlan-rfa2-config = <0x149970 0x149970 0x00 0x00 0x01>; | |
| qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s4e.v, upval: 966}", "{class: wlan_pdc, ss: rf, res: s4e.v, dwnval: 615}", "{class: wlan_pdc, ss: rf, res: s4g.v, upval: 1350}", "{class: wlan_pdc, ss: rf, res: s4g.v, dwnval: 945}", "{class: wlan_pdc, ss: rf, res: s6g.v, upval: 1900}", "{class: wlan_pdc, ss: rf, res: s6g.v, dwnval: 1825}", "{class: wlan_pdc, ss: rf, res: s2g.m, enable: 1}", "{class: wlan_pdc, ss: rf, res: s2g.v, enable: 1}", "{class: wlan_pdc, ss: rf, res: s2g.v, upval: 1012}", "{class: wlan_pdc, ss: rf, res: s2g.v, dwnval: 800}", "{class: wlan_pdc, ss: bb, res: pdc, enable: 0}"; | |
| pinctrl-1 = <0x5df>; | |
| qcom,vreg_ol_cpr = "s2g"; | |
| wlan-en-gpio = <0x33 0x50 0x00>; | |
| qcom,wlan-ramdump-dynamic = <0x420000>; | |
| mboxes = <0x02 0x00>; | |
| qcom,vdd-wlan-dig-config = <0xebd70 0xebd70 0x00 0x00 0x01>; | |
| cnss-enable-self-recovery; | |
| use-pm-domain; | |
| qcom,wlan-cbc-enabled; | |
| }; | |
| }; | |
| wsa_core_clk { | |
| qcom,codec-ext-clk-src = <0x03>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| status = "disabled"; | |
| phandle = <0x735>; | |
| qcom,codec-lpass-clk-id = <0x309>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| interconnect@1500000 { | |
| #interconnect-cells = <0x01>; | |
| qcom,bcm-voters = <0x40>; | |
| compatible = "qcom,kalama-cnoc_main"; | |
| reg = <0x1500000 0x13080>; | |
| phandle = <0x355>; | |
| qcom,bcm-voter-names = "hlos"; | |
| }; | |
| qcom,gdsc@abf80cc { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2ba>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x45 0xa7>; | |
| regulator-name = "video_cc_mvs1_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xabf80cc 0x04>; | |
| phandle = <0x2bb>; | |
| }; | |
| syscon@3d9958c { | |
| compatible = "syscon"; | |
| reg = <0x3d9958c 0x04>; | |
| phandle = <0x2e1>; | |
| }; | |
| qcom,gdsc@3d9905c { | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2e2>; | |
| qcom,retain-regs; | |
| domain-addr = <0x2de>; | |
| regulator-name = "gpu_cc_gx_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| qcom,reset-aon-logic; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x3d9905c 0x04>; | |
| sw-reset = <0x2df 0x2e0 0x2e1>; | |
| phandle = <0x505>; | |
| }; | |
| disp_rdump_region@b8000000 { | |
| label = "disp_rdump_region"; | |
| reg = <0xb8000000 0x800000>; | |
| phandle = <0x7b1>; | |
| }; | |
| tpdm@10c23000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4b>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-ufs"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10c23000 0x1000>; | |
| phandle = <0x418>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10f>; | |
| phandle = <0x175>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| bt-qca-converged { | |
| qcom,converged-dt; | |
| compatible = "qcom,bt-qca-converged"; | |
| phandle = <0x5cd>; | |
| qcom,wlan-sw-ctrl-gpio = <0x33 0x53 0x00>; | |
| bt_kiwi { | |
| pinctrl-names = "default"; | |
| qcom,bt-vdd-rfa1-config = <0x149970 0x149970 0x00 0x01>; | |
| pinctrl-0 = <0x5cc>; | |
| qcom,bt-vdd18-aon-supply = <0x30f>; | |
| qcom,bt-vdd-rfa2-config = <0x1cfde0 0x1cfde0 0x00 0x01>; | |
| qcom,bt-vdd-dig-supply = <0x316>; | |
| qcom,bt-vdd-aon-supply = <0x316>; | |
| qcom,bt-vdd-rfaOp8-supply = <0x316>; | |
| qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s4e.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s4e.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s4g.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s4g.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6g.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6g.v, dwnval: 1820}"; | |
| qcom,bt-reset-gpio = <0x33 0x51 0x00>; | |
| compatible = "qcom,kiwi"; | |
| qcom,bt-vdd-rfa1-supply = <0x31f>; | |
| qcom,bt-vdd18-aon-config = <0x1b7740 0x1b7740 0x00 0x01>; | |
| qcom,wl-reset-gpio = <0x33 0x50 0x00>; | |
| qcom,bt-vdd-rfa2-supply = <0x321>; | |
| qcom,bt-vdd-dig-config = <0xe7ef0 0xe7ef0 0x00 0x01>; | |
| mboxes = <0x02 0x00>; | |
| qcom,bt-sw-ctrl-gpio = <0x33 0x52 0x00>; | |
| qcom,bt-vdd-aon-config = <0xe7ef0 0xe7ef0 0x00 0x01>; | |
| qcom,bt-vdd-rfaOp8-config = <0xe7ef0 0xe7ef0 0x00 0x01>; | |
| }; | |
| bt_qca6490 { | |
| pinctrl-names = "default"; | |
| qcom,bt-vdd-io-config = <0x1b7740 0x1b7740 0x00 0x01>; | |
| qcom,bt-vdd-rfa1-config = <0x1cfde0 0x1cfde0 0x00 0x01>; | |
| pinctrl-0 = <0x5cc>; | |
| qcom,bt-vdd-rfa2-config = <0x149970 0x149970 0x00 0x01>; | |
| qcom,bt-vdd-dig-supply = <0x316>; | |
| qcom,bt-vdd-aon-supply = <0x316>; | |
| qcom,bt-vdd-rfaOp8-supply = <0x316>; | |
| qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s4e.v, upval: 966}", "{class: wlan_pdc, ss: rf, res: s4e.v, dwnval: 615}", "{class: wlan_pdc, ss: rf, res: s4g.v, upval: 1350}", "{class: wlan_pdc, ss: rf, res: s4g.v, dwnval: 945}", "{class: wlan_pdc, ss: rf, res: s6g.v, upval: 1900}", "{class: wlan_pdc, ss: rf, res: s6g.v, dwnval: 1825}", "{class: wlan_pdc, ss: rf, res: s2g.m, enable: 1}", "{class: wlan_pdc, ss: rf, res: s2g.v, enable: 1}", "{class: wlan_pdc, ss: rf, res: s2g.v, upval: 1012}", "{class: wlan_pdc, ss: rf, res: s2g.v, dwnval: 515}"; | |
| qcom,bt-reset-gpio = <0x33 0x51 0x00>; | |
| compatible = "qcom,qca6490"; | |
| qcom,bt-vdd-io-supply = <0x30f>; | |
| qcom,bt-vdd-rfa1-supply = <0x321>; | |
| qcom,wl-reset-gpio = <0x33 0x50 0x00>; | |
| qcom,bt-vdd-rfa2-supply = <0x31f>; | |
| qcom,bt-vdd-dig-config = <0xebd70 0xebd70 0x00 0x01>; | |
| mboxes = <0x02 0x00>; | |
| qcom,bt-sw-ctrl-gpio = <0x33 0x52 0x00>; | |
| qcom,bt-vdd-aon-config = <0xebd70 0xebd70 0x00 0x01>; | |
| qcom,bt-vdd-rfaOp8-config = <0xebd70 0xebd70 0x00 0x01>; | |
| }; | |
| }; | |
| ete7 { | |
| atid = <0x08>; | |
| qcom,skip-power-up; | |
| cpu = <0x1f>; | |
| coresight-name = "coresight-ete7"; | |
| phy-cpu = <0x07>; | |
| compatible = "arm,embedded-trace-extension"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1e7>; | |
| phandle = <0x1f0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10d01000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-shrm"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10d01000 0x1000>; | |
| phandle = <0x159>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xfa>; | |
| phandle = <0x14f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| msm_cdc_pinctrl@32 { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x3c5>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x3c6>; | |
| phandle = <0x66d>; | |
| }; | |
| qcom,qmp-aop { | |
| qcom,qmp = <0x4e>; | |
| #mbox-cells = <0x01>; | |
| label = "aop"; | |
| compatible = "qcom,qmp-mbox"; | |
| phandle = <0x02>; | |
| }; | |
| qcom,bwmon-llcc@240B6300 { | |
| qcom,second-vote = <0x9e>; | |
| reg-names = "base", "global_base"; | |
| interrupts = <0x00 0x245 0x04>; | |
| compatible = "qcom,bwmon4"; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,mport = <0x00>; | |
| qcom,count-unit = <0x10000>; | |
| reg = <0x240b6400 0x300 0x240b6300 0x200>; | |
| phandle = <0x3f0>; | |
| qcom,target-dev = <0x98>; | |
| }; | |
| qcom,rmtfs_sharedmem@0 { | |
| reg-names = "rmtfs"; | |
| qcom,client-id = <0x01>; | |
| compatible = "qcom,sharedmem-uio"; | |
| reg = <0x00 0x280000>; | |
| }; | |
| qcom,mmrm-test { | |
| clock-names = "cam_cc_ife_0_clk_src", "cam_cc_ife_1_clk_src", "cam_cc_ife_2_clk_src", "cam_cc_csid_clk_src", "cam_cc_sfe_0_clk_src", "cam_cc_sfe_1_clk_src", "cam_cc_ipe_nps_clk_src", "cam_cc_bps_clk_src", "cam_cc_ife_lite_clk_src", "cam_cc_jpeg_clk_src", "cam_cc_camnoc_axi_clk_src", "cam_cc_ife_lite_csid_clk_src", "cam_cc_icp_clk_src", "cam_cc_cphy_rx_clk_src", "cam_cc_csi0phytimer_clk_src", "cam_cc_csi1phytimer_clk_src", "cam_cc_csi2phytimer_clk_src", "cam_cc_csi3phytimer_clk_src", "cam_cc_csi4phytimer_clk_src", "cam_cc_csi5phytimer_clk_src", "cam_cc_csi6phytimer_clk_src", "cam_cc_csi7phytimer_clk_src", "cam_cc_cci_0_clk_src", "cam_cc_cci_1_clk_src", "cam_cc_cci_2_clk_src", "cam_cc_slow_ahb_clk_src", "cam_cc_fast_ahb_clk_src", "cam_cc_cre_clk_src", "video_cc_mvs1_clk_src", "disp_cc_mdss_mdp_clk_src", "disp_cc_mdss_dptx0_link_clk_src", "video_cc_mvs0_clk_src"; | |
| clocks = <0x3b 0x42 0x3b 0x47 0x3b 0x4c 0x3b 0x30 0x3b 0x8f 0x3b 0x92 0x3b 0x58 0x3b 0x02 0x3b 0x52 0x3b 0x5e 0x3b 0x05 0x3b 0x55 0x3b 0x40 0x3b 0x1b 0x3b 0x20 0x3b 0x22 0x3b 0x24 0x3b 0x26 0x3b 0x28 0x3b 0x2a 0x3b 0x2c 0x3b 0x2e 0x3b 0x09 0x3b 0x0b 0x3b 0x0d 0x3b 0x96 0x3b 0x3c 0x3b 0x1e 0x5f 0x08 0x3c 0x3e 0x3c 0x10 0x5f 0x03>; | |
| compatible = "qcom,msm-mmrm-test", "qcom,kalama-mmrm-test"; | |
| clock_rates = <0x01 0x42 0x19bfcc00 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x47 0x19bfcc00 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x4c 0x19bfcc00 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x30 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x01 0x8f 0x19bfcc00 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x92 0x15b23300 0x1dcd6500 0x23c34600 0x29b92700 0x29b92700 0x01 0x58 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x01 0x5e 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x05 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x01 0x40 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x1b 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x01 0x20 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x22 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x24 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x26 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x28 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x2a 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x2c 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x2e 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x09 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x96 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x3c 0x5f5e100 0xbebc200 0x11e1a300 0x17d78400 0x17d78400 0x01 0x1e 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x02 0x08 0x3e95ba80 0x50775d80 0x59682f00 0x62590080 0x62590080 0x03 0x3e 0xbebc200 0x135f1b40 0x165a0bc0 0x1dcd6500 0x1dcd6500 0x03 0x10 0x41eb0 0x41eb0 0x83d60 0xc5c10 0xc5c10 0x04 0x03 0x2aea5400 0x3c706980 0x41722680 0x4f64b500 0x4f64b500>; | |
| status = "disable"; | |
| phandle = <0x5d1>; | |
| }; | |
| wsa_spkr_en2_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x69e>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x69f>; | |
| status = "disabled"; | |
| phandle = <0x66a>; | |
| }; | |
| va_core_clk { | |
| qcom,codec-ext-clk-src = <0x02>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x662>; | |
| qcom,codec-lpass-clk-id = <0x307>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| cti@10b42000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-lpass_ssc_sdc_cti"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10b42000 0x1000>; | |
| phandle = <0x473>; | |
| }; | |
| tpdm@10c20000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x61>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-sdcc-2"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10c20000 0x1000>; | |
| phandle = <0x426>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x120>; | |
| phandle = <0x180>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cpu-pmu { | |
| interrupts = <0x01 0x07 0x04>; | |
| compatible = "arm,armv8-pmuv3"; | |
| phandle = <0x354>; | |
| }; | |
| funnel@10984000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base-dummy", "funnel-base-real"; | |
| qcom,duplicate-funnel; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-turing_dup"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10984000 0x1000 0x10983000 0x1000>; | |
| phandle = <0x43e>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x15b>; | |
| phandle = <0x110>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x15c>; | |
| phandle = <0x15f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cam-i3c-id-table { | |
| i3c-actuator-id-table; | |
| i3c-eeprom-id-table; | |
| i3c-sensor-id-table = <0x1b0 0x766>; | |
| status = "disabled"; | |
| i3c-ois-id-table; | |
| }; | |
| qrtr-gunyah-oemvm { | |
| qcom,master; | |
| peer-name = <0x04>; | |
| gunyah-label = <0x08>; | |
| compatible = "qcom,qrtr-gunyah"; | |
| }; | |
| power-controller@c300000 { | |
| interrupts = <0x00 0x00 0x01>; | |
| #clock-cells = <0x00>; | |
| interrupt-parent = <0x4f>; | |
| #power-domain-cells = <0x01>; | |
| compatible = "qcom,kalama-aoss-qmp"; | |
| reg = <0xc300000 0x400>; | |
| phandle = <0x4e>; | |
| mboxes = <0x4f 0x00 0x00>; | |
| }; | |
| cti@10802000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-modem_tp_cti"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x10802000 0x1000>; | |
| phandle = <0x482>; | |
| }; | |
| ufs_phy_rx_symbol_0_clk { | |
| clock-output-names = "ufs_phy_rx_symbol_0_clk"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x58>; | |
| }; | |
| cti@12020000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-cpu1"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x12020000 0x1000>; | |
| phandle = <0x487>; | |
| trig-conns { | |
| arm,trig-out-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| cpu = <0x19>; | |
| arm,trig-in-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| }; | |
| }; | |
| csr@10b11000 { | |
| qcom,blk-size = <0x01>; | |
| qcom,msr-support; | |
| clock-names = "apb_pclk"; | |
| reg-names = "csr-base", "msr-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-swao-csr"; | |
| qcom,timestamp-support; | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0x10b11000 0x1000 0x10b110f8 0x50>; | |
| phandle = <0x45d>; | |
| }; | |
| tpdm@109d0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-qm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x109d0000 0x1000>; | |
| phandle = <0x40d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x104>; | |
| phandle = <0x1a7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ufshc@1d84000 { | |
| iommus = <0x4c 0x60 0x00>; | |
| vcc-max-microamp = <0x13d620>; | |
| #reset-cells = <0x01>; | |
| qcom,vccq-shutdown-supply = <0x322>; | |
| freq-table-hz = <0x47868c0 0x11e1a300 0x00 0x00 0x00 0x00 0x47868c0 0x11e1a300 0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,ufs-bus-bw,name = "ufshc_mem"; | |
| dma-coherent; | |
| interconnect-names = "ufs-ddr", "cpu-ufs"; | |
| phy-names = "ufsphy"; | |
| clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; | |
| interconnects = <0x66 0x33 0x4b 0x200 0x61 0x02 0x62 0x225>; | |
| reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; | |
| qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", "HS_RA_G5_L2", "HS_RB_G5_L2", "MAX"; | |
| lanes-per-direction = <0x02>; | |
| qcom,vddp-ref-clk-max-microamp = <0x64>; | |
| resets = <0x45 0x18>; | |
| interrupts = <0x00 0x109 0x04>; | |
| clocks = <0x45 0x8a 0x45 0x01 0x45 0x89 0x45 0x99 0x45 0x8d 0x46 0x04 0x45 0x97 0x45 0x93 0x45 0x95>; | |
| dev-ref-clk-freq = <0x00>; | |
| shared-ice-cfg = <0x67>; | |
| qcom,vccq-parent-max-microamp = <0x33450>; | |
| qcom,bypass-pbl-rst-wa; | |
| qcom,vccq-parent-supply = <0x31f>; | |
| reset-gpios = <0x33 0xd2 0x01>; | |
| qcom,dynamic-irq-affinity; | |
| qcom,vccq-shutdown-max-microamp = <0x124f80>; | |
| compatible = "qcom,ufshc"; | |
| qcom,ufs-bus-bw,num-paths = <0x02>; | |
| qcom,ufs-bus-bw,num-cases = <0x1e>; | |
| status = "ok"; | |
| phys = <0x65>; | |
| vdd-hba-supply = <0x2dc>; | |
| reg = <0x1d84000 0x3000 0x1d88000 0x8000 0x1d90000 0x9000>; | |
| phandle = <0x64>; | |
| vccq-max-microamp = <0x124f80>; | |
| reset-names = "rst"; | |
| vccq-supply = <0x322>; | |
| qcom,vccq-lpm-uV = <0x120160>; | |
| vcc-supply = <0x311>; | |
| qcom,ufs-bus-bw,vectors-KBps = <0x00 0x00 0x00 0x00 0x39a 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x7340 0x00 0x3e8 0x00 0x1f334 0x00 0x3e8 0x00 0x3e667 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x3e667 0x00 0x3e8 0x00 0x7cccd 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x00 0x2c7b80 0x00 0x64000 0x00 0x247ae 0x00 0x3e8 0x00 0x48ccd 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x48ccd 0x00 0x3e8 0x00 0x9199a 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x64000 0x2c7b80 0x00 0x64000 0x64000 0x591000 0x00 0xc8000 0x00 0x591000 0x00 0xc8000 0x00 0x74a000 0x00 0xc8000 0x00>; | |
| qcom,vddp-ref-clk-supply = <0x324>; | |
| qcom,iommu-dma = "fastmap"; | |
| qos0 { | |
| perf; | |
| vote = <0x2c>; | |
| }; | |
| qos1 { | |
| vote = <0x2c>; | |
| }; | |
| }; | |
| syscon@3d99358 { | |
| compatible = "syscon"; | |
| reg = <0x3d99358 0x04>; | |
| phandle = <0x2e0>; | |
| }; | |
| qcom,smp2p-adsp { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x03 0x02 0x01>; | |
| interrupt-parent = <0x4f>; | |
| qcom,remote-pid = <0x02>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x4f 0x03 0x02>; | |
| qcom,smem = <0x1bb 0x1ad>; | |
| qcom,smp2p-rdbg2-out { | |
| qcom,entry-name = "rdbg"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x2d2>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x75>; | |
| interrupt-controller; | |
| }; | |
| qcom,sleepstate-in { | |
| qcom,entry-name = "sleepstate_see"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x6d>; | |
| interrupt-controller; | |
| }; | |
| sleepstate-out { | |
| qcom,entry-name = "sleepstate"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x6c>; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x76>; | |
| }; | |
| qcom,smp2p-rdbg2-in { | |
| qcom,entry-name = "rdbg"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x2d3>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| cti@10cc5000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-tmess_cti_3"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10cc5000 0x1000>; | |
| phandle = <0x47f>; | |
| }; | |
| tpdm@10d41000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x63>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-llcc-1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10d41000 0x1000>; | |
| phandle = <0x42d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x127>; | |
| phandle = <0x12b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,smmu_sde_sec_cb { | |
| iommus = <0x4c 0x1c01 0x00>; | |
| compatible = "qcom,smmu_sde_sec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x7a2>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| cti@10845000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-lpass_dl_cti"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x10845000 0x1000>; | |
| phandle = <0x464>; | |
| }; | |
| usb_audio_qmi_dev { | |
| iommus = <0x4c 0x100b 0x00>; | |
| qcom,usb-audio-intr-num = <0x02>; | |
| compatible = "qcom,usb-audio-qmi-dev"; | |
| qcom,usb-audio-stream-id = <0x0b>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| qcom,msm-adsprpc-mem { | |
| restrict-access; | |
| memory-region = <0x6f>; | |
| compatible = "qcom,msm-adsprpc-mem-region"; | |
| }; | |
| qcom,gdsc@adf0004 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x06>; | |
| regulator-name = "cam_cc_bps_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xadf0004 0x04>; | |
| phandle = <0x4fa>; | |
| }; | |
| qcom,msm_hdcp { | |
| compatible = "qcom,msm-hdcp"; | |
| phandle = <0x7a1>; | |
| }; | |
| tpdm@10ac0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x61>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-dl-north"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10ac0000 0x1000>; | |
| phandle = <0x41d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x115>; | |
| phandle = <0x181>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cpu-pause { | |
| compatible = "qcom,thermal-pause"; | |
| cpu-6-7-pause { | |
| qcom,cpus = <0x1e 0x1f>; | |
| qcom,cdev-alias = "thermal-pause-C0"; | |
| phandle = <0x4d8>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu-3-4-5-pause { | |
| qcom,cpus = <0x1b 0x1c 0x1d>; | |
| qcom,cdev-alias = "thermal-pause-38"; | |
| phandle = <0x4d7>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu3 { | |
| qcom,cpus = <0x1b>; | |
| qcom,cdev-alias = "pause-cpu3"; | |
| }; | |
| cpu6-pause { | |
| qcom,cpus = <0x1e>; | |
| qcom,cdev-alias = "thermal-pause-40"; | |
| phandle = <0xb4>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu1 { | |
| qcom,cpus = <0x19>; | |
| qcom,cdev-alias = "pause-cpu1"; | |
| }; | |
| cpu3-pause { | |
| qcom,cpus = <0x1b>; | |
| qcom,cdev-alias = "thermal-pause-8"; | |
| phandle = <0xa2>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu7-pause { | |
| qcom,cpus = <0x1f>; | |
| qcom,cdev-alias = "thermal-pause-80"; | |
| phandle = <0xba>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu6 { | |
| qcom,cpus = <0x1e>; | |
| qcom,cdev-alias = "pause-cpu6"; | |
| }; | |
| pause-cpu4 { | |
| qcom,cpus = <0x1c>; | |
| qcom,cdev-alias = "pause-cpu4"; | |
| }; | |
| cpu4-pause { | |
| qcom,cpus = <0x1c>; | |
| qcom,cdev-alias = "thermal-pause-10"; | |
| phandle = <0xa8>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu2 { | |
| qcom,cpus = <0x1a>; | |
| qcom,cdev-alias = "pause-cpu2"; | |
| }; | |
| cpu1-pause { | |
| qcom,cpus = <0x19>; | |
| qcom,cdev-alias = "thermal-pause-2"; | |
| phandle = <0xc3>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu5-pause { | |
| qcom,cpus = <0x1d>; | |
| qcom,cdev-alias = "thermal-pause-20"; | |
| phandle = <0xae>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| apc1-pause { | |
| qcom,cpus = <0x1b 0x1c 0x1d 0x1e 0x1f>; | |
| qcom,cdev-alias = "thermal-pause-F8"; | |
| phandle = <0x4d6>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu7 { | |
| qcom,cpus = <0x1f>; | |
| qcom,cdev-alias = "pause-cpu7"; | |
| }; | |
| pause-cpu5 { | |
| qcom,cpus = <0x1d>; | |
| qcom,cdev-alias = "pause-cpu5"; | |
| }; | |
| cpu2-pause { | |
| qcom,cpus = <0x1a>; | |
| qcom,cdev-alias = "thermal-pause-4"; | |
| phandle = <0xc7>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_2_out { | |
| qcom,smem-state-names = "rdbg-smp2p-out"; | |
| compatible = "qcom,smp2p-interrupt-rdbg-2-out"; | |
| qcom,smem-states = <0x2d2 0x00>; | |
| }; | |
| tpdm@10c60000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-mdss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10c60000 0x1000>; | |
| phandle = <0x16d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xfc>; | |
| phandle = <0x140>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| remoteproc-spss@1880000 { | |
| interconnect-names = "crypto_ddr"; | |
| clock-names = "xo"; | |
| interconnects = <0x4a 0x27 0x4b 0x200>; | |
| reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", "rmb_err", "rmb_general_purpose", "rmb_err_spare2"; | |
| qcom,spss-scsr-bits = <0x18 0x19>; | |
| qcom,qmp = <0x4e>; | |
| memory-region = <0x4d>; | |
| interrupts = <0x00 0x160 0x01>; | |
| clocks = <0x46 0x00>; | |
| qcom,signal-aop; | |
| cx-supply = <0x27>; | |
| qcom,extra-size = <0x1000>; | |
| compatible = "qcom,kalama-spss-pas"; | |
| ranges; | |
| status = "ok"; | |
| reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1881100 0x04 0x1882014 0x04>; | |
| phandle = <0x50>; | |
| qcom,proxy-clock-names = "xo"; | |
| cx-uV-uA = <0x180 0x186a0>; | |
| glink-edge { | |
| reg-names = "qcom,spss-addr", "qcom,spss-size"; | |
| interrupts = <0x10 0x00 0x01>; | |
| qcom,glink-label = "spss"; | |
| interrupt-parent = <0x4f>; | |
| label = "spss"; | |
| qcom,remote-pid = <0x08>; | |
| reg = <0x1885008 0x08 0x1885010 0x04>; | |
| mboxes = <0x4f 0x10 0x00>; | |
| mbox-names = "spss_spss"; | |
| }; | |
| }; | |
| qcom,spmi@c432000 { | |
| #address-cells = <0x02>; | |
| depends-on-supply = <0xe6>; | |
| reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; | |
| qcom,channel = <0x00>; | |
| cell-index = <0x00>; | |
| #size-cells = <0x00>; | |
| interrupts-extended = <0x51 0x03 0x04>; | |
| compatible = "qcom,spmi-pmic-arb"; | |
| #interrupt-cells = <0x04>; | |
| qcom,bus-id = <0x01>; | |
| interrupt-names = "periph_irq"; | |
| reg = <0xc432000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4d0000 0x10000>; | |
| phandle = <0xe7>; | |
| qcom,ee = <0x00>; | |
| interrupt-controller; | |
| }; | |
| funnel@10045000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-qdss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10045000 0x1000>; | |
| phandle = <0x453>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1c4>; | |
| phandle = <0x1bc>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x1c3>; | |
| phandle = <0x1c2>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1c5>; | |
| phandle = <0x1ce>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@1082c000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-gcc"; | |
| compatible = "arm,primecell"; | |
| reg = <0x1082c000 0x1000>; | |
| phandle = <0x40e>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x105>; | |
| phandle = <0x1af>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10cc2000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-tmess_cti_0"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10cc2000 0x1000>; | |
| phandle = <0x47c>; | |
| }; | |
| qcom,pcie@1c00000 { | |
| pinctrl-names = "default", "sleep"; | |
| qcom,vreg-0p9-voltage-level = <0xd6d80 0xd6d80 0x13c04>; | |
| #address-cells = <0x03>; | |
| gdsc-core-vdd-supply = <0x2c2>; | |
| dma-coherent; | |
| clock-suppressible = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| interconnect-names = "icc_path"; | |
| qcom,config-recovery; | |
| qcom,drv-l1ss-timeout-us = <0x1388>; | |
| pinctrl-0 = <0x2be 0x2bf 0x2c0>; | |
| clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", "pcie_aux_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_clkref_en", "pcie_slv_q2a_axi_clk", "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; | |
| interconnects = <0xed 0x2d 0x4b 0x200>; | |
| reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; | |
| qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>; | |
| qcom,phy-power-down-offset = <0x240>; | |
| qcom,pcie-phy-ver = <0x66>; | |
| cell-index = <0x00>; | |
| resets = <0x45 0x03 0x45 0x06>; | |
| qcom,dbi-debug-reg = <0x104 0x110 0x80 0x1f4 0x730 0x734 0x738 0x73c>; | |
| qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x100 0x100 0x5f5e100>; | |
| interrupts = <0x00 0x8c 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04>; | |
| clocks = <0x45 0x28 0x46 0x00 0x45 0x22 0x45 0x24 0x45 0x25 0x45 0x2a 0x5e 0x00 0x45 0x2b 0x45 0x26 0x45 0x0e 0x45 0x00 0x45 0x29 0x55>; | |
| qcom,smmu-sid-base = <0x1400>; | |
| vreg-1p2-supply = <0x31>; | |
| #size-cells = <0x02>; | |
| qcom,boot-option = <0x01>; | |
| clock-frequency = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00 0x00 0x00 0x00>; | |
| gdsc-phy-vdd-supply = <0x2c3>; | |
| vreg-mx-supply = <0x2a>; | |
| qcom,l1-2-th-scale = <0x02>; | |
| qcom,phy-status-offset = <0x214>; | |
| wake-gpio = <0x33 0x60 0x00>; | |
| qcom,phy-debug-reg = <0x1cc 0x1d0 0x1d4 0x1d8 0x1dc 0x1e0 0x1e4 0x1f8 0xed0 0x16d0 0xedc 0x16dc 0x11e0 0x19e0 0xa00 0x1200 0xa04 0x1204 0xa08 0x1208 0xa0c 0x120c 0xa10 0x1210 0xa14 0x1214 0xa18 0x1218 0xc20 0x1420 0x214 0x218 0x21c 0x220 0x224 0x228 0x22c 0x230 0x234 0x238 0x23c 0x600 0x604>; | |
| vreg-0p9-supply = <0x30>; | |
| qcom,drv-name = "lpass"; | |
| compatible = "qcom,pci-msm"; | |
| ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0x3d00000>; | |
| msi-map = <0x00 0x2fe 0x1400 0x01 0x100 0x2fe 0x1401 0x01>; | |
| pinctrl-1 = <0x2be 0x2c1 0x2c0>; | |
| interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; | |
| qcom,num-parf-testbus-sel = <0xb9>; | |
| reg = <0x1c00000 0x3000 0x1c06000 0x2000 0x60000000 0xf1d 0x60000f20 0xa8 0x60001000 0x1000 0x60100000 0x100000>; | |
| linux,pci-domain = <0x00>; | |
| phandle = <0x4c6>; | |
| qcom,aux-clk-freq = <0x14>; | |
| iommu-map = <0x00 0x4c 0x1400 0x01 0x100 0x4c 0x1401 0x01>; | |
| reset-names = "pcie_0_core_reset", "pcie_0_phy_reset"; | |
| qcom,l1-2-th-value = <0x96>; | |
| qcom,ep-latency = <0x0a>; | |
| vreg-cx-supply = <0x27>; | |
| perst-gpio = <0x33 0x5e 0x00>; | |
| qcom,vreg-1p2-voltage-level = <0x124f80 0x124f80 0x4718>; | |
| qcom,vreg-cx-voltage-level = <0xffff 0x100 0x00>; | |
| qcom,phy-status-bit = <0x06>; | |
| qcom,slv-addr-space-size = <0x4000000>; | |
| qcom,vreg-mx-voltage-level = <0xffff 0x100 0x00>; | |
| qcom,phy-sequence = <0x240 0x03 0x00 0xc0 0x01 0x00 0xcc 0x62 0x00 0xd0 0x02 0x00 0x60 0xf8 0x00 0x64 0x01 0x00 0x00 0x93 0x00 0x04 0x01 0x00 0xe0 0x90 0x00 0xe4 0x82 0x00 0xf4 0x07 0x00 0x70 0x02 0x00 0x10 0x02 0x00 0x74 0x16 0x00 0x14 0x16 0x00 0x78 0x36 0x00 0x18 0x36 0x00 0x110 0x08 0x00 0xbc 0x0a 0x00 0x120 0x40 0x00 0x80 0x0a 0x00 0x84 0x1a 0x00 0x20 0x14 0x00 0x24 0x34 0x00 0x88 0x41 0x00 0x28 0x34 0x00 0x90 0xab 0x00 0x94 0xaa 0x00 0x98 0x01 0x00 0x30 0x55 0x00 0x34 0x55 0x00 0x38 0x01 0x00 0x140 0x14 0x00 0x164 0x34 0x00 0x3c 0x01 0x00 0x1c 0x04 0x00 0x174 0x16 0x00 0x1bc 0x0f 0x00 0x170 0xa0 0x00 0x11a4 0x38 0x00 0x10dc 0x11 0x00 0x1160 0xbf 0x00 0x1164 0xbf 0x00 0x1168 0xb7 0x00 0x116c 0xea 0x00 0x115c 0x3f 0x00 0x1174 0x5c 0x00 0x1178 0x9c 0x00 0x117c 0x1a 0x00 0x1180 0x8f 0x00 0x1170 0xdc 0x00 0x1188 0x94 0x00 0x118c 0x5b 0x00 0x1190 0x1a 0x00 0x1194 0x89 0x00 0x10cc 0x00 0x00 0x1008 0x09 0x00 0x1014 0x05 0x00 0x104c 0x08 0x00 0x1050 0x08 0x00 0x10d8 0x0f 0x00 0x1118 0x1c 0x00 0x10f8 0x07 0x00 0x11f8 0x08 0x00 0xe84 0x15 0x00 0xe90 0x3f 0x00 0xee4 0x02 0x00 0xe40 0x06 0x00 0xe3c 0x18 0x00 0x19a4 0x38 0x00 0x18dc 0x11 0x00 0x1960 0xbf 0x00 0x1964 0xbf 0x00 0x1968 0xb7 0x00 0x196c 0xea 0x00 0x195c 0x3f 0x00 0x1974 0x5c 0x00 0x1978 0x9c 0x00 0x197c 0x1a 0x00 0x1980 0x8f 0x00 0x1970 0xdc 0x00 0x1988 0x94 0x00 0x198c 0x5b 0x00 0x1990 0x1a 0x00 0x1994 0x89 0x00 0x18cc 0x00 0x00 0x1808 0x09 0x00 0x1814 0x05 0x00 0x184c 0x08 0x00 0x1850 0x08 0x00 0x18d8 0x0f 0x00 0x1918 0x1c 0x00 0x18f8 0x07 0x00 0x19f8 0x08 0x00 0x1684 0x15 0x00 0x1690 0x3f 0x00 0x16e4 0x02 0x00 0x1640 0x06 0x00 0x163c 0x18 0x00 0x2dc 0x05 0x00 0x388 0x77 0x00 0x398 0x0b 0x00 0x6a4 0x1e 0x00 0x3e0 0x0f 0x00 0x60c 0x1d 0x00 0x614 0x07 0x00 0x620 0xc1 0x00 0x694 0x00 0x00 0x3d0 0x8c 0x00 0x368 0x0f 0x00 0x1424 0x00 0x00 0x1428 0x00 0x00 0x200 0x00 0x00 0x244 0x03 0x00>; | |
| pcie0_rp { | |
| #address-cells = <0x05>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4c7>; | |
| cnss_pci0 { | |
| #address-cells = <0x01>; | |
| memory-region = <0x5e1>; | |
| #size-cells = <0x01>; | |
| qcom,iommu-group = <0x5e0>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x5e4>; | |
| cnss_pci_iommu_group0 { | |
| qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; | |
| phandle = <0x5e0>; | |
| qcom,iommu-msi-size = <0x1000>; | |
| qcom,iommu-pagetable = "coherent"; | |
| qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,csid0@acb7000 { | |
| clock-control-debugfs = "true"; | |
| clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; | |
| reg-names = "csid", "csid_top"; | |
| reg-cam-base = "", "\vp", "", "\v`"; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x259 0x01>; | |
| clocks = <0x3b 0x30 0x3b 0x2f 0x3b 0x31>; | |
| rt-wrapper-base = <0x62000>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| compatible = "qcom,csid780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "csid_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "csid0"; | |
| reg = <0xacb7000 0xd00 0xacb6000 0x1000>; | |
| regulator-names = "gdsc"; | |
| phandle = <0x5ba>; | |
| shared-clks = <0x01 0x00 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; | |
| }; | |
| qcom,guestvm_loader@f8400000 { | |
| memory-region = <0x86>; | |
| qcom,pas-id = <0x22>; | |
| compatible = "qcom,guestvm-loader"; | |
| qcom,vmid = <0x31>; | |
| qcom,firmware-name = "oemvm"; | |
| }; | |
| tpda@10803000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x40>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpda-modem"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x43>; | |
| reg = <0x10803000 0x1000>; | |
| phandle = <0x448>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x187>; | |
| phandle = <0x11b>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x188>; | |
| phandle = <0x11c>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x189>; | |
| phandle = <0x190>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gmu@3d69000 { | |
| iommus = <0xee 0x05 0x00>; | |
| vddcx-supply = <0xea>; | |
| clock-names = "gmu_clk", "cxo_clk", "axi_clk", "memnoc_clk", "ahb_clk", "hub_clk"; | |
| reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; | |
| interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; | |
| clocks = <0x5d 0x03 0x5d 0x05 0x45 0x0d 0x45 0x20 0x5d 0x00 0x5d 0x12>; | |
| qcom,gmu-freq-table = <0xd1cef00 0x40 0x20c85580 0x80>; | |
| vdd-supply = <0x505>; | |
| compatible = "qcom,gen7-gmu"; | |
| interrupt-names = "hfi", "gmu"; | |
| reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; | |
| regulator-names = "vddcx", "vdd"; | |
| phandle = <0x5db>; | |
| mboxes = <0x02 0x00>; | |
| qcom,ipc-core = <0x400000 0x100000>; | |
| mbox-names = "aop"; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| interconnect@16c0000 { | |
| clocks = <0x45 0x00 0x45 0x0a>; | |
| #interconnect-cells = <0x01>; | |
| qcom,bcm-voters = <0x40>; | |
| compatible = "qcom,kalama-pcie_anoc"; | |
| reg = <0x16c0000 0x12200>; | |
| phandle = <0xed>; | |
| qcom,bcm-voter-names = "hlos"; | |
| }; | |
| cti@10c15000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-camera_dl"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10c15000 0x1000>; | |
| phandle = <0x477>; | |
| }; | |
| funnel@10b04000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-aoss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b04000 0x1000>; | |
| phandle = <0x455>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x1ce>; | |
| phandle = <0x1c5>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x1cd>; | |
| phandle = <0x136>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x1cc>; | |
| phandle = <0x130>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x1cf>; | |
| phandle = <0x1cb>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1d0>; | |
| phandle = <0x1d2>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,dsi-display-primary { | |
| pinctrl-names = "panel_active", "panel_suspend"; | |
| qcom,panel-te-source = <0x01>; | |
| pinctrl-0 = <0x760 0x761>; | |
| clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; | |
| vci-supply = <0x30e>; | |
| clocks = <0x758 0x00 0x758 0x01 0x759 0x02 0x759 0x03 0x3c 0x3d>; | |
| label = "primary"; | |
| qcom,dsi-phy = <0x758 0x759>; | |
| qcom,demura-panel-id = <0x00 0x00>; | |
| compatible = "qcom,dsi-display"; | |
| vddio-supply = <0x2e>; | |
| pinctrl-1 = <0x762 0x763>; | |
| phandle = <0x749>; | |
| qcom,dsi-ctrl = <0x74f 0x757>; | |
| qcom,dsi-default-panel = <0x764>; | |
| qcom,mdp = <0x752>; | |
| qcom,platform-te-gpio = <0x33 0x57 0x00>; | |
| }; | |
| qcom,dcvs { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,dcvs"; | |
| ranges; | |
| phandle = <0x3e9>; | |
| ddrqos { | |
| qcom,bus-width = <0x01>; | |
| qcom,dcvs-hw-type = <0x03>; | |
| qcom,freq-tbl = <0x95>; | |
| compatible = "qcom,dcvs-hw"; | |
| phandle = <0x9c>; | |
| sp { | |
| interconnects = <0x4b 0x03 0x4b 0x200>; | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x9d>; | |
| qcom,dcvs-path-type = <0x00>; | |
| }; | |
| }; | |
| ddr { | |
| qcom,bus-width = <0x04>; | |
| qcom,dcvs-hw-type = <0x00>; | |
| qcom,freq-tbl = <0x92>; | |
| compatible = "qcom,dcvs-hw"; | |
| phandle = <0x96>; | |
| fp { | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x97>; | |
| qcom,fp-voter = <0x93>; | |
| qcom,dcvs-path-type = <0x01>; | |
| }; | |
| sp { | |
| interconnects = <0x4b 0x03 0x4b 0x200>; | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x3ea>; | |
| qcom,dcvs-path-type = <0x00>; | |
| }; | |
| }; | |
| llcc { | |
| qcom,bus-width = <0x10>; | |
| qcom,dcvs-hw-type = <0x01>; | |
| qcom,freq-tbl = <0x94>; | |
| compatible = "qcom,dcvs-hw"; | |
| phandle = <0x98>; | |
| fp { | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x99>; | |
| qcom,fp-voter = <0x93>; | |
| qcom,dcvs-path-type = <0x01>; | |
| }; | |
| sp { | |
| interconnects = <0x61 0x02 0x61 0x22e>; | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x3eb>; | |
| qcom,dcvs-path-type = <0x00>; | |
| }; | |
| }; | |
| l3 { | |
| qcom,bus-width = <0x20>; | |
| reg-names = "l3-base", "l3tbl-base"; | |
| qcom,dcvs-hw-type = <0x02>; | |
| compatible = "qcom,dcvs-hw"; | |
| reg = <0x17d90000 0x4000 0x17d90100 0xa0>; | |
| phandle = <0x9a>; | |
| sp { | |
| qcom,shared-offset = <0x90>; | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x9b>; | |
| qcom,dcvs-path-type = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,logbuf-vendor-hooks { | |
| compatible = "qcom,logbuf-vendor-hooks"; | |
| phandle = <0x359>; | |
| }; | |
| csr@10001000 { | |
| qcom,set-byte-cntr-support; | |
| qcom,blk-size = <0x01>; | |
| qcom,hwctrl-set-support; | |
| reg-names = "csr-base"; | |
| coresight-name = "coresight-csr"; | |
| qcom,usb-bam-support; | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0x10001000 0x1000>; | |
| phandle = <0x1dc>; | |
| }; | |
| tsens1@c272000 { | |
| #qcom,sensors = <0x10>; | |
| interrupts = <0x00 0x1fb 0x04 0x00 0x281 0x04>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,tsens-v2"; | |
| interrupt-names = "uplow", "critical"; | |
| reg = <0xc272000 0x1ff 0xc223000 0x1ff>; | |
| phandle = <0xc1>; | |
| }; | |
| microdump_modem { | |
| compatible = "qcom,microdump_modem"; | |
| }; | |
| qcom,glinkpkt { | |
| compatible = "qcom,glinkpkt"; | |
| qcom,glinkpkt-apr-apps2 { | |
| qcom,glinkpkt-edge = "adsp"; | |
| qcom,glinkpkt-dev-name = "apr_apps2"; | |
| qcom,glinkpkt-ch-name = "apr_apps2"; | |
| }; | |
| qcom,glinkpkt-xpan_control { | |
| qcom,glinkpkt-edge = "adsp"; | |
| qcom,glinkpkt-dev-name = "bt_cp_ctrl"; | |
| qcom,glinkpkt-ch-name = "bt_cp_ctrl"; | |
| }; | |
| qcom,glinkpkt-data11 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd11"; | |
| qcom,glinkpkt-ch-name = "DATA11"; | |
| }; | |
| qcom,glinkpkt-qmc-dma { | |
| qcom,glinkpkt-enable-ch-close; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "qmc_dma"; | |
| qcom,glinkpkt-ch-name = "QMC_DMA_LINE"; | |
| }; | |
| qcom,glinkpkt-data1 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd7"; | |
| qcom,glinkpkt-ch-name = "DATA1"; | |
| }; | |
| qcom,glinkpkt-data40-cntl { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smdcntl8"; | |
| qcom,glinkpkt-ch-name = "DATA40_CNTL"; | |
| }; | |
| qcom,glinkpkt-qmc-cma { | |
| qcom,glinkpkt-enable-ch-close; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "qmc_cma"; | |
| qcom,glinkpkt-ch-name = "QMC_CMA_LINE"; | |
| }; | |
| qcom,glinkpkt-data4 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd8"; | |
| qcom,glinkpkt-ch-name = "DATA4"; | |
| }; | |
| qcom,glinkpkt-at-mdm0 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "at_mdm0"; | |
| qcom,glinkpkt-ch-name = "DS"; | |
| }; | |
| }; | |
| funnel@10042000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-in1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10042000 0x1000>; | |
| phandle = <0x452>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1bd>; | |
| phandle = <0x179>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x1c0>; | |
| phandle = <0x192>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x1be>; | |
| phandle = <0x186>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x1c1>; | |
| phandle = <0x1b5>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x1bf>; | |
| phandle = <0x19b>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1c2>; | |
| phandle = <0x1c3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| thermal-zones { | |
| phandle = <0x3f2>; | |
| mmw_pa1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x1a>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| bcl_warn { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x1f>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8550-bcl-lvl0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5eb 0x05>; | |
| thermal-governor = "step_wise"; | |
| trips { | |
| bcl-lvl0 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x605>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vph_gpu0 { | |
| trip = <0x605>; | |
| cooling-device = <0xde 0x02 0x02>; | |
| }; | |
| vph_lte0 { | |
| trip = <0x605>; | |
| cooling-device = <0xd2 0x08 0x08>; | |
| }; | |
| vph_nr0 { | |
| trip = <0x605>; | |
| cooling-device = <0xd4 0x06 0x06>; | |
| }; | |
| vph_nr0_scg { | |
| trip = <0x605>; | |
| cooling-device = <0xd3 0x03 0x03>; | |
| }; | |
| vph_cpu_3_4_5 { | |
| trip = <0x605>; | |
| cooling-device = <0x4d7 0x01 0x01>; | |
| }; | |
| vph_cdsp0 { | |
| trip = <0x605>; | |
| cooling-device = <0xcb 0x02 0x02>; | |
| }; | |
| }; | |
| }; | |
| nspss-3 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xc1 0x07>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| junction-config { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xce>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| nsp_cdev { | |
| trip = <0xce>; | |
| cooling-device = <0xcb 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-8 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x0d>; | |
| trips { | |
| cpu7-emerg0-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xb9>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu7-emerg0-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xbb>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu18_cdev { | |
| trip = <0xb9>; | |
| cooling-device = <0xba 0x01 0x01>; | |
| }; | |
| cpu18_cdev1 { | |
| trip = <0xbb>; | |
| cooling-device = <0xbc 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| epm0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x40>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mmw1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x2f>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| video { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x08>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| camera-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x0e>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8550b_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5ed>; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x62d>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| phandle = <0x630>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x62e>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x62f>; | |
| }; | |
| }; | |
| }; | |
| sdr_mmw_therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x1d>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| sub1_scg_fr2_cc { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x38>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| nspss-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xc1 0x05>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| junction-config { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xcc>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| nsp_cdev { | |
| trip = <0xcc>; | |
| cooling-device = <0xcb 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-6 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x0b>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu6-emerg0-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xb3>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu6-emerg0-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xb5>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu16_cdev1 { | |
| trip = <0xb5>; | |
| cooling-device = <0xb6 0x01 0x01>; | |
| }; | |
| cpu16_cdev { | |
| trip = <0xb3>; | |
| cooling-device = <0xb4 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| mdmss-3 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x0d>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| mdmss3-config0 { | |
| temperature = <0x18e70>; | |
| hysteresis = <0xbb8>; | |
| type = "passive"; | |
| phandle = <0xda>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| mdmss3-config1 { | |
| temperature = <0x19a28>; | |
| hysteresis = <0xbb8>; | |
| type = "passive"; | |
| phandle = <0xdb>; | |
| }; | |
| }; | |
| cooling-maps { | |
| lte_cdev2 { | |
| trip = <0xdb>; | |
| cooling-device = <0xd2 0xff 0xff>; | |
| }; | |
| nr_scg_cdev0 { | |
| trip = <0xda>; | |
| cooling-device = <0xd3 0x0a 0x0a>; | |
| }; | |
| lte_cdev0 { | |
| trip = <0xda>; | |
| cooling-device = <0xd2 0x08 0x08>; | |
| }; | |
| nr_cdev2 { | |
| trip = <0xdb>; | |
| cooling-device = <0xd4 0xff 0xff>; | |
| }; | |
| nr_cdev0 { | |
| trip = <0xda>; | |
| cooling-device = <0xd4 0x06 0x06>; | |
| }; | |
| }; | |
| }; | |
| pm8550b-ibat-lvl0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x5ef 0x00>; | |
| trips { | |
| ibat-lvl0 { | |
| temperature = <0x2710>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x632>; | |
| }; | |
| }; | |
| }; | |
| sdr0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x26>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x02>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu1-emerg-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xc2>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu1-emerg1-cfg { | |
| temperature = <0x1b580>; | |
| hysteresis = <0x2ee0>; | |
| type = "passive"; | |
| phandle = <0xc4>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu01_cdev { | |
| trip = <0xc2>; | |
| cooling-device = <0xc3 0x01 0x01>; | |
| }; | |
| cpu01_cdev1 { | |
| trip = <0xc4>; | |
| cooling-device = <0xc5 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pa { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x00>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpuss-6 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xdc 0x07>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xe4>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu6_cdev { | |
| trip = <0xe4>; | |
| cooling-device = <0xde 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| pm8550vs_g_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5f5>; | |
| status = "ok"; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x64b>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| phandle = <0x64e>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x64c>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x64d>; | |
| }; | |
| }; | |
| }; | |
| epm7 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x47>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-4 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x09>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu5-emerg0-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xad>; | |
| }; | |
| cpu5-emerg0-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xaf>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu14_cdev { | |
| trip = <0xad>; | |
| cooling-device = <0xae 0x01 0x01>; | |
| }; | |
| cpu14_cdev1 { | |
| trip = <0xaf>; | |
| cooling-device = <0xb0 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| mdmss-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x0b>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| mdmss1-config0 { | |
| temperature = <0x18e70>; | |
| hysteresis = <0xbb8>; | |
| type = "passive"; | |
| phandle = <0xd6>; | |
| }; | |
| mdmss1-config1 { | |
| temperature = <0x19a28>; | |
| hysteresis = <0xbb8>; | |
| type = "passive"; | |
| phandle = <0xd7>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| lte_cdev2 { | |
| trip = <0xd7>; | |
| cooling-device = <0xd2 0xff 0xff>; | |
| }; | |
| nr_scg_cdev0 { | |
| trip = <0xd6>; | |
| cooling-device = <0xd3 0x0a 0x0a>; | |
| }; | |
| lte_cdev0 { | |
| trip = <0xd6>; | |
| cooling-device = <0xd2 0x08 0x08>; | |
| }; | |
| nr_cdev2 { | |
| trip = <0xd7>; | |
| cooling-device = <0xd4 0xff 0xff>; | |
| }; | |
| nr_cdev0 { | |
| trip = <0xd6>; | |
| cooling-device = <0xd4 0x06 0x06>; | |
| }; | |
| }; | |
| }; | |
| pm8550vs_d_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5f3>; | |
| status = "ok"; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x644>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| phandle = <0x646>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x609>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x645>; | |
| }; | |
| }; | |
| cooling-maps { | |
| pm8550vs_d_gpu { | |
| trip = <0x609>; | |
| cooling-device = <0xde 0x05 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| pm8550b-bcl-lvl2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5ef 0x07>; | |
| trips { | |
| b-bcl-lvl2 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x604>; | |
| }; | |
| thermal-engine-trip { | |
| temperature = <0x64>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-trip { | |
| temperature = <0x64>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| lbat_gpu2 { | |
| trip = <0x604>; | |
| cooling-device = <0xde 0x05 0xffffffff>; | |
| }; | |
| lbat_cdsp2 { | |
| trip = <0x604>; | |
| cooling-device = <0xcb 0x05 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| wls-therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x5e6 0x749>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8010n_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5fb>; | |
| status = "disabled"; | |
| thermal-governor = "step_wise"; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| aoss-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x00>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| sub1_mcg_fr1_cc { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x35>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| xo-therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x5e6 0x44>; | |
| trips { | |
| display-test-config3 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| phandle = <0x60f>; | |
| }; | |
| display-test-config1 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| phandle = <0x60d>; | |
| }; | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| xo-config0 { | |
| temperature = <0x130b0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0x60b>; | |
| }; | |
| display-test-config4 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| phandle = <0x610>; | |
| }; | |
| display-test-config2 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| phandle = <0x60e>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| xo-config1 { | |
| temperature = <0x13880>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x60c>; | |
| }; | |
| }; | |
| cooling-maps { | |
| apc1_cdev { | |
| trip = <0x60b>; | |
| cooling-device = <0x4d6 0x01 0x01>; | |
| }; | |
| cpu4_hot_cdev { | |
| trip = <0x60c>; | |
| cooling-device = <0xaa 0x01 0x01>; | |
| }; | |
| display_cdev4 { | |
| trip = <0x610>; | |
| cooling-device = <0x4f7 0x04 0x04>; | |
| }; | |
| cdsp_cdev { | |
| trip = <0x60b>; | |
| cooling-device = <0xcb 0x05 0xffffffff>; | |
| }; | |
| nr_cdev { | |
| trip = <0x60c>; | |
| cooling-device = <0xd3 0xff 0xff>; | |
| }; | |
| display_cdev2 { | |
| trip = <0x60e>; | |
| cooling-device = <0x4f7 0x02 0x02>; | |
| }; | |
| lte_cdev { | |
| trip = <0x60c>; | |
| cooling-device = <0xd2 0xff 0xff>; | |
| }; | |
| cpu5_hot_cdev { | |
| trip = <0x60c>; | |
| cooling-device = <0xb0 0x01 0x01>; | |
| }; | |
| cpu6_hot_cdev { | |
| trip = <0x60c>; | |
| cooling-device = <0xb6 0x01 0x01>; | |
| }; | |
| gpu_cdev { | |
| trip = <0x60b>; | |
| cooling-device = <0xde 0x05 0xffffffff>; | |
| }; | |
| display_cdev3 { | |
| trip = <0x60f>; | |
| cooling-device = <0x4f7 0x03 0x03>; | |
| }; | |
| cpu7_hot_cdev { | |
| trip = <0x60c>; | |
| cooling-device = <0xbc 0x01 0x01>; | |
| }; | |
| display_cdev1 { | |
| trip = <0x60d>; | |
| cooling-device = <0x4f7 0x01 0x01>; | |
| }; | |
| cpu3_hot_cdev { | |
| trip = <0x60c>; | |
| cooling-device = <0xa4 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpuss-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xa0 0x03>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| usb-therm { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x5e6 0x747>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpuss-4 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xdc 0x05>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xe2>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu4_cdev { | |
| trip = <0xe2>; | |
| cooling-device = <0xde 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| epm5 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x45>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x07>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu4-emerg0-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xa9>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu4-emerg0-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xa7>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu12_cdev { | |
| trip = <0xa7>; | |
| cooling-device = <0xa8 0x01 0x01>; | |
| }; | |
| cpu12_cdev1 { | |
| trip = <0xa9>; | |
| cooling-device = <0xaa 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pm8550b-bcl-lvl0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5ef 0x05>; | |
| trips { | |
| b-bcl-lvl0 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x602>; | |
| }; | |
| thermal-engine-trip { | |
| temperature = <0x64>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-trip { | |
| temperature = <0x64>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| lbat_0_mdm_lte { | |
| trip = <0x602>; | |
| cooling-device = <0xd2 0x08 0x08>; | |
| }; | |
| lbat_gpu0 { | |
| trip = <0x602>; | |
| cooling-device = <0xde 0x02 0x02>; | |
| }; | |
| lbat_cpu_3_4_5 { | |
| trip = <0x602>; | |
| cooling-device = <0x4d7 0x01 0x01>; | |
| }; | |
| lbat_0_nr { | |
| trip = <0x602>; | |
| cooling-device = <0xd4 0x06 0x06>; | |
| }; | |
| lbat_0_nr_scg { | |
| trip = <0x602>; | |
| cooling-device = <0xd3 0x03 0x03>; | |
| }; | |
| lbat_cdsp0 { | |
| trip = <0x602>; | |
| cooling-device = <0xcb 0x02 0x02>; | |
| }; | |
| }; | |
| }; | |
| cpuss-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xa0 0x01>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpuss-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xdc 0x03>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xe0>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu2_cdev { | |
| trip = <0xe0>; | |
| cooling-device = <0xde 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| epm3 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x43>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| sdr1_pa { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x49>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xa0 0x05>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu3-emerg0-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xa1>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu3-emerg0-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xa3>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu10_cdev1 { | |
| trip = <0xa3>; | |
| cooling-device = <0xa4 0x01 0x01>; | |
| }; | |
| cpu10_cdev { | |
| trip = <0xa1>; | |
| cooling-device = <0xa2 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| mmw_pa2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x1b>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| sub1_lte_cc { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x34>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| sub1_scg_fr1_cc { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x37>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8550-bcl-lvl1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5eb 0x06>; | |
| thermal-governor = "step_wise"; | |
| trips { | |
| bcl-lvl1 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x606>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vph_nr1 { | |
| trip = <0x606>; | |
| cooling-device = <0xd4 0x09 0x09>; | |
| }; | |
| vph_cdsp1 { | |
| trip = <0x606>; | |
| cooling-device = <0xcb 0x04 0x04>; | |
| }; | |
| vph_gpu1 { | |
| trip = <0x606>; | |
| cooling-device = <0xde 0x04 0x04>; | |
| }; | |
| vph_lte1 { | |
| trip = <0x606>; | |
| cooling-device = <0xd2 0x0a 0x0a>; | |
| }; | |
| vph_nr1_scg { | |
| trip = <0x606>; | |
| cooling-device = <0xd3 0x0a 0x0a>; | |
| }; | |
| vph_cpu_6_7 { | |
| trip = <0x606>; | |
| cooling-device = <0x4d8 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-9 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x0e>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu7-emerg1-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xbd>; | |
| }; | |
| cpu7-emerg1-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xbe>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu19_cdev { | |
| trip = <0xbd>; | |
| cooling-device = <0xba 0x01 0x01>; | |
| }; | |
| cpu19_cdev1 { | |
| trip = <0xbe>; | |
| cooling-device = <0xbc 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| gpuss-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xdc 0x01>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xdd>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu0_cdev { | |
| trip = <0xdd>; | |
| cooling-device = <0xde 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| epm1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x41>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mmw2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x30>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| socd { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5f0>; | |
| trips { | |
| socd-trip { | |
| temperature = <0x63>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x601>; | |
| }; | |
| thermal-engine-trip { | |
| temperature = <0x64>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-trip { | |
| temperature = <0x64>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| socd_gpu0 { | |
| trip = <0x601>; | |
| cooling-device = <0xde 0x04 0x04>; | |
| }; | |
| socd_cdsp1 { | |
| trip = <0x601>; | |
| cooling-device = <0xcb 0x04 0x04>; | |
| }; | |
| socd_apc1 { | |
| trip = <0x601>; | |
| cooling-device = <0x4d6 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| sub1_modem_cfg { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x33>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| camera-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x0f>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8550ve_f_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5f1>; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x635>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| phandle = <0x637>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x60a>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x636>; | |
| }; | |
| }; | |
| cooling-maps { | |
| pm8550vs_e_nr { | |
| trip = <0x60a>; | |
| cooling-device = <0xd3 0xff 0xff>; | |
| }; | |
| pm8550vs_e_nsp { | |
| trip = <0x60a>; | |
| cooling-device = <0xcb 0x05 0xffffffff>; | |
| }; | |
| pm8550vs_e_lte { | |
| trip = <0x60a>; | |
| cooling-device = <0xd2 0xff 0xff>; | |
| }; | |
| }; | |
| }; | |
| pm8550vs_c_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5f2>; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x641>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| phandle = <0x643>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x608>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x642>; | |
| }; | |
| }; | |
| cooling-maps { | |
| pm8550vs_c_apc1 { | |
| trip = <0x608>; | |
| cooling-device = <0x4d6 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| nspss-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xc1 0x06>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| junction-config { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xcd>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| nsp_cdev { | |
| trip = <0xcd>; | |
| cooling-device = <0xcb 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| ddr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xc1 0x09>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| ddr0-config { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xcf>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gold_cdev3 { | |
| trip = <0xcf>; | |
| cooling-device = <0x1e 0xffffffff 0xffffffff>; | |
| }; | |
| gold_cdev1 { | |
| trip = <0xcf>; | |
| cooling-device = <0x1c 0xffffffff 0xffffffff>; | |
| }; | |
| gold_cdev2 { | |
| trip = <0xcf>; | |
| cooling-device = <0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| gold_cdev0 { | |
| trip = <0xcf>; | |
| cooling-device = <0x1b 0xffffffff 0xffffffff>; | |
| }; | |
| ddr_cdev { | |
| trip = <0xcf>; | |
| cooling-device = <0xd0 0x05 0x05>; | |
| }; | |
| gold_plus_cdev { | |
| trip = <0xcf>; | |
| cooling-device = <0x1f 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-7 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x0c>; | |
| trips { | |
| cpu6-emerg1-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xb8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu6-emerg1-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xb7>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu17_cdev1 { | |
| trip = <0xb8>; | |
| cooling-device = <0xb6 0x01 0x01>; | |
| }; | |
| cpu17_cdev { | |
| trip = <0xb7>; | |
| cooling-device = <0xb4 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pm8010m_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5fa>; | |
| status = "disabled"; | |
| thermal-governor = "step_wise"; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8550b-ibat-lvl1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x5ef 0x01>; | |
| trips { | |
| ibat-lvl1 { | |
| temperature = <0x2cec>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x633>; | |
| }; | |
| }; | |
| }; | |
| mmw0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x2e>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| sdr1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x2d>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x03>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu2-emerg1-cfg { | |
| temperature = <0x1b580>; | |
| hysteresis = <0x2ee0>; | |
| type = "passive"; | |
| phandle = <0xc8>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu2-emerg-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xc6>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu02_cdev { | |
| trip = <0xc6>; | |
| cooling-device = <0xc7 0x01 0x01>; | |
| }; | |
| cpu02_cdev1 { | |
| trip = <0xc8>; | |
| cooling-device = <0xc9 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| gpuss-7 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xdc 0x08>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xe5>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu7_cdev { | |
| trip = <0xe5>; | |
| cooling-device = <0xde 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| nspss-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xc1 0x04>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| junction-config { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xca>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| nsp_cdev { | |
| trip = <0xca>; | |
| cooling-device = <0xcb 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-5 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x0a>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu5-emerg1-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xb1>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu5-emerg1-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xb2>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu15_cdev1 { | |
| trip = <0xb2>; | |
| cooling-device = <0xb0 0x01 0x01>; | |
| }; | |
| cpu15_cdev { | |
| trip = <0xb1>; | |
| cooling-device = <0xae 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| mdmss-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x0c>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| mdmss2-config1 { | |
| temperature = <0x19a28>; | |
| hysteresis = <0xbb8>; | |
| type = "passive"; | |
| phandle = <0xd9>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| mdmss2-config0 { | |
| temperature = <0x18e70>; | |
| hysteresis = <0xbb8>; | |
| type = "passive"; | |
| phandle = <0xd8>; | |
| }; | |
| }; | |
| cooling-maps { | |
| lte_cdev2 { | |
| trip = <0xd9>; | |
| cooling-device = <0xd2 0xff 0xff>; | |
| }; | |
| nr_scg_cdev0 { | |
| trip = <0xd8>; | |
| cooling-device = <0xd3 0x0a 0x0a>; | |
| }; | |
| lte_cdev0 { | |
| trip = <0xd8>; | |
| cooling-device = <0xd2 0x08 0x08>; | |
| }; | |
| nr_cdev2 { | |
| trip = <0xd9>; | |
| cooling-device = <0xd4 0xff 0xff>; | |
| }; | |
| nr_cdev0 { | |
| trip = <0xd8>; | |
| cooling-device = <0xd4 0x06 0x06>; | |
| }; | |
| }; | |
| }; | |
| aoss-2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xdc 0x00>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mmw_ific0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x32>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x01>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-10 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x0f>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu7-emerg2-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xbf>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu7-emerg2-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xc0>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu110_cdev { | |
| trip = <0xbf>; | |
| cooling-device = <0xba 0x01 0x01>; | |
| }; | |
| cpu110_cdev1 { | |
| trip = <0xc0>; | |
| cooling-device = <0xbc 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpuss-3 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xa0 0x04>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| sdr0_pa { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x48>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpuss-5 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xdc 0x06>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xe3>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu5_cdev { | |
| trip = <0xe3>; | |
| cooling-device = <0xde 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| epm6 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x46>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-3 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xa0 0x08>; | |
| trips { | |
| cpu4-emerg1-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xab>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu4-emerg1-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xac>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu13_cdev1 { | |
| trip = <0xac>; | |
| cooling-device = <0xaa 0x01 0x01>; | |
| }; | |
| cpu13_cdev { | |
| trip = <0xab>; | |
| cooling-device = <0xa8 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| mdmss-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xc1 0x0a>; | |
| trips { | |
| mdmss0-config1 { | |
| temperature = <0x19a28>; | |
| hysteresis = <0xbb8>; | |
| type = "passive"; | |
| phandle = <0xd5>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| mdmss0-config0 { | |
| temperature = <0x18e70>; | |
| hysteresis = <0xbb8>; | |
| type = "passive"; | |
| phandle = <0xd1>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| lte_cdev2 { | |
| trip = <0xd5>; | |
| cooling-device = <0xd2 0xff 0xff>; | |
| }; | |
| nr_scg_cdev0 { | |
| trip = <0xd1>; | |
| cooling-device = <0xd3 0x0a 0x0a>; | |
| }; | |
| lte_cdev0 { | |
| trip = <0xd1>; | |
| cooling-device = <0xd2 0x08 0x08>; | |
| }; | |
| nr_cdev2 { | |
| trip = <0xd5>; | |
| cooling-device = <0xd4 0xff 0xff>; | |
| }; | |
| nr_cdev0 { | |
| trip = <0xd1>; | |
| cooling-device = <0xd4 0x06 0x06>; | |
| }; | |
| }; | |
| }; | |
| pm8550b-bcl-lvl1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5ef 0x06>; | |
| trips { | |
| thermal-engine-trip { | |
| temperature = <0x64>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| b-bcl-lvl1 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x603>; | |
| }; | |
| thermal-hal-trip { | |
| temperature = <0x64>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| lbat_1_nr { | |
| trip = <0x603>; | |
| cooling-device = <0xd4 0x09 0x09>; | |
| }; | |
| lbat_cdsp1 { | |
| trip = <0x603>; | |
| cooling-device = <0xcb 0x04 0x04>; | |
| }; | |
| lbat_cpu_6_7 { | |
| trip = <0x603>; | |
| cooling-device = <0x4d8 0x01 0x01>; | |
| }; | |
| lbat_1_mdm_lte { | |
| trip = <0x603>; | |
| cooling-device = <0xd2 0x0a 0x0a>; | |
| }; | |
| lbat_gpu1 { | |
| trip = <0x603>; | |
| cooling-device = <0xde 0x04 0x04>; | |
| }; | |
| lbat_1_nr_scg { | |
| trip = <0x603>; | |
| cooling-device = <0xd3 0x0a 0x0a>; | |
| }; | |
| }; | |
| }; | |
| aoss-0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xa0 0x00>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pa1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x01>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8550_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5ea>; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x626>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| phandle = <0x629>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x627>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x628>; | |
| }; | |
| }; | |
| }; | |
| cpuss-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xa0 0x02>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpuss-3 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xdc 0x04>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xe1>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu3_cdev { | |
| trip = <0xe1>; | |
| cooling-device = <0xde 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| epm4 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x44>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0xa0 0x06>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| cpu3-emerg1-1-cfg { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0xa6>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| cpu3-emerg1-cfg { | |
| temperature = <0x1a5e0>; | |
| hysteresis = <0x1f40>; | |
| type = "passive"; | |
| phandle = <0xa5>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu11_cdev { | |
| trip = <0xa5>; | |
| cooling-device = <0xa2 0x01 0x01>; | |
| }; | |
| cpu11_cdev1 { | |
| trip = <0xa6>; | |
| cooling-device = <0xa4 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| mmw_pa3 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x1c>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8550vs_e_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5f4>; | |
| status = "ok"; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x647>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| phandle = <0x64a>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x648>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x649>; | |
| }; | |
| }; | |
| }; | |
| pm8550b_lite_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5ee>; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x631>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "critical"; | |
| }; | |
| trip0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| trip1 { | |
| temperature = <0x20f58>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8550-bcl-lvl2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x5eb 0x07>; | |
| thermal-governor = "step_wise"; | |
| trips { | |
| bcl-lvl2 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x607>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vph_gpu2 { | |
| trip = <0x607>; | |
| cooling-device = <0xde 0x05 0xffffffff>; | |
| }; | |
| vph_cdsp2 { | |
| trip = <0x607>; | |
| cooling-device = <0xcb 0x05 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| sub1_mcg_fr2_cc { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x36>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpuss-1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0xdc 0x02>; | |
| trips { | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xdf>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu1_cdev { | |
| trip = <0xdf>; | |
| cooling-device = <0xde 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| epm2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x42>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mmw3 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x9f 0x31>; | |
| trips { | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@13860000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x42>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-actpm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x13860000 0x1000>; | |
| phandle = <0x421>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x119>; | |
| phandle = <0x195>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@10ac1000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x01 0x20>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpda-dl_north"; | |
| qcom,dsb-elem-size = <0x02 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x61>; | |
| reg = <0x10ac1000 0x1000>; | |
| phandle = <0x446>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x180>; | |
| phandle = <0x120>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x181>; | |
| phandle = <0x115>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x182>; | |
| phandle = <0x183>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@112060000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-cpu5"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x12060000 0x1000>; | |
| phandle = <0x48b>; | |
| trig-conns { | |
| arm,trig-out-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| cpu = <0x1d>; | |
| arm,trig-in-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| }; | |
| }; | |
| gpio5_pwm { | |
| pinctrl-names = "default", "fg_int"; | |
| gpio5-pwm-state = <0x01>; | |
| pinctrl-0 = <0x614>; | |
| gpio5-pwm-duty-ns = <0x2710>; | |
| qcom,fan-en-gpio = <0x33 0x6d 0x00>; | |
| gpio5-pwm-period-ns = <0xc350>; | |
| compatible = "gpio5-pwm"; | |
| pinctrl-1 = <0x35f>; | |
| qcom,fan-fg-gpio = <0x33 0x0d 0x2004>; | |
| pwms = <0x613 0x00 0x186a0>; | |
| }; | |
| qcom,rt-cdm4@ac29000 { | |
| clock-names = "cam_cc_cpas_ahb_clk"; | |
| reg-names = "rt-cdm4"; | |
| fifo-depths = <0x40 0x00 0x00 0x00>; | |
| reg-cam-base = <0x29000>; | |
| cdm-client-names = "ife4"; | |
| cell-index = <0x04>; | |
| interrupts = <0x00 0x15d 0x01>; | |
| clocks = <0x3b 0x0f>; | |
| label = "rt-cdm"; | |
| clock-cntl-level = "turbo"; | |
| cam_hw_pid = <0x1e>; | |
| compatible = "qcom,cam-rt-cdm2_1"; | |
| gdsc-supply = <0x2d9>; | |
| status = "ok"; | |
| interrupt-names = "rt-cdm4"; | |
| reg = <0xac29000 0x400>; | |
| regulator-names = "gdsc"; | |
| cam-hw-mid = <0x00>; | |
| nrt-device; | |
| single-context-cdm; | |
| clock-rates = <0x00>; | |
| config-fifo; | |
| }; | |
| funnel@10d03000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-ddr_dl0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10d03000 0x1000>; | |
| phandle = <0x43d>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x14e>; | |
| phandle = <0x146>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x14f>; | |
| phandle = <0xfa>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x14d>; | |
| phandle = <0x148>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x151>; | |
| phandle = <0x14c>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x150>; | |
| phandle = <0xf9>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| source = <0x153>; | |
| remote-endpoint = <0x152>; | |
| phandle = <0x1a9>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| source = <0x159>; | |
| remote-endpoint = <0x158>; | |
| phandle = <0x1ae>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| source = <0x155>; | |
| remote-endpoint = <0x154>; | |
| phandle = <0x1ac>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x15a>; | |
| phandle = <0x1b2>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| source = <0x157>; | |
| remote-endpoint = <0x156>; | |
| phandle = <0x1ab>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@af0b000 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x28>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x0f>; | |
| regulator-name = "disp_cc_mdss_core_int2_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xaf0b000 0x04>; | |
| phandle = <0x502>; | |
| }; | |
| ete5 { | |
| atid = <0x06>; | |
| qcom,skip-power-up; | |
| cpu = <0x1d>; | |
| coresight-name = "coresight-ete5"; | |
| phy-cpu = <0x05>; | |
| compatible = "arm,embedded-trace-extension"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1e5>; | |
| phandle = <0x1ee>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@10b44000 { | |
| coresight-name = "coresight-funnel-lpass_lpi_0"; | |
| compatible = "arm,coresight-static-funnel"; | |
| phandle = <0x433>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x134>; | |
| phandle = <0xef>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x135>; | |
| phandle = <0x133>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x136>; | |
| phandle = <0x1cd>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,dma-heaps { | |
| compatible = "qcom,dma-heaps"; | |
| qcom,display { | |
| memory-region = <0x1f2>; | |
| qcom,dma-heap-name = "qcom,display"; | |
| qcom,max-align = <0x09>; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,audio_ml { | |
| memory-region = <0x1f8>; | |
| qcom,dma-heap-name = "qcom,audio-ml"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,qseecom_ta { | |
| memory-region = <0x48>; | |
| qcom,dma-heap-name = "qcom,qseecom-ta"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,qseecom { | |
| memory-region = <0x47>; | |
| qcom,dma-heap-name = "qcom,qseecom"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,secure_sp_tz { | |
| qcom,token = <0x1000000>; | |
| memory-region = <0x1f7>; | |
| qcom,dma-heap-name = "qcom,secure-sp-tz"; | |
| qcom,dma-heap-type = <0x00>; | |
| }; | |
| qcom,secure_cdsp { | |
| memory-region = <0x1f4>; | |
| qcom,dma-heap-name = "qcom,cma-secure-cdsp"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,demura { | |
| memory-region = <0x1f3>; | |
| qcom,dma-heap-name = "qcom,demura"; | |
| qcom,max-align = <0x09>; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,secure_sp_modem { | |
| qcom,token = <0x10800000>; | |
| memory-region = <0x1f6>; | |
| qcom,dma-heap-name = "qcom,secure-sp-modem"; | |
| qcom,dma-heap-type = <0x00>; | |
| }; | |
| qcom,adsp { | |
| memory-region = <0x1f9>; | |
| qcom,dma-heap-name = "qcom,adsp"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,user_contig { | |
| memory-region = <0x49>; | |
| qcom,dma-heap-name = "qcom,user-contig"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| qcom,sp_hlos { | |
| memory-region = <0x1f5>; | |
| qcom,dma-heap-name = "qcom,sp-hlos"; | |
| qcom,dma-heap-type = <0x02>; | |
| }; | |
| }; | |
| qcom,csiphy3@acea000 { | |
| csi-vdd-1p2-supply = <0x31>; | |
| rgltr-max-voltage = <0x00 0x124f80 0xe1d48>; | |
| csi-vdd-0p9-supply = <0x30>; | |
| clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0xea000>; | |
| cell-index = <0x03>; | |
| interrupts = <0x00 0x1c0 0x01>; | |
| clocks = <0x3b 0x1b 0x3b 0x35 0x3b 0x26 0x3b 0x25>; | |
| rgltr-load-current = <0x00 0x4650 0x7dc8>; | |
| gdscr-supply = <0x2d9>; | |
| rgltr-cntrl-support; | |
| clock-cntl-level = "lowsvs", "nominal"; | |
| compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; | |
| rgltr-min-voltage = <0x00 0x124f80 0xd59f8>; | |
| src-clock-name = "csi3phytimer_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "CSIPHY3"; | |
| reg = <0xacea000 0x2000>; | |
| regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; | |
| phandle = <0x575>; | |
| shared-clks = <0x01 0x00 0x00 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; | |
| }; | |
| qcom,mdss_mdp@ae00000 { | |
| qcom,sde-dsc-hw-rev = "dsc_1_2"; | |
| qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; | |
| qcom,sde-dsc-enc-size = <0x9c>; | |
| qcom,sde-max-per-pipe-bw-kbps = <0x44aa20 0x44aa20 0x44aa20 0x44aa20 0x44aa20 0x44aa20 0x44aa20 0x44aa20 0x44aa20 0x44aa20>; | |
| qcom,sde-smart-dma-rev = "smart_dma_v2p5"; | |
| qcom,sde-qos-cpu-irq-latency = <0x12c>; | |
| qcom,sde-vbif-off = <0x00>; | |
| qcom,sde-panic-per-pipe; | |
| qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x00 0x00 0x00 0x00 0x00 0x00 0xffff 0xffff 0xffff 0xffff 0x00 0x00>; | |
| qcom,sde-sspp-smart-dma-priority = <0x07 0x08 0x09 0x0a 0x01 0x02 0x03 0x04 0x05 0x06>; | |
| qcom,sde-sspp-qseed-off = <0xa00>; | |
| qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; | |
| qcom,sde-ubwc-swizzle = <0x06>; | |
| qcom,sde-dspp-size = <0x1800>; | |
| qcom,sde-ipcc-protocol-id = <0x02>; | |
| qcom,sde-sspp-src-size = <0x344>; | |
| clock-max-rate = <0x00 0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; | |
| qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; | |
| qcom,sde-sspp-excl-rect = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>; | |
| qcom,sde-creq-lut = <0x112233 0x44556666 0x112233 0x66666666 0x112233 0x44556666 0x112233 0x66666666 0x00 0x00 0x00 0x00 0x77776666 0x66666540 0x77776666 0x66666540 0x77776541 0x00 0x77776541 0x00 0x112233 0x44556666 0x112233 0x66666666 0x112233 0x44556666 0x112233 0x66666666 0x00 0x00 0x00 0x00>; | |
| qcom,sde-wb-id = <0x01 0x02>; | |
| qcom,sde-vbif-dynamic-ot-wr-limit = <0x3b53800 0x02 0x76a7000 0x06 0x1da9c000 0x10>; | |
| qcom,sde-dsc-ctl-size = <0x24>; | |
| qcom,sde-ubwc-bw-calc-version = <0x01>; | |
| qcom,sde-dnsc-blur-dither-size = <0x20>; | |
| qcom,sde-wb-size = <0x2c8>; | |
| interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; | |
| connectors = <0x748 0x749 0x74a 0x74b 0x74c 0x74d 0x74e>; | |
| qcom,sde-dsc-pair-mask = <0x02 0x01 0x04 0x03>; | |
| qcom,sde-macrotile-mode = <0x01>; | |
| qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; | |
| qcom,sde-dnsc-blur-off = <0x7d000>; | |
| qcom,sde-pp-size = <0x04>; | |
| qcom,sde-dest-scaler-top-off = <0x61000>; | |
| clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; | |
| interconnects = <0xec 0x14 0x61 0x22e 0x4b 0x03 0x4b 0x200 0x61 0x02 0x62 0x20e>; | |
| reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; | |
| qcom,sde-dspp-rc-min-region-width = <0x14>; | |
| qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; | |
| qcom,sde-max-dest-scaler-output-linewidth = <0xa00>; | |
| qcom,sde-qos-cpu-mask = <0x03>; | |
| qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; | |
| qcom,sde-smart-panel-align-mode = <0x0c>; | |
| qcom,sde-dspp-demura-off = <0x15600 0x14600>; | |
| qcom,sde-dest-scaler-size = <0x800>; | |
| qcom,sde-reg-dma-id = <0x00 0x01>; | |
| qcom,sde-vbif-qos-nrt-remap = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-dsc-linewidth = <0xa00>; | |
| qcom,sde-cdp-setting = <0x01 0x01 0x01 0x00>; | |
| qcom,sde-dnsc-blur-size = <0x40>; | |
| qcom,sde-dnsc-blur-version = <0x100>; | |
| qcom,sde-reg-dma-trigger-off = <0x119c>; | |
| qcom,sde-qos-cpu-mask-performance = <0x07>; | |
| qcom,sde-dram-channels = <0x04>; | |
| qcom,sde-ctl-size = <0x290>; | |
| qcom,sde-max-trusted-vm-displays = <0x01>; | |
| qcom,sde-csc-type = "csc-10bit"; | |
| qcom,sde-dspp-spr-size = <0x100>; | |
| interrupts = <0x00 0x53 0x04>; | |
| qcom,sde-dspp-rc-version = <0x10001>; | |
| clocks = <0x45 0x0f 0x45 0x10 0x3c 0x02 0x3c 0x3d 0x3c 0x3e 0x3c 0x49 0x3c 0x40>; | |
| qcom,sde-merge-3d-size = <0x08>; | |
| qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>; | |
| qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb"; | |
| qcom,sde-dspp-demura-size = <0xe4>; | |
| qcom,sde-vbif-qos-cwb-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>; | |
| qcom,sde-mixer-pair-mask = <0x02 0x01 0x04 0x03 0x06 0x05 0x08 0x07>; | |
| qcom,sde-dither-version = <0x20000>; | |
| qcom,sde-vm-exclude-reg-names = "ipcc_reg"; | |
| qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; | |
| qcom,sde-pp-cwb = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01>; | |
| qcom,sde-min-core-ib-kbps = <0x2625a0>; | |
| qcom,sde-pp-merge-3d-id = <0x00 0x00 0x01 0x01 0x02 0x02 0x03 0x03>; | |
| qcom,sde-off = <0x1000>; | |
| qcom,sde-vbif-memtype-0 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-sspp-clk-ctrl = <0x4330 0x00 0x6330 0x00 0x8330 0x00 0xa330 0x00 0x24330 0x00 0x26330 0x00 0x28330 0x00 0x2a330 0x00 0x2c330 0x00 0x2e330 0x00>; | |
| qcom,sde-dspp-top-off = <0x1300>; | |
| qcom,sde-reg-dma-xin-id = <0x07>; | |
| qcom,sde-dspp-rc-size = <0x38>; | |
| qcom,sde-dspp-top-size = <0x80>; | |
| qcom,sde-qos-cpu-dma-latency = <0x12c>; | |
| qcom,sde-mixer-blendstages = <0x0b>; | |
| qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x01 0x01 0x3ff 0x3ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff>; | |
| qcom,sde-dsc-size = <0x04>; | |
| qcom,sde-dither-size = <0x20>; | |
| qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; | |
| qcom,sde-mixer-linewidth = <0xa00>; | |
| qcom,sde-max-per-pipe-bw-high-kbps = <0x4f5880 0x4f5880 0x4f5880 0x4f5880 0x4f5880 0x4f5880 0x4f5880 0x4f5880 0x4f5880 0x4f5880>; | |
| qcom,sde-dest-scaler-top-size = <0x1c>; | |
| qcom,sde-wb-xin-id = <0x0a 0x06>; | |
| qcom,sde-uidle-size = <0x80>; | |
| qcom,sde-min-llcc-ib-kbps = <0x00>; | |
| qcom,sde-max-dest-scaler-input-linewidth = <0x800>; | |
| qcom,sde-has-src-split; | |
| qcom,sde-sspp-csc-off = <0x1a00>; | |
| qcom,sde-has-dest-scaler; | |
| compatible = "qcom,sde-kms"; | |
| qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400>; | |
| qcom,sde-dest-scaler-off = <0x00 0x1000 0x2000 0x3000>; | |
| qcom,sde-ubwc-version = <0x40030001>; | |
| #interrupt-cells = <0x01>; | |
| clock-mmrm = <0x00 0x00 0x00 0x00 0x3e 0x00 0x00>; | |
| clock-rate = <0x00 0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; | |
| qcom,sde-intf-size = <0x300>; | |
| qcom,sde-dspp-rc-mem-size = <0xaa0>; | |
| qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; | |
| qcom,sde-mixer-size = <0x400>; | |
| qcom,sde-wb-linewidth-linear = <0x1400>; | |
| qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none"; | |
| qcom,sde-has-idle-pc; | |
| qcom,sde-vbif-qos-offline-wb-remap = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-sspp-clk-status = <0x4334 0x00 0x6334 0x00 0x8334 0x00 0xa334 0x00 0x24334 0x00 0x26334 0x00 0x28334 0x00 0x2a334 0x00 0x2c334 0x00 0x2e334 0x00>; | |
| qcom,sde-dnsc-blur-dither-off = <0x5e0>; | |
| qcom,sde-ipcc-client-dpu-phys-id = <0x19>; | |
| qcom,sde-dspp-spr-off = <0x15400 0x14400>; | |
| qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000 0x67700>; | |
| qcom,sde-min-dram-ib-kbps = "", "\f5"; | |
| reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaeac000 0x800 0x400000 0x1000>; | |
| qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f>; | |
| qcom,sde-max-bw-low-kbps = <0x107fa20>; | |
| qcom,sde-lm-noise-version = <0x10000>; | |
| qcom,sde-pipe-order-version = <0x01>; | |
| qcom,sde-highest-bank-bit = <0x08 0x03 0x07 0x02>; | |
| qcom,sde-vbif-id = <0x00>; | |
| phandle = <0x752>; | |
| qcom,sde-vbif-default-ot-rd-limit = <0x28>; | |
| qcom,sde-dsc-ctl = <0xf00 0xf80 0xf00 0xf80>; | |
| qcom,sde-dsc-native422-supp = <0x00 0x00 0x01 0x01>; | |
| qcom,sde-cdm-size = <0x220>; | |
| qcom,sde-reg-dma-clk-ctrl = <0x2bc 0x14>; | |
| qcom,sde-vbif-qos-rt-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>; | |
| qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; | |
| qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800 0x12800>; | |
| qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; | |
| qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0xdea8 0x00 0x900b0 0x00 0x122870>; | |
| qcom,sde-uidle-off = <0x80000>; | |
| qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>; | |
| qcom,sde-num-nrt-paths = <0x00>; | |
| qcom,sde-reg-dma-off = <0x00 0x400>; | |
| qcom,sde-cdm-off = <0x7a200>; | |
| qcom,sde-dspp-demura-version = <0x10000>; | |
| qcom,sde-vbif-qos-lutdma-remap = <0x03 0x03 0x03 0x03 0x04 0x04 0x04 0x06 0x03 0x03 0x03 0x03 0x04 0x04 0x04 0x06>; | |
| qcom,sde-vbif-default-ot-wr-limit = <0x20>; | |
| qcom,sde-dspp-ltm-version = <0x10002>; | |
| qcom,sde-reg-dma-version = <0x20000>; | |
| qcom,sde-vbif-memtype-1 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-wb-off = <0x65000 0x66000>; | |
| qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; | |
| qcom,sde-has-cdp; | |
| qcom,sde-lm-noise-off = <0x320>; | |
| qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; | |
| qcom,sde-vbif-size = <0x1074>; | |
| qcom,sde-ubwc-static = <0x01>; | |
| qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01>; | |
| qcom,sde-sspp-linewidth = <0x1400>; | |
| qcom,sde-qseed-scalar-version = <0x3002>; | |
| qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,sde-wb-linewidth = <0x1000>; | |
| qcom,sde-vbif-qos-cnoc-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x05 0x05 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-dspp-spr-version = <0x10000>; | |
| qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; | |
| qcom,sde-secure-sid-mask = <0x2801 0x2c01>; | |
| interrupt-controller; | |
| qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; | |
| qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; | |
| #cooling-cells = <0x02>; | |
| qcom,sde-len = <0x488>; | |
| qcom,sde-has-dim-layer; | |
| qcom,sde-max-bw-high-kbps = <0x17d7840>; | |
| mmcx-supply = <0x28>; | |
| qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_cmd { | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel without DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,panel-cphy-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x78b>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-rx-eot-ignore; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2b0 0x390100 0x06 0xb66c0006 0x23963901 0x00 0x2b42039 0x1000000 0xcc209 0x240c0000 0xc000000 0x93c3901 0x00 0x1ad700b9 0x3c004004 0xa00a00 0x40000000 0x19 0x3c004004 0xa00a39 0x1000000 0x2b080 0x39010000 0x14de 0x40001800 0x18001800 0x18100018 0x180018 0x2000039 0x1000000 0x2b004 0x39010000 0x3e8 0x23901 0x00 0x3e40008 0x39010000 0x2b0 0x390100 0x11 0xc4000000 0x00 0x00 0x2000000 0x32390100 0x19 0xcf640b00 0x00 0x8000b 0x77010101 0x1010102 0x2020202 0x3390100 0x15 0xd3450000 0x1131500 0x15070f77 0x777737b2 0x1100a03c 0x9c390100 0x1a 0xd700b934 0x400400 0xa00a0040 0x00 0x1934 0x400400 0xa00a3901 0x00 0x34d80000 0x00 0x3a 0x3a003a 0x3a003a 0x5000000 0x00 0xa00 0xa000000 0x00 0x00 0xa00 0x32000a00 0x22390100 0x2b 0xdf504258 0x812d0000 0x00 0x6b000000 0x00 0x10fff 0xd40e0000 0x00 0xf53f100 0x00 0x39 0x1000000 0x2f701 0x39010000 0x2b0 0x80390100 0x0a 0xe434b400 0x3904 0x9343901 0x00 0x2e60039 0x1000000 0x2b004 0x39010000 0x3eb 0x3901 0x00 0x2f70039 0x1000000 0x3df50 0x40390100 0x06 0xf3500000 0x3901 0x00 0x2f21139 0x1000000 0x6f301 0x01 0x39010000 0x3f4 0x23901 0x00 0x2f21939 0x1000000 0x3df50 0x42390100 0x02 0x35003901 0x00 0x52a0000 0x4373901 0x00 0x52b0000 0x9230501 0x7800 0x1110501 0x1400 0x1293901 0x00 0x2b00039 0x1000000 0x1ac209 0x240c0000 0xc031400 0x93c0000 0x00 0x00 0x30006c>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1a 27 09 19 09 02 04 00 00 00]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_hx8394f_720p_video { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "hx8394f video mode dsi panel without DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bl-pwm-pmi; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-reset-gpio = <0x33 0xce 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,platform-mipi-vdd = <0x33 0x20 0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,bl-pmic-pwm-period-usecs = <0x64>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x79c>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| pwms = <0x658 0x00 0xf4240>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x1f>; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x32>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-on-command = [29 01 00 00 00 00 04 b9 ff 83 94 29 01 00 00 00 00 07 ba 63 03 68 6b b2 c0 29 01 00 00 00 00 0b b1 50 12 72 09 33 54 b1 31 6b 2f 29 01 00 00 00 00 07 b2 00 80 64 0e 0d 2f 29 01 00 00 00 00 16 b4 73 74 73 74 73 74 01 0c 86 75 00 3f 73 74 73 74 73 74 01 0c 86 29 01 00 00 00 00 22 d3 00 00 07 07 40 07 10 00 08 10 08 00 08 54 15 0e 05 0e 02 15 06 05 06 47 44 0a 0a 4b 10 07 07 0e 40 29 01 00 00 00 00 2d d5 1a 1a 1b 1b 00 01 02 03 04 05 06 07 08 09 0a 0b 24 25 18 18 26 27 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 20 21 18 18 18 18 29 01 00 00 00 00 2d d6 1a 1a 1b 1b 0b 0a 09 08 07 06 05 04 03 02 01 00 21 20 18 18 27 26 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 25 24 18 18 18 18 29 01 00 00 00 00 3b e0 00 0d 1b 22 25 2a 2f 2c 5a 6b 7a 77 7e 8e 92 95 9f 9e 99 a1 b0 57 55 5c 5f 5f 67 6f 7f 00 0d 1b 22 25 2a 2f 2c 5a 6b 7a 77 7e 8e 92 95 9f 9e 99 a1 b0 57 55 5c 5f 5f 67 6f 7f 29 01 00 00 00 00 03 c0 1f 31 29 01 00 00 00 00 02 cc 0b 29 01 00 00 00 00 03 b6 78 78 29 01 00 00 00 00 02 d4 02 29 01 00 00 00 00 02 bd 02 29 01 00 00 00 00 0d d8 ff ff ff ff ff ff ff ff ff ff ff ff 29 01 00 00 00 00 02 bd 00 29 01 00 00 00 00 02 bd 01 29 01 00 00 00 00 02 b1 00 29 01 00 00 00 00 02 bd 00 29 01 00 00 00 00 08 bf 40 81 50 00 1a fc 01 05 01 00 00 78 00 02 11 00 05 01 00 00 05 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x32>; | |
| qcom,mdss-dsi-h-back-porch = <0x32>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 04 03 02 04 00 0e 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_wqxga_video_truly { | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi truly panel without DSC"; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,esd-check-enabled; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0x3ff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x32>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| phandle = <0x782>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 21 07 07 08 02 04 00 18 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x21>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35532_720p_cmd { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-name = "nt35532 cmd mode dsi truly panel with DSC"; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk1", "pll_dsi_clk1"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,platform-vdisp-en-n = <0x33 0x66 0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bl-pwm-pmi; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,platform-reset-gpio = <0x33 0x85 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,platform-vdisp-en-p = <0x33 0x65 0x00>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,platform-mipi-vdd = <0x33 0x20 0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,bl-pmic-pwm-period-usecs = <0x64>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x79e>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| pwms = <0x658 0x00 0xf4240>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x1f>; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0a>; | |
| qcom,mdss-dsi-panel-jitter = <0x01 0x01>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = [05 01 00 00 46 00 02 11 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 07 7f 05 01 00 00 00 00 02 35 00 05 01 00 00 00 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x3c>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x08>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x14>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 05 00 02 28 00 05 01 00 00 53 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x787>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 86 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 00 00 00 00 00 00 00 00 00 00 00 00 02 c9 02 c9 02 c9 03 ff 03 ff 03 ff 00 00 00 00 00 00 00 00 00 00 00 00 02 c9 02 c9 02 c9 03 ff 03 ff 03 ff 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 19 19 19 19 19 19 19 19 19 19 19 19 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f f6 0f f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 0d 17 01 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 1a d7 00 b9 40 00 40 04 00 f0 0f 00 40 00 00 00 00 00 00 19 40 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_4k_dsc_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x47>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x81>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x77>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x64 0x00 0x64 0x01 0x64>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x77>; | |
| phandle = <0x77a>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,dcs-cmd-by-left; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x08 0x0a>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 05 06 02 04 00 12 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_vtdr6130_fhd_plus_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-bl-min-level = <0x0a>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,platform-reset-gpio = <0x33 0x85 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,panel-sec-supply-entries = <0x750>; | |
| qcom,dsi-dyn-clk-enable; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x777>; | |
| qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-inverted-dbv; | |
| qcom,mdss-brightness-max-level = <0x1fff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@3 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x03>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 02 13 25 0d 8a 00 90 00 7d 00 57 00 0c 00 0c 0b 00 7e 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 02 13 25 0d 8a 00 90 00 7d 00 57 00 0c 00 0c 0b 00 7e]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-panel-clockrate = <0x3083ad80>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,dsi-dyn-clk-list = <0x3083ad80 0x30c45d12 0x31050ca4>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x28 0x28 0x438 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@1 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a 81 09 92 06 c5 00 48 00 3e 00 2b 00 0c 00 0c 05 00 3f 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a 81 09 92 06 c5 00 48 00 3e 00 2b 00 0c 00 0c 05 00 3f]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-panel-clockrate = <0x3083ad80>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,dsi-dyn-clk-list = <0x3083ad80 0x30c45d12 0x31050ca4>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x28 0x28 0x438 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e 01 0c c3 09 06 00 60 00 53 00 3a 00 0c 00 0c 07 00 54 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e 01 0c c3 09 06 00 60 00 53 00 3a 00 0c 00 0c 07 00 54]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-panel-clockrate = <0x3083ad80>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,dsi-dyn-clk-list = <0x3083ad80 0x30c45d12 0x31050ca4>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x28 0x28 0x438 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,video-mode-switch-in-commands = [39 01 00 00 00 00 02 6f 01]; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| qcom,vid-on-commands = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 01 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,cmd-mode-switch-out-commands = [39 01 00 00 00 00 02 6f 07]; | |
| qcom,compression-mode = "dsc"; | |
| qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-video-mode; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-front-porch = <0x0a>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x10>; | |
| qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-panel-clockrate = <0x3083ad80>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,dsi-dyn-clk-list = <0x3083ad80 0x30c45d12 0x31050ca4>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,cmd-on-commands = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x28 0x28 0x438 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-cmd-mode; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x12>; | |
| qcom,video-mode-switch-out-commands = [39 01 00 00 00 00 02 6f 03 39 01 00 00 00 00 02 6f 02]; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd { | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,panel-cphy-mode; | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x784>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-rx-eot-ignore; | |
| qcom,mdss-dsi-display-timings { | |
| timing@3 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x03>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 03 01 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 12 17 04 19 03 02 04 00 00 00]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 03 01 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 10 13 03 19 02 02 04 00 00 00]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 03 01 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20]; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 03 01 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 00 00 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 14 1b 05 19 06 02 04 00 00 00]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2b0 0x4390100 0x03 0xe8000239 0x1000000 0x3e400 0x8390100 0x03 0xb4201c39 0x1000000 0xdb66c 0x623af 0x131a0504 0xfa052039 0x1000000 0x2b000 0x39010000 0x32c4 0x00 0x00 0x10000002 0x29 0x10000 0x00 0x00 0x220000 0x1100 0xc0000 0x3000 0x00 0x390100 0x0d 0xd04444b2 0x2800285a 0x5a030d 0x1390100 0x15 0xd3490000 0x11a1500 0x15070f77 0x777737b2 0x1100a03c 0x9a390100 0x34 0xd8000000 0x00 0x3000 0x30003000 0x30003005 0x00 0x00 0xf000f 0x00 0x00 0x00 0xf002f 0xf0020 0x39010000 0x2bdf 0x50425881 0x2d000000 0x6b 0x00 0x00 0x10fffd4 0xe000000 0x0f 0x5318000f 0x00 0x3901 0x00 0x3eb8b8b 0x39010000 0x2f7 0x1390100 0x02 0xb0803901 0x00 0xae434b4 0x30 0x40ce239 0x1000000 0x2e600 0x39010000 0x2b0 0x4390100 0x03 0xdf504039 0x1000000 0x6f350 0x00 0x39010000 0x2f2 0x11390100 0x06 0xf3010000 0x13901 0x00 0x3f40002 0x39010000 0x2f2 0x19390100 0x03 0xdf504239 0x1000000 0x23500 0x39010000 0x52a 0x437 0x39010000 0x52b 0x923 0x5010000 0x78000111 0x5010000 0x129>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = <0x39010000 0xdd0 0x4444b228 0x285a00 0x5a030d01 0x39010000 0x1ac2 0x9240c00 0x40000 0x93400 0x00 0x00 0x3000 0x6c390100 0x34 0xd8000000 0x00 0x3000 0x30003000 0x30003005 0x00 0x00 0xf000f 0x00 0x00 0x00 0xf002f 0xf0020>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 15 1f 06 19 07 02 04 00 00 00]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_visionox_r66451_fhd_plus_video { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled video mode dsi visionox panel with DSC"; | |
| qcom,esd-check-enabled; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| phandle = <0x785>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35695b_truly_fhd_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "nt35695b truly fhd command mode dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-post-init-delay = <0x01>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| phandle = <0x783>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 08 02 04 00 1b 18]; | |
| qcom,mdss-dsi-v-back-porch = <0x02>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_dsc_375_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC 3.75:1 dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x78f>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x750>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 03 02 02 04 00 0b 08]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 11 c1 09 20 00 10 02 00 02 68 01 bb 00 0a 06 67 04 c5 39 01 00 00 00 00 03 c2 10 f0 15 01 00 00 00 00 02 c0 03 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 05 06 02 04 00 13 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_cmd { | |
| qcom,poms-align-panel-vsync; | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-t-clk-post = <0x03>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-t-clk-pre = <0x27>; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x78d>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x750>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@7 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x07>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 4a 13 14 28 24 12 14 11 02 04 00 39 18]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@13 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0d>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 06 07 02 04 00 16 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@5 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0xb4>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,mdss-dsi-panel-jitter = <0x02 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x05>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,dsi-wd-ltj-max-jitter = <0x04 0x01>; | |
| qcom,dsi-wd-ltj-time-sec = <0xe10>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,dsi-wd-jitter-enable; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 69 1d 1d 35 2f 1b 1d 18 02 04 00 51 21]; | |
| qcom,disable-rsc-solver; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@11 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x18>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0b>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 01 01 02 04 00 08 06]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@3 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x03>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x348>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 29 0a 0b 1b 26 0a 0b 0a 02 04 00 21 10]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,panel-roi-alignment = <0x168 0x14 0x168 0x14 0x168 0x14>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-video-mode; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x6e>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x6e>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 07 07 02 04 00 16 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x5a>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x6e>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@8 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x01>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x08>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 00 01 02 04 00 05 05]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@6 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0xf0>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,mdss-dsi-panel-jitter = <0x02 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x06>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,dsi-wd-ltj-max-jitter = <0x04 0x01>; | |
| qcom,dsi-wd-ltj-time-sec = <0xe10>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,dsi-wd-jitter-enable; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 89 26 27 42 39 25 27 1f 02 04 00 69 2a]; | |
| qcom,disable-rsc-solver; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@12 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0c>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 02 01 02 04 00 09 07]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@4 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x04>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e 0f 0d 02 04 00 2d 13]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@10 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x0a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0a>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 01 01 02 04 00 07 06]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,mdss-dsi-panel-jitter = <0x02 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,dsi-wd-ltj-max-jitter = <0x04 0x01>; | |
| qcom,dsi-wd-ltj-time-sec = <0xe10>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,dsi-wd-jitter-enable; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a 0a 0a 02 04 00 1f 0f]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x21c 0x28 0x21c 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,video-mode-switch-in-commands = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 39 01 00 00 00 00 06 b2 00 5d 04 80 49 15 01 00 00 00 00 02 3d 10 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 55 0c]; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,vid-on-commands = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-panel-jitter = <0x02 0x01>; | |
| qcom,cmd-mode-switch-out-commands = <0x39010000 0x3b0 0xa5000701 0x00 0x2010039 0x1000000 0x6b200 0x5d010249>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-video-mode; | |
| cell-index = <0x00>; | |
| qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,dsi-wd-ltj-max-jitter = <0x04 0x01>; | |
| qcom,dsi-wd-ltj-time-sec = <0xe10>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,dsi-wd-jitter-enable; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,cmd-on-commands = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 07 07 02 04 00 16 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-cmd-mode; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,cmd-mode-switch-in-commands = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 39 01 00 00 00 00 06 b2 00 5d 04 80 49 15 01 00 00 00 00 02 3d 11 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 55 0b]; | |
| qcom,video-mode-switch-out-commands = <0x39010000 0x3b0 0xa5000701 0x00 0x2010039 0x1000000 0x6b200 0x5d048049>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@9 { | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x05>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x09>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [03 06 00 00 0d 1a 01 00 01 02 04 00 06 05]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ext_bridge_1080p { | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "ext video mode dsi bridge"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-t-clk-post = <0x03>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-ext-bridge-mode; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-force-clock-lane-hs; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x24>; | |
| phandle = <0x78c>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x2c>; | |
| qcom,mdss-dsi-panel-height = <0x438>; | |
| qcom,mdss-dsi-h-front-porch = <0x58>; | |
| qcom,mdss-dsi-h-back-porch = <0x94>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x780>; | |
| qcom,mdss-dsi-v-pulse-width = <0x05>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 08 08 02 04 1a 0c 00]; | |
| qcom,mdss-dsi-v-back-porch = <0x24>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x04>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video { | |
| qcom,mdss-dsi-bl-min-level = <0x0a>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "vtdr6130 amoled qsync video mode dsi visionox panel with DSC"; | |
| qcom,esd-check-enabled; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; | |
| qcom,qsync-enable; | |
| qcom,platform-reset-gpio = <0x33 0x85 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| phandle = <0x79a>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-inverted-dbv; | |
| qcom,mdss-brightness-max-level = <0x1fff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 01 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_qsync_wqhd_video { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Sharp 2k video mode qsync dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x86>; | |
| qcom,esd-check-enabled; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0x1361>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; | |
| qcom,qsync-enable; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| phandle = <0x77f>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x83390100 0x11 0xc1892800 0x8020002 0x6800d500 0xa0db709 0x89390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x50>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 06 06 02 04 00 14 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0xa30>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_lt9611_720p_video { | |
| qcom,dsi-sec-phy-num = <0x00>; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x83>; | |
| qcom,dsi-sec-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "lt9611 video mode dsi panel without DSC"; | |
| qcom,mdss-pan-physical-height-dimension = <0x4a>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-ext-bridge-mode; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x14>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-force-clock-lane-hs; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x79d>; | |
| qcom,dsi-select-sec-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,mdss-dsi-panel-height = <0x2d0>; | |
| qcom,mdss-dsi-h-front-porch = <0x6e>; | |
| qcom,mdss-dsi-h-back-porch = <0xdc>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x05>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 1e 04 04 03 02 04 00 0f 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x14>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x05>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ili9881d_720p_video { | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "ili9881d video mode dsi panel without DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bl-pwm-pmi; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-reset-gpio = <0x33 0xce 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,platform-mipi-vdd = <0x33 0x20 0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,bl-pmic-pwm-period-usecs = <0x64>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x79b>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x1f>; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x4ff 0x98810339 0x1000000 0x20100 0x39010000 0x202 0x390100 0x02 0x3733901 0x00 0x2040039 0x1000000 0x20500 0x39010000 0x206 0xa390100 0x02 0x7003901 0x00 0x2080039 0x1000000 0x20901 0x39010000 0x20a 0x390100 0x02 0xb003901 0x00 0x20c0139 0x1000000 0x20d00 0x39010000 0x20e 0x390100 0x02 0xf1d3901 0x00 0x2100d39 0x1000000 0x21100 0x39010000 0x212 0x390100 0x02 0x13003901 0x00 0x2140039 0x1000000 0x21500 0x39010000 0x216 0x390100 0x02 0x17003901 0x00 0x2180039 0x1000000 0x21900 0x39010000 0x21a 0x390100 0x02 0x1b003901 0x00 0x21c0039 0x1000000 0x21d00 0x39010000 0x21e 0x40390100 0x02 0x1f803901 0x00 0x2200639 0x1000000 0x22102 0x39010000 0x222 0x390100 0x02 0x23003901 0x00 0x2240039 0x1000000 0x22500 0x39010000 0x226 0x390100 0x02 0x27003901 0x00 0x2283339 0x1000000 0x22903 0x39010000 0x22a 0x390100 0x02 0x2b003901 0x00 0x22c0039 0x1000000 0x22d00 0x39010000 0x22e 0x390100 0x02 0x2f003901 0x00 0x2300039 0x1000000 0x23100 0x39010000 0x232 0x390100 0x02 0x33003901 0x00 0x2340439 0x1000000 0x23500 0x39010000 0x236 0x390100 0x02 0x37003901 0x00 0x2383c39 0x1000000 0x23935 0x39010000 0x23a 0x1390100 0x02 0x3b403901 0x00 0x23c0039 0x1000000 0x23d01 0x39010000 0x23e 0x390100 0x02 0x3f003901 0x00 0x2400039 0x1000000 0x24188 0x39010000 0x242 0x390100 0x02 0x43003901 0x00 0x2441f39 0x1000000 0x25001 0x39010000 0x251 0x23390100 0x02 0x52453901 0x00 0x2536739 0x1000000 0x25489 0x39010000 0x255 0xab390100 0x02 0x56013901 0x00 0x2572339 0x1000000 0x25845 0x39010000 0x259 0x67390100 0x02 0x5a893901 0x00 0x25bab39 0x1000000 0x25ccd 0x39010000 0x25d 0xef390100 0x02 0x5e113901 0x00 0x25f0139 0x1000000 0x26000 0x39010000 0x261 0x15390100 0x02 0x62143901 0x00 0x2630e39 0x1000000 0x2640f 0x39010000 0x265 0xc390100 0x02 0x660d3901 0x00 0x2670639 0x1000000 0x26802 0x39010000 0x269 0x7390100 0x02 0x6a023901 0x00 0x26b0239 0x1000000 0x26c02 0x39010000 0x26d 0x2390100 0x02 0x6e023901 0x00 0x26f0239 0x1000000 0x27002 0x39010000 0x271 0x2390100 0x02 0x72023901 0x00 0x2730239 0x1000000 0x27402 0x39010000 0x275 0x1390100 0x02 0x76003901 0x00 0x2771439 0x1000000 0x27815 0x39010000 0x279 0xe390100 0x02 0x7a0f3901 0x00 0x27b0c39 0x1000000 0x27c0d 0x39010000 0x27d 0x6390100 0x02 0x7e023901 0x00 0x27f0739 0x1000000 0x28002 0x39010000 0x281 0x2390100 0x02 0x82023901 0x00 0x2830239 0x1000000 0x28402 0x39010000 0x285 0x2390100 0x02 0x86023901 0x00 0x2870239 0x1000000 0x28802 0x39010000 0x289 0x2390100 0x02 0x8a023901 0x00 0x4ff9881 0x4390100 0x02 0x6d083901 0x00 0x26f0539 0x1000000 0x27000 0x39010000 0x271 0x390100 0x02 0x820f3901 0x00 0x2840f39 0x1000000 0x2850d 0x39010000 0x232 0xac390100 0x02 0x8c803901 0x00 0x23cf539 0x1000000 0x23a24 0x39010000 0x2b5 0x7390100 0x02 0x31453901 0x00 0x2883339 0x1000000 0x4ff98 0x81013901 0x00 0x2220939 0x1000000 0x23100 0x39010000 0x253 0x8a390100 0x02 0x55a23901 0x00 0x2508139 0x1000000 0x25185 0x39010000 0x260 0x20390100 0x02 0xa0003901 0x00 0x2a11a39 0x1000000 0x2a228 0x39010000 0x2a3 0x13390100 0x02 0xa4163901 0x00 0x2a52939 0x1000000 0x2a61d 0x39010000 0x2a7 0x1e390100 0x02 0xa8843901 0x00 0x2a91c39 0x1000000 0x2aa28 0x39010000 0x2ab 0x75390100 0x02 0xac1a3901 0x00 0x2ad1939 0x1000000 0x2ae4d 0x39010000 0x2af 0x22390100 0x02 0xb0283901 0x00 0x2b15439 0x1000000 0x2b266 0x39010000 0x2b3 0x39390100 0x02 0xc0003901 0x00 0x2c11a39 0x1000000 0x2c228 0x39010000 0x2c3 0x13390100 0x02 0xc4163901 0x00 0x2c52939 0x1000000 0x2c61d 0x39010000 0x2c7 0x1e390100 0x02 0xc8843901 0x00 0x2c91c39 0x1000000 0x2ca28 0x39010000 0x2cb 0x75390100 0x02 0xcc1a3901 0x00 0x2cd1939 0x1000000 0x2ce4d 0x39010000 0x2cf 0x22390100 0x02 0xd0283901 0x00 0x2d15439 0x1000000 0x2d266 0x39010000 0x2d3 0x39390100 0x04 0xff988100 0x39010000 0x235 0x390100 0x02 0x36030501 0x7800 0x2110005 0x1000014 0x22900>; | |
| qcom,mdss-dsi-h-front-porch = <0x3c>; | |
| qcom,mdss-dsi-h-back-porch = <0x5a>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 04 03 02 04 00 0e 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x18>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x18>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled video mode dsi visionox panel with DSC"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,panel-cphy-mode; | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| phandle = <0x788>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 86 cf 64 0b 00 22 00 cd 03 33 04 00 0b 77 01 01 01 02 02 03 03 04 04 04 04 05 00 00 00 3b 00 3b 01 64 01 64 01 64 01 64 01 64 01 64 03 ff 03 ff 03 ff 00 00 00 3b 00 3b 01 64 01 64 01 64 01 64 01 64 01 64 03 ff 03 ff 03 ff 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 19 19 19 19 19 19 19 19 19 19 19 19 00 00 00 43 00 43 01 98 01 98 06 61 06 61 0f f6 0f f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 39 01 00 00 00 00 09 d1 05 00 21 02 24 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 f0 0f 00 40 00 00 00 00 00 00 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 15 1f 06 19 07 02 04 00 00 00]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_dual_sim_dsc_375_cmd { | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "Sim dual cmd mode DSC 3.75:1 dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,cmd-sync-wait-broadcast; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x793>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x750>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@15 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x10>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x168>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 03 02 02 04 00 0a 08]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@7 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x08>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 02 02 02 04 00 0a 07]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@13 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0e>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x168>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 01 02 02 04 00 08 06]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@5 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x06>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 03 03 02 04 00 0d 08]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@11 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0c>; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x4ec>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x9d8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 07 07 02 04 00 17 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@3 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x04>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 01 02 02 04 00 08 06]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@1 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 06 07 02 04 00 15 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@16 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x11>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 05 06 02 04 00 12 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@8 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x09>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 04 03 02 04 00 0d 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@14 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0f>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x168>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 02 02 02 04 00 0a 07]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@6 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x07>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 04 03 02 04 00 0f 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@12 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0d>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x168>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 01 01 02 04 00 07 06]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@4 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x05>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 02 02 02 04 00 0a 07]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@10 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0b>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 06 07 02 04 00 16 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 09 09 02 04 00 1d 0e]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 04 03 02 04 00 0d 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@17 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x12>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@9 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0a>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 05 06 02 04 00 12 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_vtdr6130_fhd_plus_vid { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-bl-min-level = <0x0a>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "vtdr6130 amoled video mode dsi visionox panel with DSC"; | |
| qcom,esd-check-enabled; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,qsync-enable; | |
| qcom,platform-reset-gpio = <0x33 0x85 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,panel-sec-supply-entries = <0x750>; | |
| qcom,dsi-dyn-clk-enable; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| phandle = <0x778>; | |
| qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,dsi-supported-qsync-min-fps-list = <0x50 0x46 0x3c 0x32>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-inverted-dbv; | |
| qcom,mdss-brightness-max-level = <0x1fff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 01 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,dsi-dyn-clk-list = <0x32838600 0x32569f50 0x3229b8a0>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_cmd_sim_panel_au { | |
| qcom,mdss-dsi-bl-min-level = <0x0a>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "cmd mode dsi sim panel au"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-reset-gpio = <0x33 0x85 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,vert-padding-value = <0xb7c>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x795>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-inverted-dbv; | |
| qcom,mdss-brightness-max-level = <0x1fff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 07 ff 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_video { | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-t-clk-post = <0x04>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| phandle = <0x78e>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x750>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-height = <0x1e0>; | |
| qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x08>; | |
| qcom,mdss-dsi-h-back-porch = <0x08>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x280>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 01 01 02 04 00 06 06]; | |
| qcom,mdss-dsi-v-back-porch = <0x06>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "mmcx"; | |
| qcom,supply-max-voltage = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x786>; | |
| qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 06 06 02 04 00 14 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 00 00 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 04 03 02 04 00 0e 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ch13726a_amoled_video { | |
| qcom,dsi-sec-phy-num = <0x00>; | |
| qcom,mdss-dsi-bypass-ram-switch; | |
| qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-bl-min-level = <0x0a>; | |
| qcom,platform-sec-reset-gpio = <0x33 0x85 0x00>; | |
| qcom,dsi-sec-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "ch13726a video mode dsi boe panel with DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-bl-max-level = <0xffff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; | |
| qcom,platform-mipi-vdd = <0x33 0x8f 0x00>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,panel-sec-supply-entries = <0x751>; | |
| qcom,dsi-dyn-clk-enable; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x78 0x3c>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| phandle = <0x75e>; | |
| qcom,dsi-select-sec-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-inverted-dbv; | |
| qcom,mdss-brightness-max-level = <0xfff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,video-mode-bypass-ram-commands-state = "dsi_lp_mode"; | |
| qcom,video-mode-pass-ram-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x4d8>; | |
| qcom,mdss-dsi-on-command = [05 01 00 00 78 00 02 11 00 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x0c>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-bypass-ram-command = <0x5010000 0x228 0x390100 0x02 0xf0503901 0x00 0x2b90005 0x1000000 0x22900>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,dsi-dyn-clk-list = <0x3c42a2c0 0x1e19b040>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 16 21 07 07 07 02 04 00 17 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,mdss-dsi-ram-command = <0x5010000 0x228 0x390100 0x02 0xf0503901 0x00 0x2b91105 0x1000000 0x22900>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_dual_sim_cmd { | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; | |
| qcom,qsync-enable; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,cmd-sync-wait-broadcast; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x791>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x750>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,bl-dcs-cmd-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-display-timings { | |
| timing@3 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x28>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| cell-index = <0x03>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a 0a 0a 02 04 00 1f 0f]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x02 0x01>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x1c>; | |
| qcom,mdss-dsi-h-back-porch = <0x04>; | |
| qcom,dsi-wd-ltj-max-jitter = <0x04 0x01>; | |
| qcom,dsi-wd-ltj-time-sec = <0xe10>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,dsi-wd-jitter-enable; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-mdp-transfer-time-us-min = <0x1af4>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 07 08 02 04 00 18 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-mdp-transfer-time-us-max = <0x1edc>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@4 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x50>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| cell-index = <0x04>; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x9d8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 18 14 02 04 00 43 1c]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| cell-index = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0x5a0>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x2c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 07 07 02 04 00 17 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x02 0x01>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,dsi-wd-ltj-max-jitter = <0x04 0x01>; | |
| qcom,dsi-wd-ltj-time-sec = <0xe10>; | |
| qcom,dsi-wd-jitter-enable; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x9d8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-mdp-transfer-time-us-min = <0x36b0>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 12 0f 02 04 00 35 16]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-mdp-transfer-time-us-max = <0x3e80>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_dsc_10b_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC3:1 10bit dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x790>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x750>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x1e>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@7 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x0a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x07>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 01 01 02 04 00 07 06]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@5 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x05>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 06 06 02 04 00 13 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@11 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0b>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 06 07 02 04 00 16 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@3 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0xb4>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x03>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 11 c1 09 20 00 10 02 00 02 68 01 bb 00 0a 06 67 04 c5 39 01 00 00 00 00 03 c2 10 f0 15 01 00 00 00 00 02 c0 03 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 16 08 08 08 02 04 00 1a 0d]; | |
| qcom,disable-rsc-solver; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x01>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 03 02 02 04 00 0c 08]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@8 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x18>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x08>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 01 01 02 04 00 08 06]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@6 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x01>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x06>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 00 01 02 04 00 05 05]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@4 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0xf0>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x04>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 11 c1 09 20 00 10 02 00 02 68 01 bb 00 0a 06 67 04 c5 39 01 00 00 00 00 03 c2 10 f0 15 01 00 00 00 00 02 c0 03 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a 0b 0a 02 04 00 21 0f]; | |
| qcom,disable-rsc-solver; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@10 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x0a>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e 0f 0d 02 04 00 2d 13]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x02>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 11 c1 09 20 00 10 02 00 02 68 01 bb 00 0a 06 67 04 c5 39 01 00 00 00 00 03 c2 10 f0 15 01 00 00 00 00 02 c0 03 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 08 08 02 04 00 19 0d]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 11 c1 09 20 00 10 02 00 02 68 01 bb 00 0a 06 67 04 c5 39 01 00 00 00 00 03 c2 10 f0 15 01 00 00 00 00 02 c0 03 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 f0 00 01 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 05 06 02 04 00 13 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| timing@9 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x09>; | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 02 01 02 04 00 09 07]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-version = <0x12>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_qsync_wqhd_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Sharp 2k cmd mode qsync dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x86>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0x1361>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-schedule-line = <0x05>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x77e>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@5 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x05>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x50>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 c0 85 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 00 00 00 00 00 03 c2 10 f0 39 00 00 00 00 00 02 ff 24 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 16 03 39 00 00 00 00 00 02 17 70 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 00 00 00 00 00 02 62 02 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 02 02 02 04 00 0a 07]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x08 0x08 0x08 0x438 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@3 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,video-to-cmd-mode-post-switch-commands-state = "dsi_lp_mode"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x03>; | |
| qcom,cmd-to-video-mode-switch-commands = <0x39010000 0x52a 0x2cf 0x39010000 0x52b 0x9ff>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 c0 83 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 00 00 00 00 00 03 c2 10 f0 39 00 00 00 00 00 02 ff 24 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 16 00 39 00 00 00 00 00 02 17 10 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 00 00 00 00 00 02 62 03 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 06 06 02 04 00 14 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0x08 0x08 0x08 0x5a0 0x08>; | |
| qcom,cmd-to-video-mode-post-switch-commands = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 bb 13 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 06]; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@1 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 c0 85 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 00 00 00 00 00 03 c2 10 f0 39 00 00 00 00 00 02 ff 24 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 16 0a 39 00 00 00 00 00 02 17 30 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 00 00 00 00 00 02 62 01 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1c 02 02 01 02 04 00 09 07]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x08 0x08 0x08 0x438 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@4 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x04>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 00 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 c0 85 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 00 00 00 00 00 03 c2 10 f0 39 00 00 00 00 00 02 ff 24 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 16 00 39 00 00 00 00 00 02 17 10 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 00 00 00 00 00 02 62 00 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1c 04 03 02 02 04 00 0c 08]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x08 0x08 0x08 0x438 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@2 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 c0 83 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 00 00 00 00 00 03 c2 10 f0 39 00 00 00 00 00 02 ff 24 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 16 03 39 00 00 00 00 00 02 17 70 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 00 00 00 00 00 02 62 02 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 12 1e 04 05 03 02 04 00 0f 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0x08 0x08 0x08 0x5a0 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,video-mode-switch-in-commands = [39 00 00 40 00 00 02 ff 10 39 00 00 40 00 00 02 fb 01 39 00 00 00 00 00 02 bb 13]; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,vid-on-commands = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 05 be 00 10 00 10 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,cmd-mode-switch-out-commands = <0x39000040 0x52a 0x2cf 0x39000000 0x52b 0x9ff>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-video-mode; | |
| cell-index = <0x00>; | |
| qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-timing-switch-command = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 c0 83 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 00 00 00 00 00 03 c2 10 f0 39 00 00 00 00 00 02 ff 24 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 16 0a 39 00 00 00 00 00 02 17 30 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 00 00 00 00 00 02 62 01 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,cmd-on-commands = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1c 04 03 02 02 04 00 0c 08]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0x08 0x08 0x08 0x5a0 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-cmd-mode; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,cmd-mode-switch-in-commands = [39 00 00 40 00 00 02 ff 10 39 00 00 40 00 00 02 fb 01 39 00 00 00 00 00 02 bb 10]; | |
| qcom,video-mode-switch-out-commands = [39 00 00 40 00 00 02 ff 10 39 00 00 40 00 00 02 fb 01 39 00 00 00 00 00 02 bb 10]; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_4k_dsc_video { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x47>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x81>; | |
| qcom,esd-check-enabled; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x77>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x64 0x00 0x64 0x01 0x64>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x77>; | |
| phandle = <0x77b>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 10 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 06 07 02 04 00 15 0b]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_truly_wqxga_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi truly panel without DSC"; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| phandle = <0x781>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-panel-jitter = <0x01 0x01>; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 08 02 04 00 19 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd { | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-bl-min-level = <0x0a>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "vtdr6130 amoled qsync cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; | |
| qcom,qsync-enable; | |
| qcom,platform-reset-gpio = <0x33 0x85 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x799>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-inverted-dbv; | |
| qcom,mdss-brightness-max-level = <0x1fff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-qsync-off-commands = <0x39010000 0x3f0 0xaa103901 0x00 0x2bb0039 0x1000000 0x3f0aa 0x13390100 0x18 0xce091109 0x1108c107 0xfa05a400 0x3c003400 0x24000c00 0xc040035>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-qsync-on-commands = [39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 3c 00 3c 00 0c 00 0c 04 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 0c bb 00 4c 00 01 ff 01 32 01 6e 01 6e 39 01 00 00 00 00 02 bb 01]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 09 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd { | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "Sharp qhd cmd mode dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0x1361>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x77c>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0xc30>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 df 97 51 e8 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 05 d9 00 00 00 04 39 01 00 00 00 00 03 bc 3f 66 39 01 00 00 00 00 04 dd 66 19 b7 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a 00 00 39 01 00 00 00 00 03 c1 58 10 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 45 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 00 0b 10 39 01 00 00 00 00 34 c6 00 12 88 00 08 00 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 05 05 05 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 49 00 99 01 49 01 49 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f af af af af af af ff ff ff ff ff ff ff ff aa ff ff ff ff ff ff ff ff ff ff ff 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f af af af af af af ff ff ff ff ff ff ff ff aa ff ff ff ff ff ff ff ff ff ff ff 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 60 00 00 20 00 01 02 01 40 00 73 00 05 01 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 02 02 04 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 00 00 00 00 00 01 49 01 49 00 00 07 40 40 07 99 00 99 00 00 00 00 03 00 00 00 00 00 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 39 01 00 00 00 00 02 de 02 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d 94 18 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 40 40 39 01 00 00 00 00 02 c7 08 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 54 a6 82 d0 04 3c 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 14 9d 0a 29 39 01 00 00 00 00 02 de 03 39 01 00 00 00 00 03 b0 04 f0 39 01 00 00 00 00 02 b2 10 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 39 01 00 00 00 00 02 b5 68 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 0f 00 16 11 bf 39 01 00 00 00 00 02 de 04 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 b6 00 39 01 00 00 00 00 03 bf 02 ff 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 00 00 00 00 00 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 07 00 05 02 02 39 01 00 00 00 00 2c ed 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 de 06 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 e7 39 01 00 00 00 00 02 bd 20 39 01 00 00 00 00 02 de 07 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 39 01 00 00 00 00 05 b2 00 00 00 00 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 ab 10 32 54 76 98 ba 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 12 a9 6b 87 43 05 21 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 9a 0e 21 43 65 87 a9 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 01 92 ba 76 38 54 10 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 ab 10 32 54 76 98 ba 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 12 a9 6b 87 43 05 21 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 9a 0e 21 43 65 87 a9 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b 67 c2 e4 10 38 5a 76 39 01 00 00 00 00 04 bb 1e cc 66 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 4a 2b 04 e5 c6 a7 80 61 42 23 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 4a 6b 84 a5 c6 e7 00 21 42 63 39 01 00 00 00 00 05 be 3f ff ff ff 39 01 00 00 00 00 05 bf 3e ff ff ff 39 01 00 00 00 00 05 c0 2b ff ff ff 39 01 00 00 00 00 05 c1 1a 7f fb ff 39 01 00 00 00 00 05 c2 1a ff ff ff 39 01 00 00 00 00 05 c3 15 ff ff ff 39 01 00 00 00 00 05 c4 15 ff ff ff 39 01 00 00 00 00 05 c5 00 ff ff ff 39 01 00 00 00 00 03 c6 00 00 39 01 00 00 00 00 03 c7 00 00 39 01 00 00 00 00 05 c8 22 00 00 00 39 01 00 00 00 00 0c c9 10 f1 f0 ff ff ff ff ff ff ee 02 39 01 00 00 00 00 02 de 08 39 01 00 00 00 00 1a b2 52 07 11 01 13 41 02 01 11 11 0e 15 15 15 0e 0e 0e 0e 0e 0e 0e 0e 0e 15 15 39 01 00 00 00 00 02 b6 18 39 01 00 00 00 00 02 de 0a 39 01 00 00 00 00 04 d5 3f 78 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 36 00 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 be 2c e0 39 01 00 00 00 00 03 c0 27 78 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 33 0c 39 01 00 00 00 00 05 b0 01 23 06 09 39 01 00 00 78 00 01 11 39 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x48>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = <0x39010000 0x2de 0x390100 0x34 0xc6001288 0x8000b 0x1202530 0x1490149 0x00 0x00 0x00 0x00 0x00 0x300 0x4501 0x454b024b 0x5050505>; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04 04 03 02 04 00 03 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [39 01 00 00 00 00 02 de 00 05 01 00 00 05 00 01 28 05 01 00 00 78 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x27>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xc30>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 df 97 51 e8 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 05 d9 00 00 00 04 39 01 00 00 00 00 03 bc 3f 66 39 01 00 00 00 00 04 dd 66 19 b7 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a 00 00 39 01 00 00 00 00 03 c1 58 10 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 45 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 00 0b 10 39 01 00 00 00 00 34 c6 00 12 44 00 08 00 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 05 05 05 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 49 00 99 01 49 01 49 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f af af af af af af ff ff ff ff ff ff ff ff aa ff ff ff ff ff ff ff ff ff ff ff 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f af af af af af af ff ff ff ff ff ff ff ff aa ff ff ff ff ff ff ff ff ff ff ff 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 60 00 00 20 00 01 02 01 40 00 73 00 05 01 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 02 02 04 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 00 00 00 00 00 01 49 01 49 00 00 07 40 40 07 99 00 99 00 00 00 00 03 00 00 00 00 00 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 39 01 00 00 00 00 02 de 02 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d 94 18 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 40 40 39 01 00 00 00 00 02 c7 08 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 54 a6 82 d0 04 3c 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 14 9d 0a 29 39 01 00 00 00 00 02 de 03 39 01 00 00 00 00 03 b0 04 f0 39 01 00 00 00 00 02 b2 10 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 39 01 00 00 00 00 02 b5 68 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 0f 00 16 11 bf 39 01 00 00 00 00 02 de 04 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 b6 00 39 01 00 00 00 00 03 bf 02 ff 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 00 00 00 00 00 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 07 00 05 02 02 39 01 00 00 00 00 2c ed 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 de 06 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 e7 39 01 00 00 00 00 02 bd 20 39 01 00 00 00 00 02 de 07 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 39 01 00 00 00 00 05 b2 00 00 00 00 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 ab 10 32 54 76 98 ba 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 12 a9 6b 87 43 05 21 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 9a 0e 21 43 65 87 a9 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 01 92 ba 76 38 54 10 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 ab 10 32 54 76 98 ba 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 12 a9 6b 87 43 05 21 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 9a 0e 21 43 65 87 a9 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b 67 c2 e4 10 38 5a 76 39 01 00 00 00 00 04 bb 1e cc 66 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 4a 2b 04 e5 c6 a7 80 61 42 23 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 4a 6b 84 a5 c6 e7 00 21 42 63 39 01 00 00 00 00 05 be 3f ff ff ff 39 01 00 00 00 00 05 bf 3e ff ff ff 39 01 00 00 00 00 05 c0 2b ff ff ff 39 01 00 00 00 00 05 c1 1a 7f fb ff 39 01 00 00 00 00 05 c2 1a ff ff ff 39 01 00 00 00 00 05 c3 15 ff ff ff 39 01 00 00 00 00 05 c4 15 ff ff ff 39 01 00 00 00 00 05 c5 00 ff ff ff 39 01 00 00 00 00 03 c6 00 00 39 01 00 00 00 00 03 c7 00 00 39 01 00 00 00 00 05 c8 22 00 00 00 39 01 00 00 00 00 0c c9 10 f1 f0 ff ff ff ff ff ff ee 02 39 01 00 00 00 00 02 de 08 39 01 00 00 00 00 1a b2 52 07 11 01 13 41 02 01 11 11 0e 15 15 15 0e 0e 0e 0e 0e 0e 0e 0e 0e 15 15 39 01 00 00 00 00 02 b6 18 39 01 00 00 00 00 02 de 0a 39 01 00 00 00 00 04 d5 3f 78 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 36 00 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 be 2c e0 39 01 00 00 00 00 03 c0 27 78 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 33 0c 39 01 00 00 00 00 05 b0 01 23 06 09 39 01 00 00 78 00 01 11 39 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x48>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = <0x39010000 0x2de 0x390100 0x34 0xc6001244 0x8000b 0x1202530 0x1490149 0x00 0x00 0x00 0x00 0x00 0x300 0x4501 0x454b024b 0x5050505>; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 07 07 02 04 00 17 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [39 01 00 00 00 00 02 de 00 05 01 00 00 05 00 01 28 05 01 00 00 78 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x27>; | |
| qcom,mdss-mdp-transfer-time-us = <0x1efd>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-sspp-vig-blocks { | |
| vcm@1 { | |
| qcom,sde-fp16-unmult = <0x280 0x10000>; | |
| cell-index = <0x01>; | |
| qcom,sde-fp16-gc = <0x280 0x10000>; | |
| qcom,sde-fp16-csc = <0x280 0x10000>; | |
| qcom,sde-fp16-igc = <0x280 0x10000>; | |
| }; | |
| vcm@0 { | |
| qcom,sde-vig-igc = <0x1d00 0x60000>; | |
| qcom,sde-fp16-unmult = <0x200 0x10000>; | |
| qcom,sde-vig-top-off = <0xa00>; | |
| cell-index = <0x00>; | |
| qcom,sde-vig-gamut = <0x1d00 0x60001>; | |
| qcom,sde-fp16-gc = <0x200 0x10000>; | |
| qcom,sde-vig-qseed-size = <0xe0>; | |
| qcom,sde-fp16-csc = <0x200 0x10000>; | |
| qcom,sde-fp16-igc = <0x200 0x10000>; | |
| qcom,sde-vig-csc-off = <0x1a00>; | |
| qcom,sde-vig-inverse-pma; | |
| qcom,sde-vig-qseed-off = <0xa00>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_dual_sim_video { | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; | |
| qcom,qsync-enable; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-broadcast-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0xc8 0x01 0x14>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| phandle = <0x792>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x5a0>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x2c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,panel-cphy-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x789>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-rx-eot-ignore; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 00 00 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-dspp-blocks { | |
| qcom,sde-dspp-memcolor = <0x880 0x10007>; | |
| qcom,sde-dspp-gc = <0x17c0 0x10008>; | |
| qcom,sde-dspp-pcc = <0x1700 0x40000>; | |
| qcom,sde-dspp-igc = <0x1260 0x40000>; | |
| qcom,sde-dspp-hist = <0x800 0x10007>; | |
| qcom,sde-dspp-vlut = <0xa00 0x10008>; | |
| qcom,sde-dspp-dither = <0x82c 0x10007>; | |
| qcom,sde-dspp-gamut = <0x1000 0x40003>; | |
| qcom,sde-dspp-sixzone = <0x900 0x20000>; | |
| qcom,sde-dspp-hsic = <0x800 0x10007>; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_video { | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled video mode dsi visionox panel without DSC"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,panel-cphy-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; | |
| qcom,qsync-enable; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| phandle = <0x797>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 06 b6 6c 00 06 23 92 39 01 00 00 00 00 02 b4 20 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 02 f7 00 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1a 27 09 19 09 02 04 00 00 00]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_sec_hd_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "sim hd command mode secondary dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-post-init-delay = <0x01>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-bl-max-level = <0x3ff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,panel-sec-supply-entries = <0x751>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x794>; | |
| qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x750>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 04 03 02 04 00 0e 09]; | |
| qcom,mdss-dsi-v-back-porch = <0x02>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_truly_sl_wqxga_cmd { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 cmd dsi truly splitlink panel without DSC"; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,sublinks-count = <0x02>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,lanes-per-sublink = <0x02>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x796>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,split-link-enabled; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-panel-jitter = <0x01 0x01>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x10150100 0x02 0xfb011501 0x00 0x2ba0115 0x1000000 0x2ff20 0x15010000 0x2fb 0x1150100 0x02 0x11501 0x00 0x2015515 0x1000000 0x20245 0x15010000 0x205 0x40150100 0x02 0x6191501 0x00 0x2071e15 0x1000000 0x20b73 0x15010000 0x20c 0x73150100 0x02 0xeb01501 0x00 0x20fae15 0x1000000 0x211b8 0x15010000 0x213 0x150100 0x02 0x58801501 0x00 0x2590115 0x1000000 0x25a00 0x15010000 0x25b 0x1150100 0x02 0x5c801501 0x00 0x25d8115 0x1000000 0x25e00 0x15010000 0x25f 0x1150100 0x02 0x72311501 0x00 0x2680315 0x1000000 0x2ff24 0x15010000 0x2fb 0x1150100 0x02 0x1c1501 0x00 0x2010b15 0x1000000 0x2020c 0x15010000 0x203 0x1150100 0x02 0x40f1501 0x00 0x2051015 0x1000000 0x20610 0x15010000 0x207 0x10150100 0x02 0x8891501 0x00 0x2098a15 0x1000000 0x20a13 0x15010000 0x20b 0x13150100 0x02 0xc151501 0x00 0x20d1515 0x1000000 0x20e17 0x15010000 0x20f 0x17150100 0x02 0x101c1501 0x00 0x2110b15 0x1000000 0x2120c 0x15010000 0x213 0x1150100 0x02 0x140f1501 0x00 0x2151015 0x1000000 0x21610 0x15010000 0x217 0x10150100 0x02 0x18891501 0x00 0x2198a15 0x1000000 0x21a13 0x15010000 0x21b 0x13150100 0x02 0x1c151501 0x00 0x21d1515 0x1000000 0x21e17 0x15010000 0x21f 0x17150100 0x02 0x20401501 0x00 0x2210115 0x1000000 0x22200 0x15010000 0x223 0x40150100 0x02 0x24401501 0x00 0x2256d15 0x1000000 0x22640 0x15010000 0x227 0x40150100 0x02 0xe0001501 0x00 0x2dc2115 0x1000000 0x2dd22 0x15010000 0x2de 0x7150100 0x02 0xdf071501 0x00 0x2e36d15 0x1000000 0x2e107 0x15010000 0x2e2 0x7150100 0x02 0x29d81501 0x00 0x22a2a15 0x1000000 0x24b03 0x15010000 0x24c 0x11150100 0x02 0x4d101501 0x00 0x24e0115 0x1000000 0x24f01 0x15010000 0x250 0x10150100 0x02 0x51001501 0x00 0x2528015 0x1000000 0x25300 0x15010000 0x256 0x150100 0x02 0x54071501 0x00 0x2580715 0x1000000 0x25525 0x15010000 0x25b 0x43150100 0x02 0x5c001501 0x00 0x25f7315 0x1000000 0x26073 0x15010000 0x263 0x22150100 0x02 0x64001501 0x00 0x2670815 0x1000000 0x26804 0x15010000 0x272 0x2150100 0x02 0x7a801501 0x00 0x27b9115 0x1000000 0x27cd8 0x15010000 0x27d 0x60150100 0x02 0x7f151501 0x00 0x2751515 0x1000000 0x2b3c0 0x15010000 0x2b4 0x150100 0x02 0xb5001501 0x00 0x2780015 0x1000000 0x27900 0x15010000 0x280 0x150100 0x02 0x83001501 0x00 0x2930a15 0x1000000 0x2940a 0x15010000 0x28a 0x150100 0x02 0x9bff1501 0x00 0x29db015 0x1000000 0x29f63 0x15010000 0x298 0x10150100 0x02 0xec001501 0x00 0x2ff1015 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-panel-clockrate = <0x60152b00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 33 0e 0e 2c 29 0d 0e 0d 02 04 00 2b 1c]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-sspp-dma-blocks { | |
| dgm@1 { | |
| qcom,sde-dma-igc = <0x1a00 0x50000>; | |
| qcom,sde-dma-gc = <0xc00 0x50000>; | |
| qcom,sde-fp16-unmult = <0x200 0x10000>; | |
| qcom,sde-dma-csc-off = <0x1800>; | |
| cell-index = <0x01>; | |
| qcom,sde-fp16-gc = <0x200 0x10000>; | |
| qcom,sde-fp16-csc = <0x200 0x10000>; | |
| qcom,sde-fp16-igc = <0x200 0x10000>; | |
| qcom,sde-dma-inverse-pma; | |
| }; | |
| dgm@0 { | |
| qcom,sde-dma-igc = <0xa00 0x50000>; | |
| qcom,sde-dma-gc = <0xc00 0x50000>; | |
| qcom,sde-fp16-unmult = <0x200 0x10000>; | |
| qcom,sde-dma-csc-off = <0x800>; | |
| cell-index = <0x00>; | |
| qcom,sde-fp16-gc = <0x200 0x10000>; | |
| qcom,sde-fp16-csc = <0x200 0x10000>; | |
| qcom,sde-fp16-igc = <0x200 0x10000>; | |
| qcom,sde-dma-top-off = <0x800>; | |
| qcom,sde-dma-inverse-pma; | |
| }; | |
| }; | |
| qcom,mdss_dsi_visionox_r66451_fhd_plus_sync_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox sync panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x78a>; | |
| qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-panel-clockrate = <0x1d98aa58>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 13 1e 05 05 04 02 04 00 10 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-mdp-transfer-time-us = <0x2847>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| cell-index = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-panel-clockrate = <0x1d98aa58>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 13 1e 05 05 04 02 04 00 10 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3d24>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35695b_truly_fhd_sl_cmd { | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "nt35695b truly fhd command mode split link dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,sublinks-count = <0x02>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-post-init-delay = <0x01>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,lanes-per-sublink = <0x02>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x798>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,split-link-enabled; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 01 15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-back-porch = <0x02>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35532_720p_video { | |
| qcom,mdss-dsi-bl-min-level = <0x0a>; | |
| qcom,dsi-phy-num = <0x01>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "nt35532 video mode dsi panel without DSC"; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk1", "pll_dsi_clk1"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,platform-reset-gpio = <0x33 0x89 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x88b8 0x6978 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,platform-mipi-vdd = <0x33 0x8e 0x00>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x14>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x78 0x3c>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| phandle = <0x779>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,platform-bklight-en-gpio = <0x33 0x34 0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-inverted-dbv; | |
| qcom,mdss-brightness-max-level = <0xfff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 9f 01 39 01 00 00 00 00 24 b3 00 e0 a0 10 c8 00 02 83 00 10 14 00 00 c3 00 10 14 00 00 e0 10 10 9c 00 00 e0 a0 10 c8 22 18 18 18 18 18 39 01 00 00 00 00 02 9f 07 39 01 00 00 00 00 08 b5 04 0c 08 0c 04 00 c4 39 01 00 00 00 00 10 d9 88 40 40 88 40 40 00 eb 00 00 00 00 00 00 00 39 01 00 00 00 00 08 ce 01 01 01 01 04 09 2c 39 01 00 00 00 00 02 48 01 39 01 00 00 00 00 02 48 31 39 01 00 00 00 00 03 9c a5 a5 39 01 00 00 00 00 03 fd 5a 5a 39 01 00 00 00 00 02 48 03 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 53 e0 39 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 39 01 00 00 00 00 02 9f 0f 39 01 00 00 00 00 02 ce 52 05 01 00 00 78 00 02 29 00 39 01 00 00 00 00 03 51 0d bb]; | |
| qcom,mdss-dsi-h-front-porch = <0x9c>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x17>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 08 08 02 04 00 1a 0d]; | |
| qcom,mdss-dsi-v-back-porch = <0x0f>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_qhd_plus_dsc_video { | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "Sharp qhd video mode dsi panel"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0x1361>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| phandle = <0x77d>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xc30>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 df 97 51 e8 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 05 d9 00 00 00 04 39 01 00 00 00 00 03 bc 3f 66 39 01 00 00 00 00 04 dd 66 19 b7 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a 00 00 39 01 00 00 00 00 03 c1 58 10 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 45 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 00 0b 10 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 05 05 05 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 49 00 99 01 49 01 49 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f af af af af af af ff ff ff ff ff ff ff ff aa ff ff ff ff ff ff ff ff ff ff ff 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f 1f af af af af af af ff ff ff ff ff ff ff ff aa ff ff ff ff ff ff ff ff ff ff ff 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 60 00 00 20 00 01 02 01 40 00 73 00 05 01 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 02 02 04 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 00 00 00 00 00 01 49 01 49 00 00 07 40 40 07 99 00 99 00 00 00 00 03 00 00 00 00 00 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 39 01 00 00 00 00 02 de 02 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d 94 18 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 40 40 39 01 00 00 00 00 02 c7 08 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 54 a6 82 d0 04 3c 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 14 9d 0a 29 39 01 00 00 00 00 02 de 03 39 01 00 00 00 00 03 b0 04 f0 39 01 00 00 00 00 02 b2 10 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 39 01 00 00 00 00 02 b5 68 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 0f 00 16 11 bf 39 01 00 00 00 00 02 de 04 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 b6 00 39 01 00 00 00 00 03 bf 02 ff 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 00 00 00 00 00 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 07 00 05 02 02 39 01 00 00 00 00 2c ed 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 de 06 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 e7 39 01 00 00 00 00 02 bd 20 39 01 00 00 00 00 02 de 07 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 39 01 00 00 00 00 05 b2 00 00 00 00 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 ab 10 32 54 76 98 ba 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 12 a9 6b 87 43 05 21 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 9a 0e 21 43 65 87 a9 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 01 92 ba 76 38 54 10 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 ab 10 32 54 76 98 ba 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 12 a9 6b 87 43 05 21 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 9a 0e 21 43 65 87 a9 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b 67 c2 e4 10 38 5a 76 39 01 00 00 00 00 04 bb 1e cc 66 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 4a 2b 04 e5 c6 a7 80 61 42 23 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 4a 6b 84 a5 c6 e7 00 21 42 63 39 01 00 00 00 00 05 be 3f ff ff ff 39 01 00 00 00 00 05 bf 3e ff ff ff 39 01 00 00 00 00 05 c0 2b ff ff ff 39 01 00 00 00 00 05 c1 1a 7f fb ff 39 01 00 00 00 00 05 c2 1a ff ff ff 39 01 00 00 00 00 05 c3 15 ff ff ff 39 01 00 00 00 00 05 c4 15 ff ff ff 39 01 00 00 00 00 05 c5 00 ff ff ff 39 01 00 00 00 00 03 c6 00 00 39 01 00 00 00 00 03 c7 00 00 39 01 00 00 00 00 05 c8 22 00 00 00 39 01 00 00 00 00 0c c9 10 f1 f0 ff ff ff ff ff ff ee 02 39 01 00 00 00 00 02 de 08 39 01 00 00 00 00 1a b2 52 07 11 01 13 41 02 01 11 11 0e 15 15 15 0e 0e 0e 0e 0e 0e 0e 0e 0e 15 15 39 01 00 00 00 00 02 b6 18 39 01 00 00 00 00 02 de 0a 39 01 00 00 00 00 04 d5 3f 78 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 36 00 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 be 2c e0 39 01 00 00 00 00 03 c0 27 78 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 33 0c 39 01 00 00 00 00 05 b0 01 23 06 09 39 01 00 00 78 00 01 11 39 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x48>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 07 07 02 04 00 17 0c]; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [39 01 00 00 00 00 02 de 00 05 01 00 00 05 00 01 28 05 01 00 00 78 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x27>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_lt8912b_1080p_video { | |
| qcom,dsi-sec-phy-num = <0x00>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,dsi-sec-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "lt8912b video mode dsi panel without DSC"; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-post-init-delay = <0x04>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-ext-bridge-mode; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x02 0x01 0x14>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-force-clock-lane-hs; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| phandle = <0x79f>; | |
| qcom,dsi-select-sec-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x2c>; | |
| qcom,mdss-dsi-panel-height = <0x438>; | |
| qcom,mdss-dsi-h-front-porch = <0x58>; | |
| qcom,mdss-dsi-h-back-porch = <0x94>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x780>; | |
| qcom,mdss-dsi-v-pulse-width = <0x05>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 08 08 02 04 00 1a 0d]; | |
| qcom,mdss-dsi-v-back-porch = <0x24>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x04>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_icna3520_dsc_cmd { | |
| qcom,mdss-dsi-bl-min-level = <0x0a>; | |
| qcom,dsi-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "icna3520 amoled panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "pll_byte_clk1", "pll_dsi_clk1"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xd55>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,platform-reset-gpio = <0x33 0x89 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,platform-mipi-vdd = <0x33 0x8e 0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x14>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,quec-refresh-120hz = <0x4c>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-force-clock-lane-hs; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x764>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x751>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,platform-bklight-en-gpio = <0x33 0x34 0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-inverted-dbv; | |
| qcom,mdss-brightness-max-level = <0xfff>; | |
| qcom,quec-refresh-60hz = <0x7d6>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 9c a5 a5 39 01 00 00 00 00 03 fd 5a 5a 39 01 00 00 00 00 02 48 00 39 01 00 00 00 00 02 53 e0 39 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 39 01 00 00 00 00 02 9f 00 39 01 00 00 00 00 07 b3 00 d8 00 1c 00 4c 39 01 00 00 00 00 02 9f 01 39 01 00 00 00 00 02 b2 00 39 01 00 00 00 00 02 9f 0d 39 01 00 00 00 00 02 b2 27 39 01 00 00 00 00 02 b6 03 39 01 00 00 00 00 02 bb 01 39 01 00 00 00 00 02 b2 24 39 01 00 00 0a 00 03 51 0d 70 39 01 00 00 00 00 03 51 0d 75 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x18>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x18>; | |
| qcom,mdss-dsi-timing-switch-command = <0x39010000 0x248 0x390100 0x02 0x9f003901 0x00 0x7b300d8 0x1c004c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x0c>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 05 06 02 04 00 13 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x1c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x1c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 9c a5 a5 39 01 00 00 00 00 03 fd 5a 5a 39 01 00 00 00 00 02 48 10 39 01 00 00 00 00 02 53 e0 39 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 39 01 00 00 00 00 02 9f 00 39 01 00 00 00 00 0f b3 00 db 00 1c 00 1c 00 00 db 00 1c 07 d6 00 39 01 00 00 00 00 02 9f 01 39 01 00 00 00 00 02 b2 00 39 01 00 00 00 00 02 9f 0d 39 01 00 00 00 00 02 b2 27 39 01 00 00 00 00 02 b6 03 39 01 00 00 00 00 02 bb 01 39 01 00 00 00 00 02 b2 24 39 01 00 00 0a 00 03 51 0d 70 39 01 00 00 00 00 03 51 0d 75 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x18>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x18>; | |
| qcom,mdss-dsi-timing-switch-command = <0x39010000 0x248 0x10390100 0x02 0x9f003901 0x00 0xfb300db 0x1c001c 0xdb00 0x1c07d600>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x0c>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 05 06 02 04 00 13 0a]; | |
| qcom,mdss-dsi-v-back-porch = <0x1c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x7d6>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_1080p_cmd { | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x40>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x75>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-clockrate = <0x32a9f880>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| phandle = <0x780>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x74f>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-panel-clockrate = <0x35a4e900>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 08 08 02 04 00 1a 0d]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-cdsp-loader { | |
| compatible = "qcom,cdsp-loader"; | |
| qcom,proc-img-to-load = "cdsp"; | |
| qcom,rproc-handle = <0x24>; | |
| }; | |
| dma_dev { | |
| memory-region = <0x80>; | |
| compatible = "qcom,iommu-dma"; | |
| }; | |
| apps-smmu@15000000 { | |
| #global-interrupts = <0x01>; | |
| #address-cells = <0x01>; | |
| dma-coherent; | |
| reg-names = "base", "tcu-base"; | |
| interrupts = <0x00 0x41 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x158 0x04 0x00 0x159 0x04 0x00 0x18b 0x04 0x00 0x18c 0x04 0x00 0x18d 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04 0x00 0x194 0x04 0x00 0x195 0x04 0x00 0x196 0x04 0x00 0x197 0x04 0x00 0x198 0x04 0x00 0x199 0x04 0x00 0x1a2 0x04 0x00 0x1a3 0x04 0x00 0x19c 0x04 0x00 0x1a5 0x04 0x00 0x2c2 0x04 0x00 0x1a7 0x04 0x00 0x1a8 0x04 0x00 0x1a9 0x04 0x00 0x2b1 0x04 0x00 0x2b2 0x04 0x00 0x2b3 0x04 0x00 0x2b4 0x04 0x00 0x2b5 0x04 0x00 0x2b6 0x04 0x00 0x2b7 0x04 0x00 0x2b8 0x04>; | |
| qcom,actlr = <0x18a0 0x00 0x103 0x18e0 0x00 0x103 0x800 0x20 0x01 0x1800 0xc0 0x01 0x1820 0x00 0x01 0x1860 0x00 0x01 0xc01 0x20 0x303 0xc02 0x20 0x303 0xc03 0x20 0x303 0xc04 0x20 0x303 0xc05 0x20 0x303 0xc06 0x20 0x303 0xc07 0x20 0x303 0xc08 0x20 0x303 0xc09 0x20 0x303 0xc0c 0x20 0x303 0xc0d 0x20 0x303 0xc0e 0x20 0x303 0xc0f 0x20 0x303 0x1961 0x00 0x303 0x1962 0x00 0x303 0x1963 0x00 0x303 0x1964 0x00 0x303 0x1965 0x00 0x303 0x1966 0x00 0x303 0x1967 0x00 0x303 0x1968 0x00 0x303 0x1969 0x00 0x303 0x196c 0x00 0x303 0x196d 0x00 0x303 0x196e 0x00 0x303 0x196f 0x00 0x303 0x19c1 0x10 0x303 0x19c2 0x10 0x303 0x19c3 0x10 0x303 0x19c4 0x10 0x303 0x19c5 0x10 0x303 0x19c6 0x10 0x303 0x19c7 0x10 0x303 0x19c8 0x10 0x303 0x19c9 0x10 0x303 0x19cc 0x10 0x303 0x19cd 0x10 0x303 0x19ce 0x10 0x303 0x19cf 0x10 0x303 0x1c00 0x02 0x01 0x1c01 0x00 0x01 0x1920 0x00 0x103 0x1923 0x00 0x103 0x1924 0x00 0x103 0x1940 0x00 0x103 0x1941 0x04 0x103 0x1943 0x00 0x103 0x1944 0x00 0x103 0x1947 0x00 0x103>; | |
| #size-cells = <0x01>; | |
| qcom,use-3-lvl-tables; | |
| #iommu-cells = <0x02>; | |
| compatible = "qcom,qsmmu-v500"; | |
| ranges; | |
| reg = <0x15000000 0x100000 0x151fe000 0x40>; | |
| phandle = <0x4c>; | |
| qcom,handoff-smrs = <0x1c00 0x02>; | |
| mdp_hf_qtb@17d0000 { | |
| interconnects = <0xec 0x14 0x4b 0x200>; | |
| reg-names = "base", "debugchain-base"; | |
| qcom,num-qtb-ports = <0x02>; | |
| qcom,stream-id-range = <0x1c00 0x400>; | |
| qcom,iova-width = <0x20>; | |
| compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; | |
| reg = <0x17d0000 0x1000 0x1783000 0x1000>; | |
| phandle = <0x404>; | |
| }; | |
| cam_hf_qtb@17d2000 { | |
| interconnects = <0xec 0x0b 0x4b 0x200>; | |
| reg-names = "base", "debugchain-base"; | |
| qcom,num-qtb-ports = <0x02>; | |
| qcom,stream-id-range = <0x800 0x400>; | |
| qcom,iova-width = <0x24>; | |
| compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; | |
| reg = <0x17d2000 0x1000 0x1783000 0x1000>; | |
| phandle = <0x3ff>; | |
| }; | |
| anoc_1_qtb@16f0000 { | |
| interconnects = <0xeb 0x09 0x4b 0x200>; | |
| reg-names = "base", "debugchain-base"; | |
| qcom,num-qtb-ports = <0x01>; | |
| qcom,stream-id-range = <0x00 0x400>; | |
| qcom,iova-width = <0x24>; | |
| compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; | |
| reg = <0x16f0000 0x1000 0x16e1100 0x1000>; | |
| phandle = <0x3fd>; | |
| }; | |
| anoc_2_qtb@171a000 { | |
| interconnects = <0xeb 0x0a 0x4b 0x200>; | |
| reg-names = "base", "debugchain-base"; | |
| qcom,num-qtb-ports = <0x01>; | |
| qcom,stream-id-range = <0x400 0x400>; | |
| qcom,iova-width = <0x24>; | |
| compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; | |
| reg = <0x171a000 0x1000 0x16e1100 0x1000>; | |
| phandle = <0x3fe>; | |
| }; | |
| pcie_qtb@16cd000 { | |
| interconnects = <0xed 0x2d 0x4b 0x200>; | |
| reg-names = "base", "debugchain-base"; | |
| qcom,num-qtb-ports = <0x01>; | |
| qcom,stream-id-range = <0x1400 0x400>; | |
| qcom,opt-out-tbu-halting; | |
| qcom,iova-width = <0x24>; | |
| compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; | |
| reg = <0x16cd000 0x1000 0x16c3000 0x1000>; | |
| phandle = <0x402>; | |
| }; | |
| lpass_qtb@503000 { | |
| interconnects = <0x72 0x29 0x4b 0x200>; | |
| reg-names = "base", "debugchain-base"; | |
| qcom,num-qtb-ports = <0x01>; | |
| qcom,stream-id-range = <0x1000 0x400>; | |
| qcom,iova-width = <0x20>; | |
| compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; | |
| reg = <0x503000 0x1000 0x511000 0x1000>; | |
| phandle = <0x401>; | |
| }; | |
| nsp_qtb@523000 { | |
| interconnects = <0x7a 0x2a 0x4b 0x200>; | |
| reg-names = "base", "debugchain-base"; | |
| qcom,num-qtb-ports = <0x02>; | |
| qcom,stream-id-range = <0xc00 0x400>; | |
| qcom,iova-width = <0x22>; | |
| compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; | |
| reg = <0x523000 0x1000 0x532000 0x1000>; | |
| phandle = <0x400>; | |
| }; | |
| sf_qtb@17d1000 { | |
| interconnects = <0xec 0x1d 0x4b 0x200>; | |
| reg-names = "base", "debugchain-base"; | |
| qcom,num-qtb-ports = <0x02>; | |
| qcom,stream-id-range = <0x1800 0x400>; | |
| qcom,iova-width = <0x24>; | |
| compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; | |
| reg = <0x17d1000 0x1000 0x1783000 0x1000>; | |
| phandle = <0x403>; | |
| }; | |
| }; | |
| funnel@10804000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-modem"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10804000 0x1000>; | |
| phandle = <0x44b>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x190>; | |
| phandle = <0x189>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x191>; | |
| phandle = <0x18e>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x18f>; | |
| phandle = <0x11e>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x192>; | |
| phandle = <0x1c0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| clocks { | |
| xo_board { | |
| clock-output-names = "xo_board"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x493e000>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x3de>; | |
| }; | |
| sleep_clk { | |
| clock-output-names = "sleep_clk"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x7d00>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x54>; | |
| }; | |
| }; | |
| clock-controller@aaf0000 { | |
| #reset-cells = <0x01>; | |
| clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; | |
| vdd_mxc-supply = <0x2b>; | |
| clocks = <0x46 0x00 0x46 0x01 0x54 0x45 0xa7>; | |
| vdd_mm-supply = <0x28>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,kalama-videocc-v2", "syscon"; | |
| reg-name = "cc_base"; | |
| reg = <0xaaf0000 0x10000>; | |
| phandle = <0x5f>; | |
| }; | |
| ddrqos-freq-table { | |
| qcom,freq-tbl = <0x00 0x01>; | |
| phandle = <0x95>; | |
| }; | |
| qcom,pmic_glink { | |
| depends-on-supply = <0x4f>; | |
| qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; | |
| qcom,subsys-name = "lpass"; | |
| compatible = "qcom,pmic-glink"; | |
| qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; | |
| qcom,battery_charger { | |
| qcom,wireless-fw-name = "idt9418.bin"; | |
| qcom,display-panels = <0x764 0x779>; | |
| compatible = "qcom,battery-charger"; | |
| qcom,thermal-mitigation-step = <0x7a120>; | |
| phandle = <0x3f5>; | |
| }; | |
| qcom,ucsi { | |
| compatible = "qcom,ucsi-glink"; | |
| phandle = <0x3f6>; | |
| connector { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x618>; | |
| phandle = <0x617>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,altmode { | |
| #altmode-cells = <0x01>; | |
| compatible = "qcom,altmode-glink"; | |
| phandle = <0x3f7>; | |
| }; | |
| }; | |
| tpdm@10d30000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-ddr-ch13"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10d30000 0x1000>; | |
| phandle = <0x155>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf8>; | |
| phandle = <0x147>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,bps@ac2c000 { | |
| clock-control-debugfs = "true"; | |
| clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; | |
| reg-names = "bps_top"; | |
| reg-cam-base = <0x2c000>; | |
| cell-index = <0x00>; | |
| bps-vdd-supply = <0x4fa>; | |
| clocks = <0x3b 0x00 0x3b 0x03 0x3b 0x02 0x3b 0x01 0x3b 0x10>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| cam_hw_pid = <0x00 0x02>; | |
| compatible = "qcom,cam-bps680"; | |
| src-clock-name = "bps_clk_src"; | |
| status = "ok"; | |
| reg = <0xac2c000 0xb000>; | |
| regulator-names = "bps-vdd"; | |
| phandle = <0x5c9>; | |
| nrt-device; | |
| clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; | |
| }; | |
| tx_core_clk { | |
| qcom,codec-ext-clk-src = <0x07>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x65f>; | |
| qcom,codec-lpass-clk-id = <0x30c>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| qcom,sps { | |
| qcom,pipe-attr-ee; | |
| compatible = "qcom,msm-sps-4k"; | |
| }; | |
| syscon@3d9953c { | |
| compatible = "syscon"; | |
| reg = <0x3d9953c 0x04>; | |
| phandle = <0x2dd>; | |
| }; | |
| qcom,spss_utils { | |
| qcom,spss-dev-firmware-name = "spss1d.mdt"; | |
| qcom,spss-debug-reg-addr = <0x1886020>; | |
| qcom,spss-fuse2-addr = <0x221c8214>; | |
| qcom,spss-fuse1-addr = <0x221c8214>; | |
| qcom,spss-fuse1-bit = <0x08>; | |
| qcom,pil-size = <0xf0000>; | |
| qcom,spss-prod-firmware-name = "spss1p.mdt"; | |
| qcom,spss-emul-type-reg-addr = <0x1fc8004>; | |
| qcom,spss-fuse2-bit = <0x07>; | |
| qcom,spss-test-firmware-name = "spss1t.mdt"; | |
| compatible = "qcom,spss-utils"; | |
| status = "ok"; | |
| pil-mem = <0x4d>; | |
| phandle = <0x35e>; | |
| qcom,rproc-handle = <0x50>; | |
| qcom,spss-debug-reg-addr3 = <0x188c020>; | |
| qcom,spss-debug-reg-addr1 = <0x1888020>; | |
| }; | |
| interconnect@0 { | |
| #interconnect-cells = <0x01>; | |
| qcom,bcm-voters = <0x40>; | |
| compatible = "qcom,kalama-clk_virt"; | |
| phandle = <0x1fa>; | |
| qcom,bcm-voter-names = "hlos"; | |
| }; | |
| funnel@10ac2000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-dl_north"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10ac2000 0x1000>; | |
| phandle = <0x447>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x183>; | |
| phandle = <0x182>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x185>; | |
| phandle = <0x17f>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x184>; | |
| phandle = <0x166>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x186>; | |
| phandle = <0x1be>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10831000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-iris_dl_cti"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x10831000 0x1000>; | |
| phandle = <0x468>; | |
| }; | |
| qcom,msm-eud@88e0000 { | |
| reg-names = "eud_base", "eud_mode_mgr2"; | |
| interrupts = <0x0b 0x04>; | |
| interrupt-parent = <0x51>; | |
| qcom,secure-eud-en; | |
| compatible = "qcom,msm-eud"; | |
| status = "ok"; | |
| interrupt-names = "eud_irq"; | |
| reg = <0x88e0000 0x2000 0x88e2000 0x1000>; | |
| phandle = <0x2b4>; | |
| }; | |
| ipcc-self-ping-cdsp { | |
| interrupts-extended = <0x4f 0x06 0x03 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x3f9>; | |
| mboxes = <0x4f 0x06 0x03>; | |
| }; | |
| qcom,gdsc@adf33e0 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x06>; | |
| regulator-name = "cam_cc_sfe_1_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xadf33e0 0x04>; | |
| phandle = <0x501>; | |
| }; | |
| qcom,mpm2-sleep-counter@c221000 { | |
| clock-frequency = <0x8000>; | |
| compatible = "qcom,mpm2-sleep-counter"; | |
| reg = <0xc221000 0x1000>; | |
| }; | |
| qcom,cam-isp { | |
| compatible = "qcom,cam-isp"; | |
| status = "ok"; | |
| arch-compat = "ife"; | |
| }; | |
| clock-controller@100000 { | |
| #reset-cells = <0x01>; | |
| vdd_mxa-supply = <0x2a>; | |
| clock-names = "bi_tcxo", "pcie_0_pipe_clk", "pcie_1_phy_aux_clk", "pcie_1_pipe_clk", "sleep_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; | |
| clocks = <0x46 0x00 0x55 0x56 0x57 0x54 0x58 0x59 0x5a 0x5b>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,kalama-gcc-v2", "syscon"; | |
| reg-name = "cc_base"; | |
| reg = <0x100000 0x1f4200>; | |
| phandle = <0x45>; | |
| vdd_cx-supply = <0x27>; | |
| }; | |
| apps_rsc@17a00000 { | |
| power-domains = <0x20>; | |
| reg-names = "drv-0", "drv-1", "drv-2"; | |
| interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>; | |
| label = "apps_rsc"; | |
| compatible = "qcom,rpmh-rsc"; | |
| reg = <0x17a00000 0x10000 0x17a10000 0x10000 0x17a20000 0x10000>; | |
| phandle = <0x2ff>; | |
| qcom,drv-count = <0x03>; | |
| drv@2 { | |
| qcom,drv-id = <0x02>; | |
| qcom,tcs-offset = <0xd00>; | |
| phandle = <0x300>; | |
| rpmh-regulator-ldom4 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldom4"; | |
| regulator-pm8010m-l4 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8010m_l4"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x334>; | |
| }; | |
| }; | |
| rpmh-regulator-lcxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "lcx.lvl"; | |
| regulator-pm-v6d-s4-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v6d_s4_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x70>; | |
| }; | |
| }; | |
| rpmh-regulator-bobb2 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "bobb2"; | |
| regulator-pm-humu-bob2 { | |
| regulator-max-microvolt = <0x2de600>; | |
| qcom,init-voltage = <0x298100>; | |
| regulator-min-microvolt = <0x294280>; | |
| regulator-name = "pm_humu_bob2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x313>; | |
| }; | |
| }; | |
| rpmh-regulator-ldol4 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldol4"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrl-l4 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pmr_nalojrl_l4"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x32d>; | |
| }; | |
| }; | |
| cam1_avdd2v8 { | |
| pinctrl-names = "default"; | |
| gpio = <0x33 0x16 0x00>; | |
| pinctrl-0 = <0x37>; | |
| regulator-enable-ramp-delay = <0x00>; | |
| enable-active-high; | |
| regulator-name = "cam1_avdd2v8"; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x343>; | |
| }; | |
| rpmh-regulator-ldok4 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldok4"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrk-l4 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pmr_nalojrk_l4"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x328>; | |
| }; | |
| }; | |
| rpmh-regulator-smpg1 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpg1"; | |
| regulator-pm-v6g-s1 { | |
| regulator-max-microvolt = <0x13d620>; | |
| qcom,init-voltage = <0x132a40>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm_v6g_s1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x31c>; | |
| }; | |
| }; | |
| rpmh-regulator-ldon2 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldon2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8010n-l2 { | |
| regulator-max-microvolt = <0x10d880>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x10d880>; | |
| regulator-min-microvolt = <0x10d880>; | |
| regulator-name = "pm8010n_l2"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x339>; | |
| }; | |
| }; | |
| rpmh-regulator-ldom2 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldom2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8010m-l2 { | |
| regulator-max-microvolt = <0x101d00>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x101d00>; | |
| regulator-min-microvolt = <0x101d00>; | |
| regulator-name = "pm8010m_l2"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x332>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob8 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob8"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l8 { | |
| regulator-max-microvolt = <0x2de600>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm_humu_l8"; | |
| qcom,set = <0x03>; | |
| phandle = <0x30b>; | |
| }; | |
| }; | |
| rtl8367_switch_power { | |
| regulator-max-microvolt = <0xf4240>; | |
| pinctrl-names = "default"; | |
| gpio = <0x33 0xc6 0x01>; | |
| pinctrl-0 = <0x39 0x3a>; | |
| regulator-enable-ramp-delay = <0x2710>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0xf4240>; | |
| gpio1 = <0x33 0x97 0x01>; | |
| regulator-name = "rtl8367_switch_power"; | |
| compatible = "regulator-fixed"; | |
| status = "okay"; | |
| phandle = <0x2cc>; | |
| gpio2 = <0x33 0x98 0x01>; | |
| }; | |
| rpmh-regulator-ldok2 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldok2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrk-l2 { | |
| regulator-max-microvolt = <0xdbba0>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = "", "\f5"; | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-name = "pmr_nalojrk_l2"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x326>; | |
| }; | |
| }; | |
| cam0_afvdd_2v8 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| pinctrl-names = "default"; | |
| regulator-boot-on; | |
| gpio = <0x33 0x30 0x00>; | |
| pinctrl-0 = <0x35>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "cam0_afvdd_2v8"; | |
| startup-delay-us = <0x00>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x341>; | |
| }; | |
| rpmh-regulator-ldob16 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob16"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l16 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm_humu_l16"; | |
| qcom,set = <0x03>; | |
| phandle = <0x310>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob6 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob6"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l6 { | |
| regulator-max-microvolt = <0x2de600>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm_humu_l6"; | |
| qcom,set = <0x03>; | |
| phandle = <0x309>; | |
| }; | |
| }; | |
| rpmh-regulator-ebilvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "ebi.lvl"; | |
| regulator-pm-v8-s3-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v8_s3_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x304>; | |
| }; | |
| }; | |
| rpmh-regulator-cxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "cx.lvl"; | |
| proxy-supply = <0x27>; | |
| regulator-pm-v6e-s6-mmcx-sup-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x30>; | |
| regulator-name = "pm_v6e_s6_mmcx_sup_level"; | |
| qcom,init-voltage-level = <0x30>; | |
| qcom,set = <0x03>; | |
| phandle = <0x29>; | |
| }; | |
| regulator-pm-v6e-s6-level-ao { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v6e_s6_level_ao"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x01>; | |
| phandle = <0x301>; | |
| }; | |
| regulator-pm-v6e-s6-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v6e_s6_level"; | |
| qcom,init-voltage-level = <0x180>; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x27>; | |
| qcom,proxy-consumer-voltage = <0x180 0xffff>; | |
| }; | |
| }; | |
| cam_avdd2v8 { | |
| pinctrl-names = "default"; | |
| gpio = <0x33 0x9c 0x00>; | |
| pinctrl-0 = <0x34>; | |
| regulator-enable-ramp-delay = <0x00>; | |
| enable-active-high; | |
| regulator-name = "cam0_avdd2v8"; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x340>; | |
| }; | |
| rpmh-regulator-ldog2 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldog2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v6g-l2 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x10c8e0>; | |
| regulator-name = "pm_v6g_l2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x323>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob14 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob14"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l14 { | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x2dc6c0>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-name = "pm_humu_l14"; | |
| qcom,set = <0x03>; | |
| phandle = <0x30e>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof2 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v8-l2 { | |
| regulator-max-microvolt = <0xdea80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm_v8_l2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x31b>; | |
| }; | |
| }; | |
| clock-controller { | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,kalama-rpmh-clk"; | |
| phandle = <0x46>; | |
| }; | |
| rpmh-regulator-ldoe2 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoe2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v6e-l2 { | |
| regulator-max-microvolt = <0xecd10>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xdcb40>; | |
| regulator-min-microvolt = <0xd4670>; | |
| regulator-name = "pm_v6e_l2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x318>; | |
| }; | |
| }; | |
| rpmh-regulator-smpg6 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpg6"; | |
| regulator-pm-v6g-s6 { | |
| regulator-max-microvolt = <0x1e8480>; | |
| qcom,init-voltage = <0x1c5200>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm_v6g_s6"; | |
| qcom,set = <0x03>; | |
| phandle = <0x321>; | |
| }; | |
| }; | |
| rpmh-regulator-ldon7 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldon7"; | |
| regulator-pm8010n-l7 { | |
| regulator-max-microvolt = <0x2d2a80>; | |
| qcom,init-voltage = <0x2d2a80>; | |
| regulator-min-microvolt = <0x2d2a80>; | |
| regulator-name = "pm8010n_l7"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x33e>; | |
| }; | |
| }; | |
| cam1_vdig1v2 { | |
| pinctrl-names = "default"; | |
| gpio = <0x33 0x5a 0x00>; | |
| pinctrl-0 = <0x36>; | |
| regulator-enable-ramp-delay = <0x00>; | |
| enable-active-high; | |
| regulator-name = "cam1_vdig1v2"; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x342>; | |
| }; | |
| rpmh-regulator-ldom7 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldom7"; | |
| regulator-pm8010m-l7 { | |
| regulator-max-microvolt = <0x2c4fc0>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8010m_l7"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x337>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob12 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob12"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x2e>; | |
| regulator-pm-humu-l12 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm_humu_l12"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x2e>; | |
| }; | |
| }; | |
| rpmh-regulator-ldol7 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldol7"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrl-l7 { | |
| regulator-max-microvolt = <0xdbba0>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xb7980>; | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-name = "pmr_nalojrl_l7"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x330>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob2 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l2 { | |
| regulator-max-microvolt = <0x2de600>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x2de600>; | |
| regulator-min-microvolt = <0x2de600>; | |
| regulator-name = "pm_humu_l2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x307>; | |
| }; | |
| }; | |
| channel@0 { | |
| qcom,tcs-config = <0x02 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x04 0x01>; | |
| }; | |
| rpmh-regulator-ldok7 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldok7"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrk-l7 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pmr_nalojrk_l7"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x32b>; | |
| }; | |
| }; | |
| rpmh-regulator-smpg4 { | |
| qcom,mode-threshold-currents = <0x00 0x30d40>; | |
| qcom,regulator-type = "pmic5-ftsmps"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpg4"; | |
| qcom,supported-modes = <0x01 0x04>; | |
| regulator-pm-v6g-s4 { | |
| regulator-max-microvolt = <0x14a140>; | |
| qcom,init-mode = <0x01>; | |
| qcom,init-voltage = <0x13e5c0>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm_v6g_s4"; | |
| qcom,set = <0x03>; | |
| phandle = <0x31f>; | |
| }; | |
| }; | |
| rpmh-regulator-ldon5 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldon5"; | |
| regulator-pm8010n-l5 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8010n_l5"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x33c>; | |
| }; | |
| }; | |
| bcm_voter { | |
| compatible = "qcom,bcm-voter"; | |
| phandle = <0x40>; | |
| }; | |
| rpmh-regulator-smpf4 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpf4"; | |
| regulator-pm-v8-s4 { | |
| regulator-max-microvolt = <0xaae60>; | |
| qcom,init-voltage = <0x7a120>; | |
| regulator-min-microvolt = <0x493e0>; | |
| regulator-name = "pm_v8_s4"; | |
| qcom,set = <0x03>; | |
| phandle = <0x319>; | |
| }; | |
| }; | |
| rpmh-regulator-ldom5 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldom5"; | |
| regulator-pm8010m-l5 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8010m_l5"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x335>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob10 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob10"; | |
| regulator-pm-humu-l10 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm_humu_l10"; | |
| qcom,set = <0x03>; | |
| phandle = <0x30d>; | |
| }; | |
| }; | |
| rpmh-regulator-smpe4 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpe4"; | |
| regulator-pm-v6e-s4 { | |
| regulator-max-microvolt = <0xf03c0>; | |
| qcom,init-voltage = <0xe86c0>; | |
| regulator-min-microvolt = <0xdcb40>; | |
| regulator-name = "pm_v6e_s4"; | |
| qcom,set = <0x03>; | |
| phandle = <0x316>; | |
| }; | |
| }; | |
| rpmh-regulator-ldol5 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldol5"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrl-l5 { | |
| regulator-max-microvolt = "", "\f5"; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = "", "\f5"; | |
| regulator-min-microvolt = "", "\f5"; | |
| regulator-name = "pmr_nalojrl_l5"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x32e>; | |
| }; | |
| }; | |
| qcom,dcvs-fp { | |
| qcom,llcc-bcm-name = "SH5"; | |
| compatible = "qcom,dcvs-fp"; | |
| phandle = <0x93>; | |
| qcom,ddr-bcm-name = "MC4"; | |
| }; | |
| rpmh-regulator-ldok5 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldok5"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrk-l5 { | |
| regulator-max-microvolt = "", "\f5"; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = "", "\f5"; | |
| regulator-min-microvolt = "", "\f5"; | |
| regulator-name = "pmr_nalojrk_l5"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x329>; | |
| }; | |
| }; | |
| rpmh-regulator-smpg2 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpg2"; | |
| regulator-pm-v6g-s2 { | |
| regulator-max-microvolt = <0xfcee0>; | |
| qcom,init-voltage = <0xd0020>; | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-name = "pm_v6g_s2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x31d>; | |
| }; | |
| }; | |
| rpmh-regulator-ldon3 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldon3"; | |
| regulator-pm8010n-l3 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8010n_l3"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x33a>; | |
| }; | |
| }; | |
| cam_vdig1v2 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x32>; | |
| regulator-enable-ramp-delay = <0x00>; | |
| regulator-name = "cam0_vdig1v2"; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x33f>; | |
| }; | |
| rpmh-regulator-ldom3 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldom3"; | |
| regulator-pm8010m-l3 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8010m_l3"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x333>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob9 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob9"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l9 { | |
| regulator-max-microvolt = <0x2de600>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x2d2a80>; | |
| regulator-min-microvolt = <0x2d2a80>; | |
| regulator-name = "pm_humu_l9"; | |
| qcom,set = <0x03>; | |
| phandle = <0x30c>; | |
| }; | |
| }; | |
| rpmh-regulator-gfxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "gfx.lvl"; | |
| regulator-pm-v6d-s5-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v6d_s5_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x2c>; | |
| }; | |
| }; | |
| rpmh-regulator-bobb1 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "bobb1"; | |
| regulator-pm-humu-bob1 { | |
| regulator-max-microvolt = <0x3c6cc0>; | |
| qcom,init-voltage = "", "2K"; | |
| regulator-min-microvolt = <0x2de600>; | |
| regulator-name = "pm_humu_bob1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x312>; | |
| }; | |
| }; | |
| rpmh-regulator-nsplvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "nsp.lvl"; | |
| regulator-pm-v8-s1-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v8_s1_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x77>; | |
| }; | |
| }; | |
| cam1_afvdd_2v8 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| pinctrl-names = "default"; | |
| regulator-boot-on; | |
| gpio = <0x33 0x17 0x00>; | |
| pinctrl-0 = <0x38>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "cam1_afvdd_2v8"; | |
| startup-delay-us = <0x00>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x344>; | |
| }; | |
| rpmh-regulator-ldol3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldol3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrl-l3 { | |
| regulator-max-microvolt = <0xdea80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xdea80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pmr_nalojrl_l3"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x32c>; | |
| }; | |
| }; | |
| rpmh-regulator-lmxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "lmx.lvl"; | |
| regulator-pm-v6d-l2-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v6d_l2_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x71>; | |
| }; | |
| }; | |
| rpmh-regulator-ldok3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldok3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrk-l3 { | |
| regulator-max-microvolt = <0xdea80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pmr_nalojrk_l3"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x327>; | |
| }; | |
| }; | |
| rpmh-regulator-ldon1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldon1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8010n-l1 { | |
| regulator-max-microvolt = <0x10d880>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x10d880>; | |
| regulator-min-microvolt = <0x10d880>; | |
| regulator-name = "pm8010n_l1"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x338>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob17 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob17"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l17 { | |
| regulator-max-microvolt = <0x263540>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x263540>; | |
| regulator-min-microvolt = <0x263540>; | |
| regulator-name = "pm_humu_l17"; | |
| qcom,set = <0x03>; | |
| phandle = <0x311>; | |
| }; | |
| }; | |
| rpmh-regulator-ldom1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldom1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8010m-l1 { | |
| regulator-max-microvolt = <0x101d00>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x101d00>; | |
| regulator-min-microvolt = <0x101d00>; | |
| regulator-name = "pm8010m_l1"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x331>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob7 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob7"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l7 { | |
| regulator-max-microvolt = <0x2de600>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm_humu_l7"; | |
| qcom,set = <0x03>; | |
| phandle = <0x30a>; | |
| }; | |
| }; | |
| rpmh-regulator-ldok1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldok1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrk-l1 { | |
| regulator-max-microvolt = <0xdbba0>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = "", "\f5"; | |
| regulator-min-microvolt = <0x61a80>; | |
| regulator-name = "pmr_nalojrk_l1"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x325>; | |
| }; | |
| }; | |
| rpmh-regulator-msslvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "mss.lvl"; | |
| regulator-pm-v8-s7-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v8_s7_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x7d>; | |
| }; | |
| }; | |
| rpmh-regulator-mxclvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "mxc.lvl"; | |
| proxy-supply = <0x2b>; | |
| regulator-pm-v8-s5-gfx-voter-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x30>; | |
| regulator-name = "pm_v8_s5_gfx_voter_level"; | |
| qcom,init-voltage-level = <0x30>; | |
| qcom,set = <0x03>; | |
| phandle = <0x2e2>; | |
| pm_v8_s5_gfx_voter_level-parent-supply = <0x2c>; | |
| }; | |
| regulator-pm-v8-s5-mmcx-voter-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x30>; | |
| regulator-name = "pm_v8_s5_mmcx_voter_level"; | |
| pm_v8_s5_mmcx_voter_level-parent-supply = <0x28>; | |
| qcom,init-voltage-level = <0x30>; | |
| qcom,set = <0x03>; | |
| phandle = <0x2d8>; | |
| }; | |
| regulator-pm-v8-s5-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v8_s5_level"; | |
| qcom,init-voltage-level = <0x180>; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x2b>; | |
| qcom,proxy-consumer-voltage = <0x180 0xffff>; | |
| }; | |
| regulator-pm-v8-s5-level-ao { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v8_s5_level_ao"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x01>; | |
| phandle = <0x305>; | |
| }; | |
| }; | |
| rpmh-regulator-ldog3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldog3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v6g-l3 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm_v6g_l3"; | |
| qcom,set = <0x03>; | |
| phandle = <0x324>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob15 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob15"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l15 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm_humu_l15"; | |
| qcom,set = <0x03>; | |
| phandle = <0x30f>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v8-l3 { | |
| regulator-max-microvolt = <0xdea80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xdea80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm_v8_l3"; | |
| qcom,set = <0x03>; | |
| phandle = <0x2b7>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob5 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob5"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l5 { | |
| regulator-max-microvolt = "", "/]"; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = "", "/]"; | |
| regulator-min-microvolt = "", "/]"; | |
| regulator-name = "pm_humu_l5"; | |
| qcom,set = <0x03>; | |
| phandle = <0x308>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoe3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoe3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x31>; | |
| regulator-pm-v6e-l3-so { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| qcom,init-enable = <0x00>; | |
| regulator-name = "pm_v6e_l3_so"; | |
| qcom,set = <0x02>; | |
| }; | |
| regulator-pm-v6e-l3-ao { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm_v6e_l3_ao"; | |
| qcom,set = <0x01>; | |
| phandle = <0x2d7>; | |
| }; | |
| regulator-pm-v6e-l3 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm_v6e_l3"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x31>; | |
| }; | |
| }; | |
| rpmh-regulator-mmcxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "mmcx.lvl"; | |
| proxy-supply = <0x28>; | |
| regulator-pm-v6e-s1-level { | |
| regulator-max-microvolt = <0xffff>; | |
| pm_v6e_s1_level-parent-supply = <0x29>; | |
| regulator-min-microvolt = <0x40>; | |
| regulator-name = "pm_v6e_s1_level"; | |
| qcom,init-voltage-level = <0x180>; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x28>; | |
| qcom,proxy-consumer-voltage = <0x180 0xffff>; | |
| }; | |
| regulator-pm-v6e-s1-level-so { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x40>; | |
| regulator-name = "pm_v6e_s1_level_so"; | |
| qcom,init-voltage-level = <0x40>; | |
| qcom,set = <0x02>; | |
| }; | |
| regulator-pm-v6e-s1-level-ao { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x40>; | |
| regulator-name = "pm_v6e_s1_level_ao"; | |
| qcom,init-voltage-level = <0x40>; | |
| qcom,set = <0x01>; | |
| phandle = <0x302>; | |
| }; | |
| }; | |
| rpmh-regulator-mxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "mx.lvl"; | |
| proxy-supply = <0x2a>; | |
| regulator-pm-v6e-s3-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v6e_s3_level"; | |
| qcom,init-voltage-level = <0x180>; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x2a>; | |
| qcom,proxy-consumer-voltage = <0x180 0xffff>; | |
| }; | |
| regulator-pm-v6e-s3-level-ao { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm_v6e_s3_level_ao"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x01>; | |
| phandle = <0x303>; | |
| }; | |
| }; | |
| rpmh-regulator-ldog1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldog1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v6g-l1 { | |
| regulator-max-microvolt = <0x132a40>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x1174c0>; | |
| regulator-name = "pm_v6g_l1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x322>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob13 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob13"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x2f>; | |
| regulator-pm-humu-l13 { | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x2dc6c0>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-name = "pm_humu_l13"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x2f>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v6c-l3 { | |
| regulator-max-microvolt = <0xdea80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xdea80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm_v6c_l3"; | |
| qcom,set = <0x03>; | |
| phandle = <0x2c9>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v8-l1 { | |
| regulator-max-microvolt = <0xdea80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xdea80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm_v8_l1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x31a>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoe1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoe1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x30>; | |
| regulator-pm-v6e-l1-so { | |
| regulator-max-microvolt = <0xd6d80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| qcom,init-enable = <0x00>; | |
| regulator-name = "pm_v6e_l1_so"; | |
| qcom,set = <0x02>; | |
| }; | |
| regulator-pm-v6e-l1-ao { | |
| regulator-max-microvolt = <0xd6d80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm_v6e_l1_ao"; | |
| qcom,set = <0x01>; | |
| phandle = <0x2d6>; | |
| }; | |
| regulator-pm-v6e-l1 { | |
| regulator-max-microvolt = <0xdea80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm_v6e_l1"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x30>; | |
| }; | |
| }; | |
| rpmh-regulator-smpg5 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpg5"; | |
| regulator-pm-v6g-s5 { | |
| regulator-max-microvolt = <0xf51e0>; | |
| qcom,init-voltage = <0xd0020>; | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-name = "pm_v6g_s5"; | |
| qcom,set = <0x03>; | |
| phandle = <0x320>; | |
| }; | |
| }; | |
| rpmh-regulator-ldon6 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldon6"; | |
| regulator-pm8010n-l6 { | |
| regulator-max-microvolt = <0x326a40>; | |
| qcom,init-voltage = <0x326a40>; | |
| regulator-min-microvolt = <0x326a40>; | |
| regulator-name = "pm8010n_l6"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x33d>; | |
| }; | |
| }; | |
| rpmh-regulator-ldod1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldod1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v6d-l1 { | |
| regulator-max-microvolt = <0xe09c0>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm_v6d_l1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x315>; | |
| }; | |
| }; | |
| rpmh-regulator-ldom6 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldom6"; | |
| regulator-pm8010m-l6 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8010m_l6"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x336>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob11 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob11"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x2d>; | |
| regulator-pm-humu-l11 { | |
| regulator-max-microvolt = <0x16f300>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm_humu_l11"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x2d>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-v6c-l1 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm_v6c_l1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x314>; | |
| }; | |
| }; | |
| rpmh-regulator-smpe5 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpe5"; | |
| regulator-pm-v6e-s5 { | |
| regulator-max-microvolt = <0x111700>; | |
| qcom,init-voltage = <0x107ac0>; | |
| regulator-min-microvolt = <0xf6950>; | |
| regulator-name = "pm_v6e_s5"; | |
| qcom,set = <0x03>; | |
| phandle = <0x317>; | |
| }; | |
| }; | |
| rpmh-regulator-ldol6 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldol6"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrl-l6 { | |
| regulator-max-microvolt = <0x1b1980>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x1b1980>; | |
| regulator-min-microvolt = <0x1b1980>; | |
| regulator-name = "pmr_nalojrl_l6"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x32f>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldob1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm-humu-l1 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-always-on; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm_humu_l1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x306>; | |
| }; | |
| }; | |
| rpmh-regulator-ldok6 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldok6"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pmr-nalojrk-l6 { | |
| regulator-max-microvolt = <0x1cfde0>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x1b1980>; | |
| regulator-min-microvolt = <0x1b1980>; | |
| regulator-name = "pmr_nalojrk_l6"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x32a>; | |
| }; | |
| }; | |
| rpmh-regulator-smpg3 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpg3"; | |
| regulator-pm-v6g-s3 { | |
| regulator-max-microvolt = <0xf51e0>; | |
| qcom,init-voltage = <0xb7980>; | |
| regulator-min-microvolt = <0x493e0>; | |
| regulator-name = "pm_v6g_s3"; | |
| qcom,set = <0x03>; | |
| phandle = <0x31e>; | |
| }; | |
| }; | |
| rpmh-regulator-ldon4 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| status = "disabled"; | |
| qcom,resource-name = "ldon4"; | |
| regulator-pm8010n-l4 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8010n_l4"; | |
| status = "disabled"; | |
| qcom,set = <0x03>; | |
| phandle = <0x33b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10b0d000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-swao-1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b0d000 0x1000>; | |
| phandle = <0x413>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10a>; | |
| phandle = <0x1ca>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cam-icp { | |
| icp_pc_en; | |
| ipe_bps_pc_en; | |
| num-bps = <0x01>; | |
| num-ipe = <0x01>; | |
| compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; | |
| icp_use_pil; | |
| compatible = "qcom,cam-icp"; | |
| status = "ok"; | |
| num-icp = <0x01>; | |
| }; | |
| psci { | |
| method = "smc"; | |
| compatible = "arm,psci-1.0"; | |
| cpu-pd3 { | |
| power-domains = <0x20>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x0d>; | |
| }; | |
| cpu-pd1 { | |
| power-domains = <0x20>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x09>; | |
| }; | |
| cpu-pd6 { | |
| power-domains = <0x20>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x13>; | |
| }; | |
| cluster-pd { | |
| domain-idle-states = <0x21 0x22>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x20>; | |
| }; | |
| cpu-pd4 { | |
| power-domains = <0x20>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x0f>; | |
| }; | |
| cpu-pd2 { | |
| power-domains = <0x20>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x0b>; | |
| }; | |
| cpu-pd0 { | |
| power-domains = <0x20>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x05>; | |
| }; | |
| cpu-pd7 { | |
| power-domains = <0x20>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x16>; | |
| }; | |
| cpu-pd5 { | |
| power-domains = <0x20>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x11>; | |
| }; | |
| }; | |
| tpdm@10b0a000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-swao-prio-1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b0a000 0x1000>; | |
| phandle = <0x408>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf3>; | |
| phandle = <0x1c7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gpio_key { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x612 0x361>; | |
| label = "gpio-keys"; | |
| compatible = "gpio-keys"; | |
| vol_up { | |
| linux,can-disable; | |
| label = "volume_up"; | |
| linux,input-type = <0x01>; | |
| gpio-key,wakeup; | |
| linux,code = <0x73>; | |
| debounce-interval = <0x0f>; | |
| gpios = <0x5fd 0x06 0x01>; | |
| }; | |
| cus_key { | |
| linux,can-disable; | |
| label = "custom_key"; | |
| linux,input-type = <0x01>; | |
| linux,code = <0xc2>; | |
| debounce-interval = <0x0f>; | |
| gpios = <0x33 0x29 0x01>; | |
| }; | |
| }; | |
| qcom,vidc@aa00000 { | |
| qcom,allowed-clock-rates = <0xe4e1c00 0x14257880 0x15d0b780 0x1a76e700 0x1fca0555>; | |
| iris-ctl-supply = <0x2e3>; | |
| #address-cells = <0x01>; | |
| pas-id = <0x09>; | |
| interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc"; | |
| clock-names = "gcc_video_axi0", "core_clk", "vcodec_clk", "video_cc_mvs0_clk_src"; | |
| vidc,firmware-name = "vpu30_4v"; | |
| interconnects = <0x61 0x02 0x62 0x227 0x4b 0x03 0x4b 0x200 0xec 0x1d 0x61 0x22e>; | |
| clock-ids = <0xa8 0x05 0x02 0x03>; | |
| resets = <0x45 0x21>; | |
| vcodec-supply = <0x506>; | |
| memory-region = <0x2f1>; | |
| interrupts = <0x00 0xae 0x04>; | |
| clocks = <0x45 0xa8 0x5f 0x05 0x5f 0x02 0x5f 0x03>; | |
| #size-cells = <0x01>; | |
| qcom,reg-presets = <0xb0088 0x00 0x11>; | |
| compatible = "qcom,msm-vidc", "qcom,msm-vidc-kalama", "qcom,msm-vidc-iris3"; | |
| status = "okay"; | |
| reg = <0xaa00000 0xf0000>; | |
| phandle = <0x5d0>; | |
| qcom,proxy-clock-names = "gcc_video_axi0", "core_clk", "vcodec_clk", "video_cc_mvs0_clk_src"; | |
| reset-names = "video_axi_reset"; | |
| qcom,clock-configs = <0x00 0x00 0x00 0x01>; | |
| qcom,bus-range-kbps = <0x3e8 0x3e8 0x3e8 0xe4e1c0 0x3e8 0xe4e1c0>; | |
| cache-slice-names = "vidsc0", "vidvsp"; | |
| non_secure_pixel_cb { | |
| iommus = <0x4c 0x1947 0x00>; | |
| dma-coherent; | |
| virtual-addr-pool = <0x100000 0xdff00000>; | |
| label = "venus_ns_pixel"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| }; | |
| non_secure_cb { | |
| iommus = <0x4c 0x1940 0x00>; | |
| dma-coherent; | |
| virtual-addr-pool = <0x25800000 0xba800000>; | |
| label = "venus_ns"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| }; | |
| secure_non_pixel_cb { | |
| iommus = <0x4c 0x1944 0x00>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x1000000 0x24800000>; | |
| label = "venus_sec_non_pixel"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0b>; | |
| }; | |
| secure_bitstream_cb { | |
| iommus = <0x4c 0x1941 0x04>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x500000 0xdfb00000>; | |
| label = "venus_sec_bitstream"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x09>; | |
| }; | |
| secure_pixel_cb { | |
| iommus = <0x4c 0x1943 0x00>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x500000 0xdfb00000>; | |
| label = "venus_sec_pixel"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| }; | |
| qcom,gdsc@150018 { | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2a>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x00>; | |
| regulator-name = "gcc_usb3_phy_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| qcom,proxy-consumer-enable; | |
| reg = <0x150018 0x04>; | |
| phandle = <0x2b8>; | |
| proxy-supply = <0x2b8>; | |
| }; | |
| qcom,gdsc@3d99108 { | |
| hw-ctrl-addr = <0x2dd>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x27>; | |
| qcom,retain-regs; | |
| qcom,clk-dis-wait-val = <0x08>; | |
| regulator-name = "gpu_cc_cx_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0x3d99108 0x04>; | |
| phandle = <0xea>; | |
| }; | |
| qcom,test-msgq { | |
| qcom,primary; | |
| gunyah-label = <0x04>; | |
| compatible = "qcom,gh-msgq-test"; | |
| }; | |
| regulator-ocp-notifier { | |
| periph-5c2-supply = <0x31b>; | |
| periph-5c3-supply = <0x2b7>; | |
| periph-1ca-supply = <0x30d>; | |
| periph-1c1-supply = <0x306>; | |
| nvmem-cells = <0x600>; | |
| periph-1cb-supply = <0x2d>; | |
| periph-1c2-supply = <0x307>; | |
| periph-1cc-supply = <0x2e>; | |
| periph-6c1-supply = <0x322>; | |
| periph-1cd-supply = <0x2f>; | |
| periph-ac1-supply = <0x325>; | |
| periph-6c2-supply = <0x323>; | |
| periph-1ce-supply = <0x30e>; | |
| periph-ac2-supply = <0x326>; | |
| periph-6c3-supply = <0x324>; | |
| periph-1c5-supply = <0x308>; | |
| periph-2c1-supply = <0x314>; | |
| periph-1cf-supply = <0x30f>; | |
| periph-ac3-supply = <0x327>; | |
| interrupts = <0x00 0x71 0x01 0x01>; | |
| periph-1c6-supply = <0x309>; | |
| periph-ac4-supply = <0x328>; | |
| periph-1c7-supply = <0x30a>; | |
| periph-2c3-supply = <0x2c9>; | |
| periph-ac5-supply = <0x329>; | |
| periph-c40-supply = <0x331>; | |
| interrupt-parent = <0xe6>; | |
| periph-1c8-supply = <0x30b>; | |
| periph-ac6-supply = <0x32a>; | |
| periph-c41-supply = <0x332>; | |
| periph-1c9-supply = <0x30c>; | |
| periph-3c1-supply = <0x315>; | |
| periph-ac7-supply = <0x32b>; | |
| periph-c42-supply = <0x333>; | |
| periph-3c2-supply = <0x71>; | |
| periph-c43-supply = <0x334>; | |
| periph-1d0-supply = <0x310>; | |
| compatible = "qcom,regulator-ocp-notifier"; | |
| periph-c44-supply = <0x335>; | |
| periph-1d1-supply = <0x311>; | |
| periph-d40-supply = <0x338>; | |
| periph-c45-supply = <0x336>; | |
| periph-d41-supply = <0x339>; | |
| nvmem-cell-names = "ocp_log"; | |
| periph-4c1-supply = <0x30>; | |
| periph-c46-supply = <0x337>; | |
| phandle = <0x65d>; | |
| periph-d42-supply = <0x33a>; | |
| periph-4c2-supply = <0x318>; | |
| periph-d43-supply = <0x33b>; | |
| periph-4c3-supply = <0x31>; | |
| periph-d44-supply = <0x33c>; | |
| periph-d45-supply = <0x33d>; | |
| periph-5c1-supply = <0x31a>; | |
| periph-d46-supply = <0x33e>; | |
| }; | |
| qcom,qupv3_i2c_geni_se@9c0000 { | |
| #address-cells = <0x01>; | |
| clock-names = "m-ahb", "s-ahb"; | |
| clocks = <0x45 0x5a 0x45 0x5a>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,geni-se-qup"; | |
| ranges; | |
| status = "ok"; | |
| reg = <0x9c0000 0x2000>; | |
| phandle = <0x4b8>; | |
| i2c@998000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x2a7 0x2a8>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d6 0x04>; | |
| clocks = <0x45 0x52 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2a9>; | |
| status = "disabled"; | |
| reg = <0x998000 0x4000>; | |
| phandle = <0x4c0>; | |
| qcom,i2c-hub; | |
| }; | |
| i2c@984000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x298 0x299>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d1 0x04>; | |
| clocks = <0x45 0x48 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x29a>; | |
| status = "disabled"; | |
| reg = <0x984000 0x4000>; | |
| phandle = <0x4ba>; | |
| qcom,i2c-hub; | |
| }; | |
| i2c@9a0000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x2ad 0x2ae>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d8 0x04>; | |
| clocks = <0x45 0x56 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2af>; | |
| status = "disabled"; | |
| reg = <0x9a0000 0x4000>; | |
| phandle = <0x4c2>; | |
| qcom,i2c-hub; | |
| }; | |
| i2c@98c000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x29e 0x29f>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d3 0x04>; | |
| clocks = <0x45 0x4c 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2a0>; | |
| status = "okay"; | |
| reg = <0x98c000 0x4000>; | |
| phandle = <0x4bd>; | |
| qcom,i2c-hub; | |
| focaltech@38 { | |
| focaltech,reset-gpio = <0x33 0x0e 0x00>; | |
| pinctrl-names = "pmx_ts_active1", "pmx_ts_suspend1", "pmx_ts_release1"; | |
| pinctrl-2 = <0x776>; | |
| focaltech,ic-type = <0x54220402>; | |
| pinctrl-0 = <0x773>; | |
| focaltech,max-touch-number = <0x05>; | |
| interrupts = <0x0f 0x2008>; | |
| qcom,i2c-touch-active = "focaltech,fts_3"; | |
| interrupt-parent = <0x33>; | |
| vdd-supply = <0x769>; | |
| compatible = "focaltech,fts_3"; | |
| focaltech,touch-environment = "pvm"; | |
| focaltech,display-coords = <0x00 0x00 0x438 0x4d8>; | |
| pinctrl-1 = <0x774 0x775>; | |
| status = "ok"; | |
| focaltech,irq-gpio = <0x33 0x0f 0x2008>; | |
| reg = <0x38>; | |
| vcc_i2c-supply = <0x76b>; | |
| panel = <0x75e>; | |
| }; | |
| }; | |
| i2c@994000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x2a4 0x2a5>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d5 0x04>; | |
| clocks = <0x45 0x50 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2a6>; | |
| status = "disabled"; | |
| reg = <0x994000 0x4000>; | |
| phandle = <0x4bf>; | |
| qcom,i2c-hub; | |
| }; | |
| i2c@980000 { | |
| pinctrl-names = "default"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x296 0x297>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d0 0x04>; | |
| clocks = <0x45 0x46 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| status = "disabled"; | |
| reg = <0x980000 0x4000>; | |
| phandle = <0x4b9>; | |
| qcom,clk-freq-out = <0x186a0>; | |
| qcom,i2c-hub; | |
| }; | |
| i2c@99c000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x2aa 0x2ab>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d7 0x04>; | |
| clocks = <0x45 0x54 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2ac>; | |
| status = "disabled"; | |
| reg = <0x99c000 0x4000>; | |
| phandle = <0x4c1>; | |
| qcom,i2c-hub; | |
| }; | |
| i2c@990000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x2a1 0x2a2>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d4 0x04>; | |
| clocks = <0x45 0x4e 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2a3>; | |
| status = "disabled"; | |
| reg = <0x990000 0x4000>; | |
| phandle = <0x4be>; | |
| qcom,i2c-hub; | |
| }; | |
| i2c@988000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x29b 0x29c>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d2 0x04>; | |
| clocks = <0x45 0x4a 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x29d>; | |
| status = "ok"; | |
| reg = <0x988000 0x4000>; | |
| phandle = <0x4bb>; | |
| qcom,i2c-hub; | |
| aw883xx_smartpa@34 { | |
| irq-gpio = <0x33 0x61 0x00>; | |
| sync-load = <0x01>; | |
| re-min = <0x3e8>; | |
| re-max = <0x9c40>; | |
| reset-gpio = <0x33 0x67 0x00>; | |
| compatible = "awinic,aw883xx_smartpa"; | |
| sound-channel = <0x00>; | |
| status = "okay"; | |
| reg = <0x34>; | |
| }; | |
| nq@64 { | |
| rtc6226,vdd-supply-voltage = <0x2ab980 0x2ab980>; | |
| rtc6226,vdd-load = <0x3a98>; | |
| rtc6226,vio-supply-voltage = <0x1b7740 0x1b7740>; | |
| vdd-supply = <0x310>; | |
| compatible = "rtc6226"; | |
| reg = <0x64>; | |
| vio-supply = <0x30f>; | |
| }; | |
| redriver@1c { | |
| pinctrl-names = "default"; | |
| output-comp = <0x3030303 0x3030303>; | |
| pinctrl-0 = <0x3c8>; | |
| flat-gain = <0x3010103 0x2010102>; | |
| lane-channel-swap; | |
| loss-match = <0x1030301 0x3030303>; | |
| compatible = "onnn,redriver"; | |
| status = "disabled"; | |
| eq = <0x4040404 0x6040406>; | |
| reg = <0x1c>; | |
| phandle = <0x615>; | |
| gpios = <0x33 0x0b 0x00>; | |
| }; | |
| aw883xx_smartpa@35 { | |
| irq-gpio = <0x33 0x62 0x00>; | |
| sync-load = <0x01>; | |
| re-min = <0x3e8>; | |
| re-max = <0x9c40>; | |
| reset-gpio = <0x33 0x64 0x00>; | |
| compatible = "awinic,aw883xx_smartpa"; | |
| sound-channel = <0x01>; | |
| status = "okay"; | |
| reg = <0x35>; | |
| }; | |
| fsa4480@42 { | |
| compatible = "qcom,fsa4480-i2c"; | |
| reg = <0x42>; | |
| phandle = <0x4bc>; | |
| }; | |
| }; | |
| i2c@9a4000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config"; | |
| pinctrl-0 = <0x2b0 0x2b1>; | |
| clock-names = "se-clk", "core-clk"; | |
| interconnects = <0x1fa 0x24 0x1fa 0x23d 0x61 0x02 0x62 0x210>; | |
| interrupts = <0x00 0x1d9 0x04>; | |
| clocks = <0x45 0x58 0x45 0x45>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2b2>; | |
| status = "disabled"; | |
| reg = <0x9a4000 0x4000>; | |
| phandle = <0x4c3>; | |
| qcom,i2c-hub; | |
| }; | |
| }; | |
| qcom,rt-cdm0@ac25000 { | |
| clock-names = "cam_cc_cpas_ahb_clk"; | |
| reg-names = "rt-cdm0"; | |
| fifo-depths = <0x40 0x00 0x00 0x00>; | |
| reg-cam-base = <0x25000>; | |
| cdm-client-names = "ife0", "dualife0"; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x1c8 0x01>; | |
| clocks = <0x3b 0x0f>; | |
| label = "rt-cdm"; | |
| clock-cntl-level = "turbo"; | |
| cam_hw_pid = <0x19>; | |
| compatible = "qcom,cam-rt-cdm2_1"; | |
| gdsc-supply = <0x2d9>; | |
| status = "ok"; | |
| interrupt-names = "rt-cdm0"; | |
| reg = <0xac25000 0x400>; | |
| regulator-names = "gdsc"; | |
| cam-hw-mid = <0x00>; | |
| nrt-device; | |
| single-context-cdm; | |
| clock-rates = <0x00>; | |
| config-fifo; | |
| }; | |
| hall@0 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x76d>; | |
| compatible = "qcom,hall-switch"; | |
| hall-gpio = <0x33 0x11 0x00>; | |
| phandle = <0x7b7>; | |
| }; | |
| ete3 { | |
| atid = <0x04>; | |
| qcom,skip-power-up; | |
| cpu = <0x1b>; | |
| coresight-name = "coresight-ete3"; | |
| phy-cpu = <0x03>; | |
| compatible = "arm,embedded-trace-extension"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1e3>; | |
| phandle = <0x1ec>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| mem_dump { | |
| memory-region = <0x1f1>; | |
| compatible = "qcom,mem-dump"; | |
| l1_icache600 { | |
| qcom,dump-size = <0x11100>; | |
| qcom,dump-id = <0x66>; | |
| }; | |
| l2victim600 { | |
| qcom,dump-size = <0x2100>; | |
| qcom,dump-id = <0x1e6>; | |
| }; | |
| l1btb500 { | |
| qcom,dump-size = <0x10100>; | |
| qcom,dump-id = <0x1b5>; | |
| }; | |
| l2_cache600 { | |
| qcom,dump-size = <0x68100>; | |
| qcom,dump-id = <0xc6>; | |
| }; | |
| l1dcmte100 { | |
| qcom,dump-size = <0x1100>; | |
| qcom,dump-id = <0x181>; | |
| }; | |
| l1_dtlb600 { | |
| qcom,dump-size = <0x600>; | |
| qcom,dump-id = <0x46>; | |
| }; | |
| c400_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x04>; | |
| }; | |
| spr_cpu2 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x1f2>; | |
| }; | |
| osm_reg { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x163>; | |
| }; | |
| l0mopca700 { | |
| qcom,dump-size = <0x4100>; | |
| qcom,dump-id = <0x1a7>; | |
| }; | |
| l1_dcache300 { | |
| qcom,dump-size = <0xd100>; | |
| qcom,dump-id = <0x83>; | |
| }; | |
| etflpass_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x104>; | |
| }; | |
| llcc3dc { | |
| qcom,dump-size = <0x171000>; | |
| qcom,dump-id = <0x142>; | |
| }; | |
| l1bim600 { | |
| qcom,dump-size = <0x2100>; | |
| qcom,dump-id = <0x1d6>; | |
| }; | |
| l1ghb500 { | |
| qcom,dump-size = <0x4100>; | |
| qcom,dump-id = <0x1c5>; | |
| }; | |
| l1_itlb700 { | |
| qcom,dump-size = <0x600>; | |
| qcom,dump-id = <0x27>; | |
| }; | |
| l2_tlb700 { | |
| qcom,dump-size = <0xa900>; | |
| qcom,dump-id = <0x127>; | |
| }; | |
| spr_cpu0 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x1f0>; | |
| }; | |
| c0_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x00>; | |
| }; | |
| l1_dcache600 { | |
| qcom,dump-size = <0xd100>; | |
| qcom,dump-id = <0x86>; | |
| }; | |
| l2tldtcsp400 { | |
| qcom,dump-size = <0x7900>; | |
| qcom,dump-id = <0x204>; | |
| }; | |
| etr1_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x105>; | |
| }; | |
| fsm_data { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x165>; | |
| }; | |
| l1_icache200 { | |
| qcom,dump-size = <0x11100>; | |
| qcom,dump-id = <0x62>; | |
| }; | |
| l2_cache200 { | |
| qcom,dump-size = <0x24100>; | |
| qcom,dump-id = <0xc2>; | |
| }; | |
| c200_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x02>; | |
| }; | |
| c700_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x07>; | |
| }; | |
| l1dcdirty100 { | |
| qcom,dump-size = <0x1100>; | |
| qcom,dump-id = <0x171>; | |
| }; | |
| l2dcmte200 { | |
| qcom,dump-size = <0x4100>; | |
| qcom,dump-id = <0x192>; | |
| }; | |
| spr_cpu7 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x1f7>; | |
| }; | |
| l1_icache500 { | |
| qcom,dump-size = <0x11100>; | |
| qcom,dump-id = <0x65>; | |
| }; | |
| l2victim500 { | |
| qcom,dump-size = <0x2100>; | |
| qcom,dump-id = <0x1e5>; | |
| }; | |
| fcm { | |
| qcom,dump-size = <0x8400>; | |
| qcom,dump-id = <0xee>; | |
| }; | |
| l2_cache500 { | |
| qcom,dump-size = <0x68100>; | |
| qcom,dump-id = <0xc5>; | |
| }; | |
| rpm_sw { | |
| qcom,dump-size = <0x28000>; | |
| qcom,dump-id = <0xea>; | |
| }; | |
| l1_dtlb500 { | |
| qcom,dump-size = <0x600>; | |
| qcom,dump-id = <0x45>; | |
| }; | |
| etfswao_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x102>; | |
| }; | |
| l1_dcache0 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x80>; | |
| }; | |
| l0mopca600 { | |
| qcom,dump-size = <0x4100>; | |
| qcom,dump-id = <0x1a6>; | |
| }; | |
| l1_dcache200 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x82>; | |
| }; | |
| spr_cpu5 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x1f5>; | |
| }; | |
| llcc2dc { | |
| qcom,dump-size = <0x171000>; | |
| qcom,dump-id = <0x141>; | |
| }; | |
| l2_tlb0 { | |
| qcom,dump-size = <0xf700>; | |
| qcom,dump-id = <0x120>; | |
| }; | |
| l1bim500 { | |
| qcom,dump-size = <0x2100>; | |
| qcom,dump-id = <0x1d5>; | |
| }; | |
| l1_itlb600 { | |
| qcom,dump-size = <0x600>; | |
| qcom,dump-id = <0x26>; | |
| }; | |
| l2_tlb600 { | |
| qcom,dump-size = <0x7900>; | |
| qcom,dump-id = <0x126>; | |
| }; | |
| l1dcdirty0 { | |
| qcom,dump-size = <0x1100>; | |
| qcom,dump-id = <0x170>; | |
| }; | |
| etr_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x100>; | |
| }; | |
| c500_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x05>; | |
| }; | |
| l1dcmte0 { | |
| qcom,dump-size = <0x1100>; | |
| qcom,dump-id = <0x180>; | |
| }; | |
| gemnoc { | |
| qcom,dump-size = <0x100000>; | |
| qcom,dump-id = <0x162>; | |
| }; | |
| l1_dcache500 { | |
| qcom,dump-size = <0xd100>; | |
| qcom,dump-id = <0x85>; | |
| }; | |
| l2tldtcsp300 { | |
| qcom,dump-size = <0x7900>; | |
| qcom,dump-id = <0x203>; | |
| }; | |
| spr_cpu3 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x1f3>; | |
| }; | |
| pmic { | |
| qcom,dump-size = <0x200000>; | |
| qcom,dump-id = <0xe4>; | |
| }; | |
| l1_icache100 { | |
| qcom,dump-size = <0x11100>; | |
| qcom,dump-id = <0x61>; | |
| }; | |
| l2_cache100 { | |
| qcom,dump-size = <0x24100>; | |
| qcom,dump-id = <0xc1>; | |
| }; | |
| etf_slpi { | |
| qcom,dump-size = <0x4000>; | |
| qcom,dump-id = <0xf3>; | |
| }; | |
| l2dcmte100 { | |
| qcom,dump-size = <0x4100>; | |
| qcom,dump-id = <0x191>; | |
| }; | |
| spr_cpu1 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x1f1>; | |
| }; | |
| l1_icache400 { | |
| qcom,dump-size = <0x11100>; | |
| qcom,dump-id = <0x64>; | |
| }; | |
| etfslpi_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x103>; | |
| }; | |
| l2_cache400 { | |
| qcom,dump-size = <0xd0100>; | |
| qcom,dump-id = <0xc4>; | |
| }; | |
| l2tldtcmp400 { | |
| qcom,dump-size = <0x1300>; | |
| qcom,dump-id = <0x214>; | |
| }; | |
| c300_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x03>; | |
| }; | |
| l2_tlb200 { | |
| qcom,dump-size = <0xf700>; | |
| qcom,dump-id = <0x122>; | |
| }; | |
| l0mopca500 { | |
| qcom,dump-size = <0x4100>; | |
| qcom,dump-id = <0x1a5>; | |
| }; | |
| l1_dcache100 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x81>; | |
| }; | |
| etf_swao { | |
| qcom,dump-size = <0x10000>; | |
| qcom,dump-id = <0xf1>; | |
| }; | |
| cpuss_reg { | |
| qcom,dump-size = <0x30000>; | |
| qcom,dump-id = <0xef>; | |
| }; | |
| l1_icache700 { | |
| qcom,dump-size = <0x22100>; | |
| qcom,dump-id = <0x67>; | |
| }; | |
| l2victim700 { | |
| qcom,dump-size = <0x2100>; | |
| qcom,dump-id = <0x1e7>; | |
| }; | |
| pcu_reg { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x164>; | |
| }; | |
| llcc1dc { | |
| qcom,dump-size = <0x171000>; | |
| qcom,dump-id = <0x140>; | |
| }; | |
| l1btb600 { | |
| qcom,dump-size = <0x10100>; | |
| qcom,dump-id = <0x1b6>; | |
| }; | |
| l2_cache700 { | |
| qcom,dump-size = <0x1a0100>; | |
| qcom,dump-id = <0xc7>; | |
| }; | |
| l1dcmte200 { | |
| qcom,dump-size = <0x1100>; | |
| qcom,dump-id = <0x182>; | |
| }; | |
| l2dcmte0 { | |
| qcom,dump-size = <0x4100>; | |
| qcom,dump-id = <0x190>; | |
| }; | |
| l1_itlb500 { | |
| qcom,dump-size = <0x600>; | |
| qcom,dump-id = <0x25>; | |
| }; | |
| l1_dtlb700 { | |
| qcom,dump-size = <0x600>; | |
| qcom,dump-id = <0x47>; | |
| }; | |
| l2_tlb500 { | |
| qcom,dump-size = <0x7900>; | |
| qcom,dump-id = <0x125>; | |
| }; | |
| l1_icache0 { | |
| qcom,dump-size = <0x11100>; | |
| qcom,dump-id = <0x60>; | |
| }; | |
| misc_data { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0xe8>; | |
| }; | |
| l2_cache0 { | |
| qcom,dump-size = <0x24100>; | |
| qcom,dump-id = <0xc0>; | |
| }; | |
| l1_dcache400 { | |
| qcom,dump-size = <0xd100>; | |
| qcom,dump-id = <0x84>; | |
| }; | |
| etf_lpass { | |
| qcom,dump-size = <0x4000>; | |
| qcom,dump-id = <0xf4>; | |
| }; | |
| llcc4dc { | |
| qcom,dump-size = <0x171000>; | |
| qcom,dump-id = <0x143>; | |
| }; | |
| l1ghb600 { | |
| qcom,dump-size = <0x4100>; | |
| qcom,dump-id = <0x1c6>; | |
| }; | |
| c100_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x01>; | |
| }; | |
| c600_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x06>; | |
| }; | |
| spr_cpu6 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x1f6>; | |
| }; | |
| rpmh { | |
| qcom,dump-size = <0x2000000>; | |
| qcom,dump-id = <0xec>; | |
| }; | |
| l1_dcache700 { | |
| qcom,dump-size = <0x1a100>; | |
| qcom,dump-id = <0x87>; | |
| }; | |
| l1_icache300 { | |
| qcom,dump-size = <0x11100>; | |
| qcom,dump-id = <0x63>; | |
| }; | |
| l2_cache300 { | |
| qcom,dump-size = <0xd0100>; | |
| qcom,dump-id = <0xc3>; | |
| }; | |
| l2tldtcmp300 { | |
| qcom,dump-size = <0x1300>; | |
| qcom,dump-id = <0x213>; | |
| }; | |
| l2_tlb100 { | |
| qcom,dump-size = <0xf700>; | |
| qcom,dump-id = <0x121>; | |
| }; | |
| l1dcdirty200 { | |
| qcom,dump-size = <0x1100>; | |
| qcom,dump-id = <0x172>; | |
| }; | |
| spr_cpu4 { | |
| qcom,dump-size = <0x2000>; | |
| qcom,dump-id = <0x1f4>; | |
| }; | |
| }; | |
| stm@10002000 { | |
| arm,primecell-periphid = <0xbb962>; | |
| atid = <0x10>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "stm-base", "stm-stimulus-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-stm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10002000 0x1000 0x16280000 0x180000>; | |
| phandle = <0x416>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10d>; | |
| phandle = <0x1ba>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply_avdd { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x7b0>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-name = "avdd"; | |
| qcom,supply-max-voltage = <0x2ab980>; | |
| reg = <0x01>; | |
| qcom,supply-min-voltage = <0x2ab980>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-enable-load = <0x30d40>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| }; | |
| }; | |
| qcom,secure-buffer { | |
| compatible = "qcom,secure-buffer"; | |
| qcom,vmid-cp-camera-preview-ro; | |
| }; | |
| funnel@10d32000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-ddr_ch13"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10d32000 0x1000>; | |
| phandle = <0x43a>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x147>; | |
| phandle = <0xf8>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x148>; | |
| phandle = <0x14d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,wb-display@1 { | |
| cell-index = <0x00>; | |
| label = "wb_display1"; | |
| compatible = "qcom,wb-display"; | |
| phandle = <0x74b>; | |
| }; | |
| cti@10901000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-gpu_dl"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10901000 0x1000>; | |
| phandle = <0x467>; | |
| }; | |
| qcom,qrtr-mhi-cnss { | |
| qcom,dev-id = <0x1107>; | |
| qcom,net-id = <0x01>; | |
| qcom,low-latency; | |
| compatible = "qcom,qrtr-mhi"; | |
| }; | |
| tpdm@10c39000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-rdpm-mx"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10c39000 0x1000>; | |
| phandle = <0x173>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xff>; | |
| phandle = <0x169>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@1382e000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-riscv_sifive_cti"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x1382e000 0x1000>; | |
| phandle = <0x479>; | |
| }; | |
| disp_rsc@af20000 { | |
| reg-names = "drv-0"; | |
| interrupts = <0x00 0x81 0x04>; | |
| clocks = <0x3c 0x46>; | |
| label = "disp_rsc"; | |
| compatible = "qcom,rpmh-rsc"; | |
| reg = <0xaf20000 0x10000>; | |
| phandle = <0x34a>; | |
| qcom,drv-count = <0x01>; | |
| drv@0 { | |
| qcom,drv-id = <0x00>; | |
| qcom,tcs-offset = <0x1c00>; | |
| phandle = <0x34b>; | |
| sde_rsc_rpmh { | |
| cell-index = <0x00>; | |
| compatible = "qcom,sde-rsc-rpmh"; | |
| }; | |
| channel@0 { | |
| qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x04 0x00>; | |
| }; | |
| bcm_voter { | |
| qcom,tcs-wait = <0x01>; | |
| compatible = "qcom,bcm-voter"; | |
| phandle = <0x41>; | |
| }; | |
| }; | |
| }; | |
| cti@10010000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| pinctrl-names = "cti-trigout-pctrl"; | |
| qcom,cti-gpio-trigout = <0x10>; | |
| pinctrl-0 = <0x1df>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-qc_cti"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x10010000 0x1000>; | |
| phandle = <0x45e>; | |
| }; | |
| qcom,cam-res-mgr { | |
| compatible = "qcom,cam-res-mgr"; | |
| status = "ok"; | |
| }; | |
| cti@1382b000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-riscv_cti"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x1382b000 0x1000>; | |
| phandle = <0x478>; | |
| }; | |
| qcom,cpu-hotplug { | |
| compatible = "qcom,cpu-hotplug"; | |
| cpu4-hotplug { | |
| qcom,cpu = <0x1c>; | |
| qcom,cdev-alias = "cpu-hotplug4"; | |
| phandle = <0xaa>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu6-hotplug { | |
| qcom,cpu = <0x1e>; | |
| qcom,cdev-alias = "cpu-hotplug6"; | |
| phandle = <0xb6>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu1-hotplug { | |
| qcom,cpu = <0x19>; | |
| qcom,cdev-alias = "cpu-hotplug1"; | |
| phandle = <0xc5>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu3-hotplug { | |
| qcom,cpu = <0x1b>; | |
| qcom,cdev-alias = "cpu-hotplug3"; | |
| phandle = <0xa4>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu5-hotplug { | |
| qcom,cpu = <0x1d>; | |
| qcom,cdev-alias = "cpu-hotplug5"; | |
| phandle = <0xb0>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu7-hotplug { | |
| qcom,cpu = <0x1f>; | |
| qcom,cdev-alias = "cpu-hotplug7"; | |
| phandle = <0xbc>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu2-hotplug { | |
| qcom,cpu = <0x1a>; | |
| qcom,cdev-alias = "cpu-hotplug2"; | |
| phandle = <0xc9>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| modem_etm0 { | |
| atid = <0x24 0x25>; | |
| qcom,inst-id = <0x02>; | |
| coresight-name = "coresight-modem-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x11d>; | |
| phandle = <0x18a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm_fastrpc { | |
| qcom,fastrpc-adsp-audio-pdr; | |
| qcom,qos-cores = <0x00 0x01 0x02>; | |
| qcom,rpc-latency-us = <0xeb>; | |
| compatible = "qcom,msm-fastrpc-compute"; | |
| qcom,fastrpc-adsp-sensors-pdr; | |
| phandle = <0x3e4>; | |
| qcom,fastrpc-gids = <0xb5c>; | |
| qcom,adsp-remoteheap-vmid = <0x16 0x25>; | |
| qcom,msm_fastrpc_compute_cb3 { | |
| iommus = <0x4c 0x1963 0x00 0x4c 0xc03 0x20 0x4c 0x19c3 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb1 { | |
| iommus = <0x4c 0x1961 0x00 0x4c 0xc01 0x20 0x4c 0x19c1 0x10>; | |
| dma-coherent; | |
| pd-type = <0x01>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb17 { | |
| iommus = <0x4c 0x196e 0x00 0x4c 0xc0e 0x20 0x4c 0x19ce 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb15 { | |
| iommus = <0x4c 0x196c 0x00 0x4c 0xc0c 0x20 0x4c 0x19cc 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb8 { | |
| iommus = <0x4c 0x1968 0x00 0x4c 0xc08 0x20 0x4c 0x19c8 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb13 { | |
| iommus = <0x4c 0x1006 0x80 0x4c 0x1066 0x00>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb6 { | |
| iommus = <0x4c 0x1966 0x00 0x4c 0xc06 0x20 0x4c 0x19c6 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb11 { | |
| iommus = <0x4c 0x1004 0x80 0x4c 0x1064 0x00>; | |
| dma-coherent; | |
| pd-type = <0x02>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb4 { | |
| iommus = <0x4c 0x1964 0x00 0x4c 0xc04 0x20 0x4c 0x19c4 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb2 { | |
| iommus = <0x4c 0x1962 0x00 0x4c 0xc02 0x20 0x4c 0x19c2 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb18 { | |
| iommus = <0x4c 0x196f 0x00 0x4c 0xc0f 0x20 0x4c 0x19cf 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb16 { | |
| iommus = <0x4c 0x196d 0x00 0x4c 0xc0d 0x20 0x4c 0x19cd 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb9 { | |
| iommus = <0x4c 0x1969 0x00 0x4c 0xc09 0x20 0x4c 0x19c9 0x10>; | |
| dma-coherent; | |
| qcom,secure-context-bank; | |
| pd-type = <0x06>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb14 { | |
| iommus = <0x4c 0x1007 0x80 0x4c 0x1067 0x00>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb7 { | |
| iommus = <0x4c 0x1967 0x00 0x4c 0xc07 0x20 0x4c 0x19c7 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb12 { | |
| iommus = <0x4c 0x1005 0x80 0x4c 0x1065 0x00>; | |
| dma-coherent; | |
| shared-cb = <0x08>; | |
| pd-type = <0x03>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb5 { | |
| iommus = <0x4c 0x1965 0x00 0x4c 0xc05 0x20 0x4c 0x19c5 0x10>; | |
| dma-coherent; | |
| qcom,iova-max-align-shift = <0x09>; | |
| pd-type = <0x07>; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb10 { | |
| iommus = <0x4c 0x1003 0x80 0x4c 0x1063 0x00>; | |
| dma-coherent; | |
| pd-type = <0x01>; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; | |
| qcom,iommu-faults = "stall-disable", "HUPCF"; | |
| }; | |
| }; | |
| qcom,ddr-cdev { | |
| qcom,freq-table = <0x858b8 0xbb800 0x17bb00 0x1a1300 0x1fef00 0x29bf80 0x30c780 0x392100 0x410a00>; | |
| qcom,bus-width = <0x04>; | |
| interconnects = <0x4b 0x03 0x4b 0x200>; | |
| compatible = "qcom,ddr-cooling-device"; | |
| phandle = <0xd0>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| tpdm@138a0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x42>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-llm-silver"; | |
| compatible = "arm,primecell"; | |
| reg = <0x138a0000 0x1000>; | |
| phandle = <0x41e>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x116>; | |
| phandle = <0x193>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,qupv3_2_geni_se@8c0000 { | |
| iommus = <0x4c 0x423 0x00>; | |
| #address-cells = <0x01>; | |
| dma-coherent; | |
| clock-names = "m-ahb", "s-ahb"; | |
| clocks = <0x45 0x81 0x45 0x82>; | |
| #size-cells = <0x01>; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| compatible = "qcom,geni-se-qup"; | |
| ranges; | |
| status = "ok"; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| reg = <0x8c0000 0x2000>; | |
| phandle = <0x4a5>; | |
| qcom,iommu-dma = "fastmap"; | |
| i3c-master@880000 { | |
| pinctrl-names = "default", "sleep", "disable"; | |
| #address-cells = <0x03>; | |
| pinctrl-2 = <0x251>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x24d 0x24e>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| qcom,ibi-ctrl-id = <0x10>; | |
| clocks = <0x45 0x6f>; | |
| #size-cells = <0x00>; | |
| interrupts-extended = <0x01 0x00 0x175 0x04 0x51 0x23 0x04 0x51 0x22 0x04>; | |
| compatible = "qcom,geni-i3c"; | |
| pinctrl-1 = <0x24f 0x250>; | |
| status = "disabled"; | |
| reg = <0x880000 0x4000 0xecb000 0x10000>; | |
| phandle = <0x4a7>; | |
| }; | |
| spi@88c000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x26f 0x270 0x271>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x249 0x04>; | |
| clocks = <0x45 0x75>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x272>; | |
| status = "disabled"; | |
| reg = <0x88c000 0x4000>; | |
| phandle = <0x4af>; | |
| dmas = <0x24c 0x00 0x03 0x01 0x40 0x00 0x24c 0x01 0x03 0x01 0x40 0x00>; | |
| }; | |
| spi@894000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x27e 0x27f 0x280 0x281>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x24b 0x04>; | |
| clocks = <0x45 0x79>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x282>; | |
| status = "disabled"; | |
| reg = <0x894000 0x4000>; | |
| phandle = <0x4b3>; | |
| dmas = <0x24c 0x00 0x05 0x01 0x40 0x00 0x24c 0x01 0x05 0x01 0x40 0x00>; | |
| }; | |
| spi@880000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x252 0x253 0x254 0x255>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x175 0x04>; | |
| clocks = <0x45 0x6f>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x256>; | |
| status = "disabled"; | |
| reg = <0x880000 0x4000>; | |
| phandle = <0x4a8>; | |
| dmas = <0x24c 0x00 0x00 0x01 0x40 0x02 0x24c 0x01 0x00 0x01 0x40 0x02>; | |
| }; | |
| i2c@884000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x257 0x258>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| interrupts = <0x00 0x247 0x04>; | |
| clocks = <0x45 0x71>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x259>; | |
| status = "disabled"; | |
| reg = <0x884000 0x4000>; | |
| phandle = <0x4a9>; | |
| dmas = <0x24c 0x00 0x01 0x03 0x40 0x00 0x24c 0x01 0x01 0x03 0x40 0x00>; | |
| }; | |
| spi@89c000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x291 0x292 0x293 0x294>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x1ce 0x04>; | |
| clocks = <0x45 0x7d>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x295>; | |
| status = "disabled"; | |
| reg = <0x89c000 0x4000>; | |
| phandle = <0x4b7>; | |
| dmas = <0x24c 0x00 0x07 0x01 0x40 0x00 0x24c 0x01 0x07 0x01 0x40 0x00>; | |
| }; | |
| spi@890000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x276 0x277 0x278 0x279>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x24a 0x04>; | |
| clocks = <0x45 0x77>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x27a>; | |
| status = "disabled"; | |
| reg = <0x890000 0x4000>; | |
| phandle = <0x4b1>; | |
| dmas = <0x24c 0x00 0x04 0x01 0x40 0x00 0x24c 0x01 0x04 0x01 0x40 0x00>; | |
| }; | |
| i2c@88c000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x26c 0x26d>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| interrupts = <0x00 0x249 0x04>; | |
| clocks = <0x45 0x75>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x26e>; | |
| status = "disabled"; | |
| reg = <0x88c000 0x4000>; | |
| phandle = <0x4ae>; | |
| dmas = <0x24c 0x00 0x03 0x03 0x40 0x00 0x24c 0x01 0x03 0x03 0x40 0x00>; | |
| }; | |
| spi@888000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x267 0x268 0x269 0x26a>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x248 0x04>; | |
| clocks = <0x45 0x73>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x26b>; | |
| status = "disabled"; | |
| reg = <0x888000 0x4000>; | |
| phandle = <0x4ad>; | |
| dmas = <0x24c 0x00 0x02 0x01 0x40 0x00 0x24c 0x01 0x02 0x01 0x40 0x00>; | |
| }; | |
| qcom,qup_uart@89c000 { | |
| pinctrl-names = "default", "sleep"; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x28b 0x28c>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| clocks = <0x45 0x7d>; | |
| interrupts-extended = <0x01 0x00 0x1ce 0x04>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-1 = <0x28d>; | |
| status = "ok"; | |
| reg = <0x89c000 0x4000>; | |
| phandle = <0x4b5>; | |
| qcom,wakeup-byte = <0xfd>; | |
| }; | |
| i2c@894000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x27b 0x27c>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| interrupts = <0x00 0x24b 0x04>; | |
| clocks = <0x45 0x79>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x27d>; | |
| status = "disabled"; | |
| reg = <0x894000 0x4000>; | |
| phandle = <0x4b2>; | |
| dmas = <0x24c 0x00 0x05 0x03 0x40 0x00 0x24c 0x01 0x05 0x03 0x40 0x00>; | |
| }; | |
| i2c@880000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x249 0x24a>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| interrupts = <0x00 0x175 0x04>; | |
| clocks = <0x45 0x6f>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x24b>; | |
| status = "disabled"; | |
| reg = <0x880000 0x4000>; | |
| phandle = <0x4a6>; | |
| dmas = <0x24c 0x00 0x00 0x03 0x40 0x02 0x24c 0x01 0x00 0x03 0x40 0x02>; | |
| }; | |
| i3c-master@884000 { | |
| pinctrl-names = "default", "sleep", "disable"; | |
| #address-cells = <0x03>; | |
| pinctrl-2 = <0x25e>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x25a 0x25b>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| qcom,ibi-ctrl-id = <0x0f>; | |
| clocks = <0x45 0x71>; | |
| i3c-scl-hz = <0xbebc20>; | |
| dfs-index = <0x00>; | |
| #size-cells = <0x00>; | |
| interrupts-extended = <0x01 0x00 0x247 0x04 0x51 0x25 0x04 0x51 0x24 0x04>; | |
| compatible = "qcom,geni-i3c"; | |
| pinctrl-1 = <0x25c 0x25d>; | |
| status = "disabled"; | |
| reg = <0x884000 0x4000 0xecc0000 0x10000>; | |
| phandle = <0x4aa>; | |
| i2c-scl-hz = <0x186a0>; | |
| se-clock-frequency = <0x5f5e100>; | |
| qcom,eeprom@50 { | |
| cam_v_custom1-supply = <0x335>; | |
| rgltr-max-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80 0x1b7740>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| i3c-i2c-target; | |
| pinctrl-0 = <0x55a 0x568>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x08>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| clocks = <0x3b 0x63>; | |
| rgltr-load-current = <0xdac 0xdef30 0x00 0x164a4 0x19258 0xf67c>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x337>; | |
| gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; | |
| cam_vaf-supply = <0x33e>; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x338>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-i2c-eeprom", "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80 0x1b7740>; | |
| pinctrl-1 = <0x55b 0x569>; | |
| status = "disabled"; | |
| reg = <0x50 0x00 0x10>; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf", "cam_v_custom1"; | |
| phandle = <0x740>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x33 0x66 0x00 0x33 0x76 0x00>; | |
| }; | |
| qcom,actuator@c { | |
| rgltr-max-voltage = <0x2d2a80>; | |
| i3c-i2c-target; | |
| cell-index = <0x08>; | |
| rgltr-load-current = <0x19258>; | |
| rgltr-cntrl-support; | |
| cam_vaf-supply = <0x33e>; | |
| compatible = "qcom,cam-i2c-actuator", "qcom,actuator"; | |
| rgltr-min-voltage = <0x2d2a80>; | |
| status = "disabled"; | |
| reg = <0x0c 0x00 0x10>; | |
| regulator-names = "cam_vaf"; | |
| phandle = <0x73f>; | |
| }; | |
| qcom,cam-sensor@34,36007660000 { | |
| cam_v_custom1-supply = <0x335>; | |
| rgltr-max-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80 0x1b7740>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| eeprom-src = <0x740>; | |
| scl-hz = "", "=\t"; | |
| pinctrl-0 = <0x55a 0x568>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x08>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| sensor-position-yaw = <0xb4>; | |
| i3c-target; | |
| clocks = <0x3b 0x63>; | |
| rgltr-load-current = <0xdac 0xdef30 0x00 0x164a4 0x19258 0xf67c>; | |
| actuator-src = <0x73f>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x337>; | |
| gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; | |
| cam_vaf-supply = <0x33e>; | |
| gpio-reset = <0x01>; | |
| assigned-address = <0x0a>; | |
| csiphy-sd-index = <0x02>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x338>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80 0x1b7740>; | |
| led-flash-src = <0x73a>; | |
| sensor-position-roll = <0x5a>; | |
| pinctrl-1 = <0x55b 0x569>; | |
| status = "disabled"; | |
| reg = <0x34 0x360 0x7660000>; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf", "cam_v_custom1"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x33 0x66 0x00 0x33 0x76 0x00>; | |
| }; | |
| }; | |
| i2c@89c000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x28e 0x28f>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| interrupts = <0x00 0x1ce 0x04>; | |
| clocks = <0x45 0x7d>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x290>; | |
| status = "disabled"; | |
| reg = <0x89c000 0x4000>; | |
| phandle = <0x4b6>; | |
| dmas = <0x24c 0x00 0x07 0x03 0x40 0x00 0x24c 0x01 0x07 0x03 0x40 0x00>; | |
| }; | |
| spi@884000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x25f 0x260 0x261 0x262>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x247 0x04>; | |
| clocks = <0x45 0x71>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x263>; | |
| status = "disabled"; | |
| reg = <0x884000 0x4000>; | |
| phandle = <0x4ab>; | |
| dmas = <0x24c 0x00 0x01 0x01 0x40 0x00 0x24c 0x01 0x01 0x01 0x40 0x00>; | |
| }; | |
| i2c@890000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x273 0x274>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| interrupts = <0x00 0x24a 0x04>; | |
| clocks = <0x45 0x77>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x275>; | |
| status = "ok"; | |
| reg = <0x890000 0x4000>; | |
| phandle = <0x2ca>; | |
| dmas = <0x24c 0x00 0x04 0x03 0x40 0x00 0x24c 0x01 0x04 0x03 0x40 0x00>; | |
| pcie_i2c_ctrl { | |
| reg_update = <0x82c030 0x01 0x828000 0x03 0x82bd00 0x08 0x82c030 0x02 0x828000 0x03 0x82bd00 0x08 0x82c030 0x08 0x828000 0x01 0x82bd00 0x08>; | |
| ep-reset-reg = <0x801210>; | |
| dump-regs = <0x801330 0x801350 0x801370>; | |
| compatible = "qcom,pcie1-i2c-ntn3"; | |
| gpio-config-reg = <0x801208>; | |
| reg = <0x77>; | |
| phandle = <0x4b0>; | |
| ep-reset-gpio-mask = <0x0c>; | |
| }; | |
| htr3212r@3c { | |
| htr3212r,mcu-uart-en = <0x33 0x0c 0x00>; | |
| compatible = "kona,htr3212r"; | |
| htr3212r,mcu-vdd = <0x33 0x63 0x00>; | |
| reg = <0x3c>; | |
| htr3212r,dv-en2 = <0x33 0x38 0x00>; | |
| }; | |
| }; | |
| i2c@888000 { | |
| pinctrl-names = "default", "sleep"; | |
| #address-cells = <0x01>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x264 0x265>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| interrupts = <0x00 0x248 0x04>; | |
| clocks = <0x45 0x73>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx", "rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x266>; | |
| status = "disabled"; | |
| reg = <0x888000 0x4000>; | |
| phandle = <0x4ac>; | |
| dmas = <0x24c 0x00 0x02 0x03 0x40 0x00 0x24c 0x01 0x02 0x03 0x40 0x00>; | |
| }; | |
| qcom,qup_uart@898000 { | |
| pinctrl-names = "default", "active", "sleep", "shutdown"; | |
| pinctrl-2 = <0x287 0x288 0x289 0x286>; | |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| pinctrl-0 = <0x283 0x284 0x285 0x286>; | |
| clock-names = "se-clk"; | |
| interconnects = <0x1fa 0x26 0x1fa 0x23f 0x61 0x02 0x62 0x21e 0x4a 0x08 0x4b 0x200>; | |
| reg-names = "se_phys"; | |
| clocks = <0x45 0x7b>; | |
| interrupts-extended = <0x01 0x00 0x1cd 0x04 0x33 0x4f 0x04>; | |
| pinctrl-3 = <0x283 0x284 0x285 0x286>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-1 = <0x287 0x288 0x289 0x28a>; | |
| status = "ok"; | |
| reg = <0x898000 0x4000>; | |
| phandle = <0x4b4>; | |
| qcom,wakeup-byte = <0xfd>; | |
| }; | |
| }; | |
| remoteproc-adsp@03000000 { | |
| qcom,smem-state-names = "stop"; | |
| interconnect-names = "rproc_ddr", "crypto_ddr"; | |
| mx-supply = <0x71>; | |
| clock-names = "xo"; | |
| interconnects = <0x72 0x29 0x4b 0x200 0x4a 0x27 0x4b 0x200>; | |
| reg-names = "cx", "mx"; | |
| qcom,qmp = <0x4e>; | |
| memory-region = <0x73 0x74>; | |
| clocks = <0x46 0x00>; | |
| mx-uV-uA = <0x180 0x00>; | |
| qcom,signal-aop; | |
| interrupts-extended = <0x51 0x06 0x01 0x75 0x00 0x00 0x75 0x02 0x00 0x75 0x01 0x00 0x75 0x03 0x00 0x75 0x07 0x00>; | |
| cx-supply = <0x70>; | |
| compatible = "qcom,kalama-adsp-pas"; | |
| status = "ok"; | |
| interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack", "shutdown-ack"; | |
| reg = <0x3000000 0x10000>; | |
| phandle = <0x23>; | |
| qcom,smem-states = <0x76 0x00>; | |
| cx-uV-uA = <0x180 0x00>; | |
| glink-edge { | |
| transport = "smem"; | |
| interrupts = <0x03 0x00 0x01>; | |
| qcom,glink-label = "lpass"; | |
| interrupt-parent = <0x4f>; | |
| label = "adsp"; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x3e5>; | |
| mboxes = <0x4f 0x03 0x00>; | |
| mbox-names = "adsp_smem"; | |
| qcom,pmic_glink_log_rpmsg { | |
| qcom,intents = <0x800 0x05 0xc00 0x03 0x2000 0x01>; | |
| qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; | |
| }; | |
| qcom,msm_adspsleepmon_rpmsg { | |
| qcom,intents = <0x1000 0x08>; | |
| compatible = "qcom,msm-adspsleepmon-rpmsg"; | |
| qcom,glink-channels = "sleepmonglink-apps-adsp"; | |
| }; | |
| qcom,msm_fastrpc_rpmsg { | |
| qcom,intents = <0x64 0x40>; | |
| compatible = "qcom,msm-fastrpc-rpmsg"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| }; | |
| qcom,pmic_glink_rpmsg { | |
| qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; | |
| }; | |
| qcom,gpr { | |
| qcom,intents = <0x200 0x14>; | |
| compatible = "qcom,gpr"; | |
| reg = <0x02>; | |
| phandle = <0x52c>; | |
| qcom,glink-channels = "adsp_apps"; | |
| audio-pkt { | |
| qcom,audiopkt-ch-name = "apr_audio_svc"; | |
| compatible = "qcom,audio-pkt"; | |
| reg = <0x17>; | |
| }; | |
| q6prm { | |
| compatible = "qcom,audio_prm"; | |
| reg = <0x07>; | |
| phandle = <0x52d>; | |
| }; | |
| spf_core { | |
| compatible = "qcom,spf_core"; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| qcom,adsp_qrtr { | |
| qcom,net-id = <0x02>; | |
| qcom,no-wake-svc = <0x190>; | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@abf8078 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0xa7>; | |
| regulator-name = "video_cc_mvs1c_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xabf8078 0x04>; | |
| phandle = <0x2ba>; | |
| }; | |
| sys-pm-vx@c320000 { | |
| compatible = "qcom,sys-pm-violators", "qcom,sys-pm-kalama"; | |
| reg = <0xc320000 0x400>; | |
| mboxes = <0x02 0x00>; | |
| mbox-names = "aop"; | |
| }; | |
| interrupt-controller@b220000 { | |
| qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x1f 0x7d 0x3f 0x01 0x7e 0x2cc 0x0c 0x8a 0xfb 0x05>; | |
| interrupt-parent = <0x01>; | |
| compatible = "qcom,kalama-pdc", "qcom,pdc"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0xb220000 0x30000 0x174000f0 0x64>; | |
| phandle = <0x51>; | |
| interrupt-controller; | |
| }; | |
| cam_rsc@add9000 { | |
| reg-names = "drv-0", "drv-1", "drv-2"; | |
| interrupts = <0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04>; | |
| clocks = <0x3b 0x3a>; | |
| label = "cam_rsc"; | |
| qcom,hw-channel; | |
| compatible = "qcom,rpmh-rsc"; | |
| reg = <0xadd9000 0x1000 0xadda000 0x1000 0xaddb000 0x1000>; | |
| phandle = <0x346>; | |
| qcom,drv-count = <0x03>; | |
| drv@1 { | |
| qcom,drv-id = <0x01>; | |
| qcom,tcs-offset = <0x520>; | |
| phandle = <0x348>; | |
| channel@0 { | |
| qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; | |
| }; | |
| bcm_voter { | |
| compatible = "qcom,bcm-voter"; | |
| phandle = <0x43>; | |
| }; | |
| channel@1 { | |
| qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; | |
| }; | |
| }; | |
| drv@2 { | |
| qcom,drv-id = <0x02>; | |
| qcom,tcs-offset = <0x520>; | |
| phandle = <0x349>; | |
| channel@0 { | |
| qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; | |
| }; | |
| bcm_voter { | |
| compatible = "qcom,bcm-voter"; | |
| phandle = <0x44>; | |
| }; | |
| channel@1 { | |
| qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; | |
| }; | |
| }; | |
| drv@0 { | |
| qcom,drv-id = <0x00>; | |
| qcom,tcs-offset = <0x520>; | |
| phandle = <0x347>; | |
| channel@0 { | |
| qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; | |
| }; | |
| bcm_voter { | |
| compatible = "qcom,bcm-voter"; | |
| phandle = <0x42>; | |
| }; | |
| channel@1 { | |
| qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; | |
| }; | |
| }; | |
| }; | |
| cti@10d11000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-ddrss_shrm2"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10d11000 0x1000>; | |
| phandle = <0x484>; | |
| }; | |
| rx_core_tx_clk { | |
| qcom,codec-ext-clk-src = <0x0d>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x661>; | |
| qcom,codec-lpass-clk-id = <0x312>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| qrtr-gunyah-tvm { | |
| qcom,master; | |
| peer-name = <0x02>; | |
| gunyah-label = <0x03>; | |
| compatible = "qcom,qrtr-gunyah"; | |
| shared-buffer = <0x6e>; | |
| }; | |
| ufsphy_mem@1d80000 { | |
| vdd-phy-gdsc-supply = <0x504>; | |
| clock-names = "ref_clk_src", "ref_aux_clk", "qref_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; | |
| reg-names = "phy_mem"; | |
| lanes-per-direction = <0x02>; | |
| resets = <0x64 0x00>; | |
| clocks = <0x46 0x1b 0x45 0x90 0x5e 0x02 0x45 0x94 0x45 0x96 0x45 0x98 0x45 0x93 0x45 0x95 0x45 0x97>; | |
| vdda-phy-supply = <0x315>; | |
| #phy-cells = <0x00>; | |
| vdda-pll-supply = <0x31>; | |
| compatible = "qcom,ufs-phy-qmp-v4-kalama"; | |
| vdda-qref-max-microamp = <0x7530>; | |
| status = "ok"; | |
| vdda-phy-max-microamp = <0x2de60>; | |
| reg = <0x1d80000 0x1934>; | |
| phandle = <0x65>; | |
| vdda-pll-max-microamp = <0x477c>; | |
| vdda-qref-supply = <0x30>; | |
| }; | |
| ssphy@88e8000 { | |
| pinctrl-names = "default"; | |
| qcom,vdd-voltage-level = <0x00 0xdea80 0xdea80>; | |
| pinctrl-0 = <0x2b9>; | |
| clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; | |
| reg-names = "qmp_phy_base"; | |
| resets = <0x45 0x1a 0x45 0x1c>; | |
| clocks = <0x45 0xa2 0x45 0xa5 0x45 0xa6 0x5b 0x46 0x1b 0x5e 0x05 0x45 0xa4>; | |
| usb3_dp_phy_gdsc-supply = <0x2b8>; | |
| vdd-supply = <0x2b7>; | |
| qcom,qmp-phy-reg-offset = <0x1c14 0x1f08 0x1f14 0x1c40 0x1c00 0x1c44 0xffff 0x08 0x04 0x1c 0x00 0x10 0x1e00>; | |
| compatible = "qcom,usb-ssphy-qmp-dp-combo"; | |
| qcom,vdd-max-load-uA = <0xb798>; | |
| reg = <0x88e8000 0x3000>; | |
| phandle = <0x2b6>; | |
| reset-names = "global_phy_reset", "phy_reset"; | |
| qcom,qmp-phy-override-seq = <0x156c 0xee 0x1580 0x0d 0x195c 0x3f 0x1980 0x0e>; | |
| qcom,qmp-phy-init-seq = <0x1000 0xc0 0x1004 0x01 0x1010 0x02 0x1014 0x16 0x1018 0x36 0x101c 0x04 0x1020 0x16 0x1024 0x41 0x1028 0x41 0x102c 0x00 0x1030 0x55 0x1034 0x75 0x1038 0x01 0x103c 0x01 0x1048 0x25 0x104c 0x02 0x1050 0x5c 0x1054 0x0f 0x1058 0x5c 0x105c 0x0f 0x1060 0xc0 0x1064 0x01 0x1070 0x02 0x1074 0x16 0x1078 0x36 0x1080 0x08 0x1084 0x1a 0x1088 0x41 0x108c 0x00 0x1090 0x55 0x1094 0x75 0x1098 0x01 0x10a8 0x25 0x10ac 0x02 0x10bc 0x0a 0x10c0 0x01 0x10cc 0x62 0x10d0 0x02 0x10e8 0x0c 0x1110 0x1a 0x1124 0x14 0x1140 0x04 0x1170 0x20 0x1174 0x16 0x11a4 0xb6 0x11a8 0x4b 0x11ac 0x37 0x11b4 0x0c 0x1234 0x00 0x1238 0x00 0x123c 0x1f 0x1240 0x09 0x1284 0xf5 0x128c 0x3f 0x1290 0x3f 0x1294 0x5f 0x12a4 0x12 0x12e4 0x21 0x1408 0x0a 0x1414 0x06 0x1430 0x2f 0x1434 0x7f 0x143c 0xff 0x1440 0x0f 0x1444 0x99 0x144c 0x08 0x1450 0x08 0x1454 0x00 0x1458 0x0a 0x1460 0xa0 0x14d4 0x54 0x14d8 0x0f 0x14dc 0x13 0x14ec 0x0f 0x14f0 0x4a 0x14f4 0x0a 0x14f8 0x07 0x14fc 0x00 0x1510 0x47 0x151c 0x04 0x1524 0x0e 0x155c 0x3f 0x1560 0xbf 0x1564 0xff 0x1568 0xdf 0x156c 0xed 0x1570 0xdc 0x1574 0x5c 0x1578 0x9c 0x157c 0x1d 0x1580 0x09 0x15a0 0x04 0x15a4 0x38 0x15a8 0x0c 0x15b0 0x10 0x15e4 0x14 0x15f8 0x08 0x1634 0x00 0x1638 0x00 0x163c 0x1f 0x1640 0x09 0x1684 0xf5 0x168c 0x3f 0x1690 0x3f 0x1694 0x5f 0x16a4 0x12 0x16e4 0x05 0x1808 0x0a 0x1814 0x06 0x1830 0x2f 0x1834 0x7f 0x183c 0xff 0x1840 0x0f 0x1844 0x99 0x184c 0x08 0x1850 0x08 0x1854 0x00 0x1858 0x0a 0x1860 0xa0 0x18d4 0x54 0x18d8 0x0f 0x18dc 0x13 0x18ec 0x0f 0x18f0 0x4a 0x18f4 0x0a 0x18f8 0x07 0x18fc 0x00 0x1910 0x47 0x191c 0x04 0x1924 0x0e 0x195c 0xbf 0x1960 0xbf 0x1964 0xbf 0x1968 0xdf 0x196c 0xfd 0x1970 0xdc 0x1974 0x5c 0x1978 0x9c 0x197c 0x1d 0x1980 0x09 0x19a0 0x04 0x19a4 0x38 0x19a8 0x0c 0x19b0 0x10 0x19e4 0x14 0x19f8 0x08 0x1cc4 0xc4 0x1cc8 0x89 0x1ccc 0x20 0x1cd8 0x13 0x1cdc 0x21 0x1d88 0x99 0x1d90 0xe7 0x1d94 0x03 0x1db0 0x0a 0x1dc0 0x88 0x1dc4 0x13 0x1dd0 0x0c 0x1ddc 0x4b 0x1dec 0x10 0x1f00 0x68 0x1f18 0xf8 0x1f3c 0x07 0x1f40 0x40 0x1f44 0x00>; | |
| core-supply = <0x31>; | |
| }; | |
| soc-sleep-stats@c3f0000 { | |
| ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss"; | |
| compatible = "qcom,rpmh-sleep-stats"; | |
| reg = <0xc3f0000 0x400>; | |
| mboxes = <0x02 0x00>; | |
| mbox-names = "aop"; | |
| ddr-freq-update; | |
| qcom,drv-max = <0x14>; | |
| }; | |
| qcom,pcie@0x40000000 { | |
| iommus = <0x4c 0x1480 0x00>; | |
| pinctrl-names = "default"; | |
| qcom,vreg-0p9-voltage-level = <0xdea80 0xd6d80 0x2f1e8>; | |
| interconnect-names = "icc_path"; | |
| qcom,pcie-mhi-a7-irq; | |
| qcom,pcie-device-id = [01 11]; | |
| pinctrl-0 = <0x2cf 0x2d0 0x2d1>; | |
| clock-names = "pcie_pipe_clk", "pcie_0_ref_clk_src", "pcie_aux_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_ldo", "pcie_slv_q2a_axi_clk", "pcie_ddrss_sf_tbu_clk", "pcie_aggre_noc_0_axi_clk", "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk"; | |
| interconnects = <0xed 0x2e 0x4b 0x200>; | |
| reg-names = "msi", "dm_core", "elbi", "iatu", "parf", "phy", "mmio"; | |
| qcom,pcie-phy-ver = <0x08>; | |
| resets = <0x45 0x08 0x45 0x0b 0x45 0x09 0x45 0x0a>; | |
| interrupts = <0x00 0x132 0x04>; | |
| qcom,tcsr-not-supported; | |
| clocks = <0x45 0x34 0x46 0x00 0x45 0x2c 0x45 0x2e 0x45 0x2f 0x45 0x36 0x5e 0x01 0x45 0x37 0x45 0x0e 0x45 0x00 0x45 0x0c 0x45 0x35 0x57 0x45 0x30>; | |
| vreg-1p2-supply = <0x31>; | |
| qcom,phy-status-reg2 = <0x1214>; | |
| clkreq-gpio = <0x33 0x62 0x00>; | |
| gdsc-phy-vdd-supply = <0x2c8>; | |
| vreg-mx-supply = <0x2a>; | |
| qcom,pcie-link-speed = <0x04>; | |
| qcom,no-path-from-ipa-to-pcie; | |
| qcom,phy-init = <0x1240 0x01 0x00 0x30 0x1d 0x00 0x34 0x03 0x00 0x78 0x01 0x00 0x7c 0x00 0x00 0x80 0x51 0x00 0xac 0x34 0x00 0x208 0x0c 0x00 0x20c 0x0a 0x00 0x218 0x04 0x00 0x220 0x16 0x00 0x234 0x00 0x00 0x29c 0x80 0x00 0x2a0 0x7c 0x00 0x2b4 0x05 0x00 0x2e8 0x0a 0x00 0x30c 0x0d 0x00 0x320 0x0b 0x00 0x348 0x1c 0x00 0x388 0x20 0x00 0x394 0x30 0x00 0x3dc 0x09 0x00 0x3f4 0x14 0x00 0x3f8 0xb3 0x00 0x3fc 0x58 0x00 0x400 0x9a 0x00 0x404 0x26 0x00 0x408 0xb6 0x00 0x40c 0xee 0x00 0x410 0xdb 0x00 0x414 0xdb 0x00 0x418 0xa0 0x00 0x41c 0xdf 0x00 0x420 0x78 0x00 0x424 0x76 0x00 0x428 0xff 0x00 0x830 0x1d 0x00 0x834 0x03 0x00 0x878 0x01 0x00 0x87c 0x00 0x00 0x880 0x51 0x00 0x8ac 0x34 0x00 0xa08 0x0c 0x00 0xa0c 0x0a 0x00 0xa18 0x04 0x00 0xa20 0x16 0x00 0xa34 0x00 0x00 0xa9c 0x80 0x00 0xaa0 0x7c 0x00 0xab4 0x05 0x00 0xae8 0x0a 0x00 0xb0c 0x0d 0x00 0xb20 0x0b 0x00 0xb48 0x1c 0x00 0xb88 0x20 0x00 0xb94 0x30 0x00 0xbdc 0x09 0x00 0xbf4 0x14 0x00 0xbf8 0xb3 0x00 0xbfc 0x58 0x00 0xc00 0x9a 0x00 0xc04 0x26 0x00 0xc08 0xb6 0x00 0xc0c 0xee 0x00 0xc10 0xdb 0x00 0xc14 0xdb 0x00 0xc18 0xa0 0x00 0xc1c 0xdf 0x00 0xc20 0x78 0x00 0xc24 0x76 0x00 0xc28 0xff 0x00 0xea0 0x01 0x00 0xeb4 0x00 0x00 0xec4 0x00 0x00 0xec8 0x1f 0x00 0xed4 0x12 0x00 0xed8 0x12 0x00 0xedc 0xdb 0x00 0xee0 0x9a 0x00 0xee4 0x38 0x00 0xee8 0xb6 0x00 0xeec 0x64 0x00 0xef0 0x1f 0x00 0xef4 0x1f 0x00 0xef8 0x1f 0x00 0xefc 0x1f 0x00 0xf00 0x1f 0x00 0xf04 0x1f 0x00 0xf0c 0x1f 0x00 0xf14 0x1f 0x00 0xf1c 0x1f 0x00 0xf28 0x5b 0x00 0x1010 0x28 0x00 0x1014 0x17 0x00 0x1018 0x03 0x00 0x101c 0x04 0x00 0x1020 0xff 0x00 0x1024 0x09 0x00 0x1028 0x28 0x00 0x103c 0x12 0x00 0x1040 0xfb 0x00 0x1044 0x00 0x00 0x1070 0x34 0x00 0x1074 0x11 0x00 0x1078 0x01 0x00 0x107c 0x0a 0x00 0x1080 0xff 0x00 0x1084 0x04 0x00 0x1088 0x19 0x00 0x109c 0x00 0x00 0x10a0 0xfb 0x00 0x10a4 0x00 0x00 0x10bc 0x06 0x00 0x10d8 0x40 0x00 0x10dc 0x14 0x00 0x10e4 0x07 0x00 0x10f4 0x1f 0x00 0x1110 0x00 0x00 0x1120 0x46 0x00 0x1124 0x04 0x00 0x1140 0x14 0x00 0x1170 0xa0 0x00 0x1174 0x06 0x00 0x1184 0x88 0x00 0x1188 0x14 0x00 0x1198 0x0f 0x00 0x1378 0x2e 0x00 0x1390 0xcc 0x00 0x13f8 0x00 0x00 0x13fc 0x22 0x00 0x14a0 0x16 0x00 0x14f0 0x27 0x00 0x14f4 0x27 0x00 0x1508 0x02 0x00 0x155c 0x2e 0x00 0x157c 0x03 0x00 0x1584 0x28 0x00 0x13dc 0x04 0x00 0x13e0 0x02 0x00 0x1418 0xc0 0x00 0x158c 0x0f 0x00 0x15ac 0xf2 0x00 0x15c0 0xf2 0x00 0x1370 0x17 0x00 0x1200 0x00 0x00 0x1244 0x03 0x00>; | |
| wake-gpio = <0x33 0x63 0x00>; | |
| vreg-0p9-supply = <0x2c9>; | |
| vreg-qref-supply = <0x30>; | |
| compatible = "qcom,pcie-ep"; | |
| qcom,aux-clk = <0x14>; | |
| status = "disabled"; | |
| interrupt-names = "int_global"; | |
| reg = <0x40002000 0x1000 0x40000000 0xf20 0x40000f20 0xa8 0x40001000 0x1000 0x1c08000 0x3000 0x1c0e000 0x2000 0x1c0b000 0x1000>; | |
| phandle = <0x4d3>; | |
| qcom,pcie-aggregated-irq; | |
| gdsc-vdd-supply = <0x2c7>; | |
| reset-names = "pcie_core_reset", "pcie_phy_reset", "pcie_link_down_reset", "pcie_phy_nocsr_com_phy_reset"; | |
| qcom,mhi-soc-reset-offset = <0x68c>; | |
| perst-gpio = <0x33 0x61 0x00>; | |
| qcom,vreg-1p2-voltage-level = <0x124f80 0x124f80 0x65f4>; | |
| qcom,pcie-vendor-id = [17 cb]; | |
| qcom,vreg-mx-voltage-level = <0xffff 0x100 0x00>; | |
| qcom,iommu-dma = "bypass"; | |
| }; | |
| cti@138e0000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-apss_cti0"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x138e0000 0x1000>; | |
| phandle = <0x474>; | |
| }; | |
| qcom,rimps_log@d8140000 { | |
| compatible = "qcom,rimps-log"; | |
| reg = <0xd8140000 0x10000 0xd8150000 0x10000>; | |
| phandle = <0x353>; | |
| mboxes = <0x3d 0x01>; | |
| }; | |
| ufs_phy_rx_symbol_1_clk { | |
| clock-output-names = "ufs_phy_rx_symbol_1_clk"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x59>; | |
| }; | |
| ete1 { | |
| atid = <0x02>; | |
| qcom,skip-power-up; | |
| cpu = <0x19>; | |
| coresight-name = "coresight-ete1"; | |
| phy-cpu = <0x01>; | |
| compatible = "arm,embedded-trace-extension"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1e1>; | |
| phandle = <0x1ea>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@12030000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-cpu2"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x12030000 0x1000>; | |
| phandle = <0x488>; | |
| trig-conns { | |
| arm,trig-out-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| cpu = <0x1a>; | |
| arm,trig-in-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| }; | |
| }; | |
| qcom,csiphy2@ace8000 { | |
| csi-vdd-1p2-supply = <0x31>; | |
| rgltr-max-voltage = <0x00 0x124f80 0xe1d48>; | |
| csi-vdd-0p9-supply = <0x30>; | |
| clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0xe8000>; | |
| cell-index = <0x02>; | |
| interrupts = <0x00 0x1df 0x01>; | |
| clocks = <0x3b 0x1b 0x3b 0x34 0x3b 0x24 0x3b 0x23>; | |
| rgltr-load-current = <0x00 0x4650 0x7dc8>; | |
| gdscr-supply = <0x2d9>; | |
| rgltr-cntrl-support; | |
| clock-cntl-level = "lowsvs", "nominal"; | |
| compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; | |
| rgltr-min-voltage = <0x00 0x124f80 0xd59f8>; | |
| src-clock-name = "csi2phytimer_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "CSIPHY2"; | |
| reg = <0xace8000 0x2000>; | |
| regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; | |
| phandle = <0x574>; | |
| shared-clks = <0x01 0x00 0x00 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; | |
| }; | |
| tpdm@10c28000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-dlct"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10c28000 0x1000>; | |
| phandle = <0x411>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x108>; | |
| phandle = <0x1a6>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tsens2@c273000 { | |
| #qcom,sensors = <0x09>; | |
| interrupts = <0x00 0x1fc 0x04 0x00 0x282 0x04>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,tsens-v2"; | |
| interrupt-names = "uplow", "critical"; | |
| reg = <0xc273000 0x1ff 0xc224000 0x1ff>; | |
| phandle = <0xdc>; | |
| }; | |
| qcom,cam-cpas@ac13000 { | |
| camnoc-bus-width = <0x20>; | |
| rpmh-bcm-info = <0x0c 0x04 0x800 0x00 0x04>; | |
| client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; | |
| vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; | |
| cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; | |
| interconnect-names = "cam_ahb"; | |
| clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_clk_src", "camnoc_axi_clk", "cam_cc_drv_xo_clk"; | |
| clocks-option = <0x3b 0x3f>; | |
| interconnects = <0x61 0x02 0x62 0x205>; | |
| reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; | |
| clock-rates-option = <0x17d78400>; | |
| reg-cam-base = <0x13000 0x19000 0xbbf0000>; | |
| cell-index = <0x00>; | |
| vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; | |
| control-camnoc-axi-clk; | |
| enable-smart-qos; | |
| interrupts = <0x00 0x1cb 0x01>; | |
| rt-wr-priority-min = <0x03>; | |
| clocks = <0x45 0x06 0x45 0x07 0x45 0x08 0x3b 0x96 0x3b 0x0f 0x3b 0x0e 0x3b 0x3a 0x3b 0x3c 0x3b 0x12 0x3b 0x05 0x3b 0x04 0x3b 0x3b>; | |
| sys-cache-uids = <0x22 0x34 0x26 0x33 0x32>; | |
| label = "cpas"; | |
| client-id-based; | |
| rt-wr-priority-max = <0x06>; | |
| cam-ahb-num-cases = <0x08>; | |
| clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; | |
| compatible = "qcom,cam-cpas"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "camnoc_axi_clk_src"; | |
| status = "ok"; | |
| camnoc-axi-clk-bw-margin-perc = <0x14>; | |
| clock-names-option = "cam_icp_clk"; | |
| interrupt-names = "cpas_camnoc"; | |
| reg = <0xac13000 0x1000 0xac19000 0xa080 0xbbf0000 0x1f00>; | |
| regulator-names = "gdsc"; | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00>; | |
| arch-compat = "cpas_top"; | |
| camnoc-axi-min-ib-bw = <0xb2d05e00>; | |
| sys-cache-names = "small-1", "large-1", "large-2", "large-3", "large-4"; | |
| camera-bus-nodes { | |
| level1-nodes { | |
| level-index = <0x01>; | |
| camnoc-max-needed; | |
| level1-nrt2-wr { | |
| parent-node = <0x549>; | |
| cell-index = <0x0d>; | |
| node-name = "level1-nrt2-wr"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x550>; | |
| }; | |
| level1-nrt3-rd { | |
| parent-node = <0x54a>; | |
| cell-index = <0x0f>; | |
| node-name = "level1-nrt3-rd"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x552>; | |
| }; | |
| level1-nrt0-rd { | |
| parent-node = <0x54a>; | |
| cell-index = <0x11>; | |
| node-name = "level1-nrt0-rd"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x554>; | |
| }; | |
| level1-rt3-wr { | |
| parent-node = <0x547>; | |
| rt-wr-niu; | |
| cell-index = <0x0a>; | |
| node-name = "level1-ife-pdaf-lite"; | |
| traffic-merge-type = <0x00>; | |
| niu-size = <0x5c>; | |
| phandle = <0x54d>; | |
| priority-lut-low-offset = <0x7a30>; | |
| }; | |
| level1-nrt1-wr { | |
| parent-node = <0x549>; | |
| cell-index = <0x0e>; | |
| node-name = "level1-nrt0-wr1"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x551>; | |
| }; | |
| level1-rt2-wr { | |
| parent-node = <0x547>; | |
| rt-wr-niu; | |
| cell-index = <0x0b>; | |
| node-name = "level1-ife-stats"; | |
| traffic-merge-type = <0x00>; | |
| niu-size = <0x24>; | |
| phandle = <0x54e>; | |
| priority-lut-low-offset = <0x7830>; | |
| }; | |
| level1-rt0-rd { | |
| parent-node = <0x548>; | |
| cell-index = <0x0c>; | |
| node-name = "level1-sfe-rd"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x54f>; | |
| }; | |
| level1-nrt1-rd { | |
| parent-node = <0x54a>; | |
| cell-index = <0x10>; | |
| node-name = "level1-nrt1-rd"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x553>; | |
| }; | |
| level1-rt4-wr1 { | |
| parent-node = <0x547>; | |
| rt-wr-niu; | |
| cell-index = <0x09>; | |
| node-name = "level1-ife-rdi-wr"; | |
| traffic-merge-type = <0x00>; | |
| niu-size = <0x86>; | |
| phandle = <0x54c>; | |
| priority-lut-low-offset = <0x7c30>; | |
| }; | |
| level1-rt1-wr { | |
| parent-node = <0x547>; | |
| rt-wr-niu; | |
| cell-index = <0x08>; | |
| node-name = "level1-ife-ubwc-linear-wr"; | |
| traffic-merge-type = <0x00>; | |
| niu-size = <0x86>; | |
| phandle = <0x54b>; | |
| priority-lut-low-offset = <0x7630>; | |
| }; | |
| }; | |
| level2-nodes { | |
| level-index = <0x02>; | |
| camnoc-max-needed; | |
| level2-nrt-wr { | |
| parent-node = <0x545>; | |
| cell-index = <0x05>; | |
| node-name = "level2-nrt-wr"; | |
| traffic-merge-type = <0x01>; | |
| phandle = <0x549>; | |
| }; | |
| level2-rt-wr { | |
| parent-node = <0x544>; | |
| cell-index = <0x03>; | |
| node-name = "level2-rt-wr"; | |
| traffic-merge-type = <0x01>; | |
| phandle = <0x547>; | |
| }; | |
| level2-nrt-rd { | |
| parent-node = <0x545>; | |
| cell-index = <0x06>; | |
| node-name = "level2-nrt-rd"; | |
| traffic-merge-type = <0x01>; | |
| phandle = <0x54a>; | |
| }; | |
| level2-icp-rd { | |
| bus-width-factor = <0x04>; | |
| parent-node = <0x546>; | |
| cell-index = <0x07>; | |
| node-name = "level2-icp-rd"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x555>; | |
| }; | |
| level2-rt-rd { | |
| parent-node = <0x544>; | |
| cell-index = <0x04>; | |
| node-name = "level2-rt-rd"; | |
| traffic-merge-type = <0x01>; | |
| phandle = <0x548>; | |
| }; | |
| }; | |
| level3-nodes { | |
| level-index = <0x03>; | |
| level3-nrt1-rd-wr-sum { | |
| cell-index = <0x02>; | |
| node-name = "level3-nrt1-rd-wr-sum"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x546>; | |
| qcom,axi-port-mnoc { | |
| interconnect-names = "cam_sf_icp"; | |
| interconnects = <0xec 0x0c 0x4b 0x200>; | |
| }; | |
| }; | |
| level3-nrt0-rd-wr-sum { | |
| cell-index = <0x01>; | |
| node-name = "level3-nrt0-rd-wr-sum"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x545>; | |
| qcom,axi-port-mnoc { | |
| interconnect-names = "cam_sf_0"; | |
| interconnects = <0xec 0x0d 0x4b 0x200>; | |
| }; | |
| }; | |
| level3-rt-rd-wr-sum { | |
| ib-bw-voting-needed; | |
| cell-index = <0x00>; | |
| node-name = "level3-rt-rd-wr-sum"; | |
| rt-axi-port; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x544>; | |
| qcom,axi-port-mnoc { | |
| interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; | |
| interconnects = <0xec 0x0b 0x4b 0x200 0xec 0x7d1 0x4b 0x9d0 0xec 0xbb9 0x4b 0xdb8 0xec 0xfa1 0x4b 0x11a0>; | |
| }; | |
| }; | |
| }; | |
| level0-nodes { | |
| level-index = <0x00>; | |
| custom1-rd { | |
| parent-node = <0x54f>; | |
| cell-index = <0x27>; | |
| node-name = "custom1-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a2>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "custom1"; | |
| }; | |
| jpeg0-dma0-all-rd { | |
| parent-node = <0x553>; | |
| cell-index = <0x32>; | |
| node-name = "jpeg-dma0-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5ad>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "jpeg-dma0"; | |
| }; | |
| icp0-all-rd { | |
| parent-node = <0x555>; | |
| cell-index = <0x3c>; | |
| node-name = "icp0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5b7>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "icp0"; | |
| }; | |
| cre0-all-rd { | |
| parent-node = <0x552>; | |
| cell-index = <0x2f>; | |
| node-name = "cre0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5aa>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "cre0"; | |
| }; | |
| ife2-pdaf-wr { | |
| parent-node = <0x54d>; | |
| cell-index = <0x1e>; | |
| node-name = "ife2-pdaf-wr"; | |
| traffic-data = <0x08>; | |
| drv-voting-index = <0x03>; | |
| phandle = <0x599>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife2"; | |
| }; | |
| ife3-rdi-stats-pixel-raw-wr { | |
| parent-node = <0x54d>; | |
| cell-index = <0x20>; | |
| node-name = "ife3-rdi-stats-pixel-raw-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; | |
| traffic-data = <0x100>; | |
| phandle = <0x59b>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife3"; | |
| }; | |
| jpeg-enc0-all-wr { | |
| parent-node = <0x551>; | |
| cell-index = <0x2b>; | |
| node-name = "jpeg-enc0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a6>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "jpeg-enc0"; | |
| }; | |
| ife0-stats-wr { | |
| parent-node = <0x54e>; | |
| cell-index = <0x21>; | |
| node-name = "ife0-stats-wr"; | |
| traffic-data = <0x03>; | |
| drv-voting-index = <0x01>; | |
| phandle = <0x59c>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife0"; | |
| }; | |
| ife1-ubwc-linear-wr { | |
| parent-node = <0x54b>; | |
| cell-index = <0x13>; | |
| node-name = "ife1-ubwc-linear-wr"; | |
| constituent-paths = <0x01 0x02 0x00>; | |
| traffic-data = <0x108>; | |
| drv-voting-index = <0x02>; | |
| phandle = <0x58e>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife1"; | |
| }; | |
| jpeg-enc1-all-wr { | |
| parent-node = <0x551>; | |
| cell-index = <0x2d>; | |
| node-name = "jpeg-enc1-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a8>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "jpeg-enc1"; | |
| }; | |
| rt-cdm0-all-rd { | |
| parent-node = <0x554>; | |
| cell-index = <0x37>; | |
| node-name = "rt-cdm0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5b2>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "rt-cdm0"; | |
| }; | |
| rt-cdm1-all-rd { | |
| parent-node = <0x554>; | |
| cell-index = <0x38>; | |
| node-name = "rt-cdm1-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5b3>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "rt-cdm1"; | |
| }; | |
| bps0-all-wr { | |
| parent-node = <0x550>; | |
| cell-index = <0x29>; | |
| node-name = "bps0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a4>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "bps0"; | |
| }; | |
| rt-cdm2-all-rd { | |
| parent-node = <0x554>; | |
| cell-index = <0x39>; | |
| node-name = "rt-cdm2-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5b4>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "rt-cdm2"; | |
| }; | |
| ife2-rdi-pixel-raw-wr { | |
| parent-node = <0x54c>; | |
| cell-index = <0x17>; | |
| node-name = "ife2-rdi-pixel-raw-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x09>; | |
| traffic-data = <0x104>; | |
| drv-voting-index = <0x03>; | |
| phandle = <0x592>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife2"; | |
| }; | |
| jpeg1-enc1-all-rd { | |
| parent-node = <0x553>; | |
| cell-index = <0x33>; | |
| node-name = "jpeg-enc1-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5ae>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "jpeg-enc1"; | |
| }; | |
| sfe0-all-wr { | |
| parent-node = <0x54c>; | |
| cell-index = <0x18>; | |
| node-name = "sfe0-all-wr"; | |
| constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; | |
| traffic-data = <0x100>; | |
| drv-voting-index = <0x20>; | |
| phandle = <0x593>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "sfe0"; | |
| }; | |
| ife0-rdi-pixel-raw-wr { | |
| parent-node = <0x54c>; | |
| cell-index = <0x15>; | |
| node-name = "ife0-rdi-pixel-raw-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x09>; | |
| traffic-data = <0x104>; | |
| drv-voting-index = <0x01>; | |
| phandle = <0x590>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife0"; | |
| }; | |
| rt-cdm3-all-rd { | |
| parent-node = <0x554>; | |
| cell-index = <0x3a>; | |
| node-name = "rt-cdm3-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5b5>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "rt-cdm3"; | |
| }; | |
| ife0-ubwc-linear-wr { | |
| parent-node = <0x54b>; | |
| cell-index = <0x12>; | |
| node-name = "ife0-ubwc-linear-wr"; | |
| constituent-paths = <0x01 0x02 0x00>; | |
| traffic-data = <0x108>; | |
| drv-voting-index = <0x01>; | |
| phandle = <0x58d>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife0"; | |
| }; | |
| custom0-rd { | |
| parent-node = <0x54f>; | |
| cell-index = <0x26>; | |
| node-name = "custom0-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a1>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "custom0"; | |
| }; | |
| jpeg-dma0-all-wr { | |
| parent-node = <0x551>; | |
| cell-index = <0x2c>; | |
| node-name = "jpeg-dma0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a7>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "jpeg-dma0"; | |
| }; | |
| sfe1-all-wr { | |
| parent-node = <0x54c>; | |
| cell-index = <0x19>; | |
| node-name = "sfe1-all-wr"; | |
| constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; | |
| traffic-data = <0x100>; | |
| drv-voting-index = <0x20>; | |
| phandle = <0x594>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "sfe1"; | |
| }; | |
| ife1-stats-wr { | |
| parent-node = <0x54e>; | |
| cell-index = <0x22>; | |
| node-name = "ife1-stats-wr"; | |
| traffic-data = <0x03>; | |
| drv-voting-index = <0x02>; | |
| phandle = <0x59d>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife1"; | |
| }; | |
| rt-cdm4-all-rd { | |
| parent-node = <0x554>; | |
| cell-index = <0x3b>; | |
| node-name = "rt-cdm4-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5b6>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "rt-cdm4"; | |
| }; | |
| jpeg-dma1-all-wr { | |
| parent-node = <0x551>; | |
| cell-index = <0x2e>; | |
| node-name = "jpeg-dma1-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a9>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "jpeg-dma1"; | |
| }; | |
| ife4-rdi-stats-pixel-raw-wr { | |
| parent-node = <0x54d>; | |
| cell-index = <0x1f>; | |
| node-name = "ife4-rdi-stats-pixel-raw-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; | |
| traffic-data = <0x100>; | |
| phandle = <0x59a>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife4"; | |
| }; | |
| ife1-pdaf-wr { | |
| parent-node = <0x54d>; | |
| cell-index = <0x1d>; | |
| node-name = "ife1-pdaf-wr"; | |
| traffic-data = <0x08>; | |
| drv-voting-index = <0x02>; | |
| phandle = <0x598>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife1"; | |
| }; | |
| jpeg1-dma1-all-rd { | |
| parent-node = <0x553>; | |
| cell-index = <0x34>; | |
| node-name = "jpeg-dma1-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5af>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "jpeg-dma1"; | |
| }; | |
| ife2-stats-wr { | |
| parent-node = <0x54e>; | |
| cell-index = <0x23>; | |
| node-name = "ife2-stats-wr"; | |
| traffic-data = <0x03>; | |
| drv-voting-index = <0x03>; | |
| phandle = <0x59e>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife2"; | |
| }; | |
| ipe0-all-wr { | |
| parent-node = <0x549>; | |
| cell-index = <0x28>; | |
| node-name = "ipe0-all-wr"; | |
| constituent-paths = <0x22 0x23 0x24>; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a3>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ipe0"; | |
| }; | |
| custom1-wr { | |
| parent-node = <0x54c>; | |
| cell-index = <0x1b>; | |
| node-name = "custom1-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x596>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "custom1"; | |
| }; | |
| ipe0-in-rd { | |
| parent-node = <0x54a>; | |
| cell-index = <0x36>; | |
| node-name = "ipe0-in-rd"; | |
| traffic-data = <0x20>; | |
| phandle = <0x5b1>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "ipe0"; | |
| }; | |
| cre0-all-wr { | |
| parent-node = <0x550>; | |
| cell-index = <0x2a>; | |
| node-name = "cre0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5a5>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "cre0"; | |
| }; | |
| bps0-all-rd { | |
| parent-node = <0x552>; | |
| cell-index = <0x30>; | |
| node-name = "bps0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5ab>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "bps0"; | |
| }; | |
| sfe0-all-rd { | |
| parent-node = <0x54f>; | |
| cell-index = <0x24>; | |
| node-name = "sfe0-all-rd"; | |
| constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; | |
| traffic-data = <0x100>; | |
| drv-voting-index = <0x20>; | |
| phandle = <0x59f>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "sfe0"; | |
| }; | |
| ipe0-ref-rd { | |
| parent-node = <0x54a>; | |
| cell-index = <0x35>; | |
| node-name = "ipe0-ref-rd"; | |
| traffic-data = <0x21>; | |
| phandle = <0x5b0>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "ipe0"; | |
| }; | |
| jpeg0-enc0-all-rd { | |
| parent-node = <0x553>; | |
| cell-index = <0x31>; | |
| node-name = "jpeg-enc0-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x5ac>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "jpeg-enc0"; | |
| }; | |
| sfe1-all-rd { | |
| parent-node = <0x54f>; | |
| cell-index = <0x25>; | |
| node-name = "sfe1-all-rd"; | |
| constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; | |
| traffic-data = <0x100>; | |
| drv-voting-index = <0x20>; | |
| phandle = <0x5a0>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "sfe1"; | |
| }; | |
| ife1-rdi-pixel-raw-wr { | |
| parent-node = <0x54c>; | |
| cell-index = <0x16>; | |
| node-name = "ife1-rdi-pixel-raw-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x09>; | |
| traffic-data = <0x104>; | |
| drv-voting-index = <0x02>; | |
| phandle = <0x591>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife1"; | |
| }; | |
| ife0-pdaf-wr { | |
| parent-node = <0x54d>; | |
| cell-index = <0x1c>; | |
| node-name = "ife0-pdaf-wr"; | |
| traffic-data = <0x08>; | |
| drv-voting-index = <0x01>; | |
| phandle = <0x597>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife0"; | |
| }; | |
| custom0-wr { | |
| parent-node = <0x54c>; | |
| cell-index = <0x1a>; | |
| node-name = "custom0-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x595>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "custom0"; | |
| }; | |
| ife2-ubwc-linear-wr { | |
| parent-node = <0x54b>; | |
| cell-index = <0x14>; | |
| node-name = "ife2-ubwc-linear-wr"; | |
| constituent-paths = <0x01 0x02 0x00>; | |
| traffic-data = <0x108>; | |
| drv-voting-index = <0x03>; | |
| phandle = <0x58f>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife2"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,tpg13@acf6000 { | |
| clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; | |
| reg-names = "tpg0", "cam_cpas_top"; | |
| reg-cam-base = <0xf6000 0x13000>; | |
| cell-index = <0x0d>; | |
| interrupts = <0x00 0x19d 0x01>; | |
| clocks = <0x3b 0x1b 0x3b 0x31>; | |
| clock-cntl-level = "lowsvs", "nominal"; | |
| compatible = "qcom,cam-tpg1031"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "cphy_rx_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "tpg0"; | |
| reg = <0xacf6000 0x400 0xac13000 0x1000>; | |
| regulator-names = "gdsc"; | |
| phandle = <0x5c4>; | |
| phy-id = <0x00>; | |
| shared-clks = <0x01 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; | |
| }; | |
| tlmm-vm-mem-access { | |
| qcom,master; | |
| tlmm-vm-gpio-list = <0x33 0x56 0x00 0x33 0x57 0x00 0x33 0x85 0x00 0x33 0x89 0x00 0x33 0x2c 0x00 0x33 0x2d 0x00 0x33 0x2e 0x00 0x33 0x2f 0x00 0x33 0x18 0x00 0x33 0x19 0x00 0x33 0x5b 0x00 0x33 0x38 0x00 0x33 0x39 0x00 0x33 0x3a 0x00 0x33 0x3b 0x00 0x33 0x0d 0x00 0x33 0x30 0x00>; | |
| compatible = "qcom,tlmm-vm-mem-access"; | |
| }; | |
| qcom,gh-qtimer@17425000 { | |
| qcom,primary; | |
| reg-names = "qtmr-base"; | |
| interrupts = <0x00 0x0a 0x04>; | |
| compatible = "qcom,gh-qtmr"; | |
| interrupt-names = "qcom,qtmr-intr"; | |
| reg = <0x17425000 0x1000>; | |
| }; | |
| iommu_test_device { | |
| compatible = "qcom,iommu-debug-test"; | |
| usecase0_apps { | |
| iommus = <0x4c 0x400 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| }; | |
| usecase5_kgsl { | |
| iommus = <0xee 0x07 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| }; | |
| usecase4_apps_secure { | |
| iommus = <0x4c 0x400 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| usecase2_apps_atomic { | |
| iommus = <0x4c 0x400 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| usecase3_apps_dma { | |
| iommus = <0x4c 0x400 0x00>; | |
| dma-coherent; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| }; | |
| usecase1_apps_fastmap { | |
| iommus = <0x4c 0x400 0x00>; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| usecase6_kgsl_dma { | |
| iommus = <0xee 0x07 0x00>; | |
| dma-coherent; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| }; | |
| }; | |
| qcom,msm-adsp-loader { | |
| qcom,adsp-state = <0x00>; | |
| compatible = "qcom,adsp-loader"; | |
| status = "ok"; | |
| phandle = <0x51b>; | |
| qcom,rproc-handle = <0x23>; | |
| }; | |
| funnel@1080c000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-modem_q6"; | |
| compatible = "arm,primecell"; | |
| reg = <0x1080c000 0x1000>; | |
| phandle = <0x44a>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x18c>; | |
| phandle = <0x18b>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x18d>; | |
| phandle = <0x11f>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x18e>; | |
| phandle = <0x191>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@10b08000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x40 0x01 0x40 0x02 0x40 0x03 0x40>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpda-aoss"; | |
| qcom,dsb-elem-size = <0x04 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x47>; | |
| reg = <0x10b08000 0x1000>; | |
| phandle = <0x454>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1c6>; | |
| phandle = <0xf2>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x1c9>; | |
| phandle = <0xf5>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x1c7>; | |
| phandle = <0xf3>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x1ca>; | |
| phandle = <0x10a>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x1c8>; | |
| phandle = <0xf4>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1cb>; | |
| phandle = <0x1cf>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| display_gpio_regulator@1 { | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| pinctrl-names = "default"; | |
| regulator-boot-on; | |
| gpio = <0x33 0x90 0x00>; | |
| pinctrl-0 = <0x76a>; | |
| regulator-enable-ramp-delay = <0xe9>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-name = "TS_AVDD_3V0"; | |
| compatible = "qti-regulator-fixed"; | |
| qcom,proxy-consumer-enable; | |
| phandle = <0x769>; | |
| proxy-supply = <0x769>; | |
| }; | |
| rx_core_clk { | |
| qcom,codec-ext-clk-src = <0x05>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x660>; | |
| qcom,codec-lpass-clk-id = <0x30e>; | |
| qcom,codec-lpass-ext-clk-freq = <0x1588800>; | |
| }; | |
| cti@12070000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-cpu6"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x12070000 0x1000>; | |
| phandle = <0x48c>; | |
| trig-conns { | |
| arm,trig-out-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| cpu = <0x1e>; | |
| arm,trig-in-sigs = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| }; | |
| }; | |
| clock-controller@af00000 { | |
| #reset-cells = <0x01>; | |
| vdd_mxa-supply = <0x2a>; | |
| clock-names = "bi_tcxo", "sleep_clk", "iface"; | |
| clocks = <0x46 0x00 0x54 0x45 0x0f>; | |
| vdd_mm-supply = <0x28>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,kalama-dispcc", "syscon"; | |
| reg-name = "cc_base"; | |
| reg = <0xaf00000 0x20000>; | |
| phandle = <0x3c>; | |
| }; | |
| ipcc-self-ping-apss { | |
| interrupts-extended = <0x4f 0x08 0x02 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x3f8>; | |
| mboxes = <0x4f 0x08 0x02>; | |
| }; | |
| qcom,power-state { | |
| qcom,subsys-name = "lpass", "cdsp", "mpss"; | |
| compatible = "qcom,power-state"; | |
| qcom,rproc-handle = <0x23 0x24 0x25>; | |
| }; | |
| qcom,kgsl-3d0@3d00000 { | |
| qcom,ubwc-mode = <0x04>; | |
| interconnect-names = "gpu_icc_path"; | |
| qcom,bus-table-cnoc = <0x00 0x64>; | |
| clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "apb_pclk"; | |
| interconnects = <0x61 0x10 0x4b 0x200>; | |
| reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "isense_cntl", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; | |
| qcom,initial-pwrlevel = <0x07>; | |
| interrupts = <0x00 0x12c 0x04>; | |
| clocks = <0x45 0x20 0x45 0x21 0x5d 0x00 0x4e 0x00>; | |
| qcom,bus-table-ddr = <0x00 0x209a8e 0x2dc6c0 0x5caf6a 0x65ce03 0x7cb163 0xa3140c 0xbdf5c2 0xdbb3e5 0xfbc520>; | |
| compatible = "qcom,adreno-gpu-gen7-2-1", "qcom,kgsl-3d0"; | |
| qcom,initial-min-pwrlevel = <0x07>; | |
| status = "ok"; | |
| qcom,gpu-qdss-stm = <0x161c0000 0x40000>; | |
| interrupt-names = "kgsl_3d0_irq"; | |
| reg = <0x3d00000 0x40000 0x3d61000 0x800 0x3d50000 0x10000 0x3d8b000 0x2000 0x3d9e000 0x1000 0x10900000 0x80000 0x10048000 0x8000 0x10b05000 0x1000>; | |
| phandle = <0xde>; | |
| qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7"; | |
| qcom,no-nap; | |
| qcom,min-access-length = <0x20>; | |
| #cooling-cells = <0x02>; | |
| qcom,gpu-mempools { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,gpu-mempools"; | |
| qcom,gpu-mempool@2 { | |
| reg = <0x02>; | |
| qcom,mempool-reserved = <0x100>; | |
| qcom,mempool-page-size = <0x10000>; | |
| }; | |
| qcom,gpu-mempool@0 { | |
| reg = <0x00>; | |
| qcom,mempool-reserved = <0x800>; | |
| qcom,mempool-page-size = <0x1000>; | |
| }; | |
| qcom,gpu-mempool@5 { | |
| reg = <0x05>; | |
| qcom,mempool-reserved = <0x20>; | |
| qcom,mempool-page-size = <0x100000>; | |
| }; | |
| qcom,gpu-mempool@3 { | |
| reg = <0x03>; | |
| qcom,mempool-reserved = <0x80>; | |
| qcom,mempool-page-size = <0x20000>; | |
| }; | |
| qcom,gpu-mempool@1 { | |
| reg = <0x01>; | |
| qcom,mempool-reserved = <0x400>; | |
| qcom,mempool-page-size = <0x2000>; | |
| }; | |
| qcom,gpu-mempool@4 { | |
| reg = <0x04>; | |
| qcom,mempool-reserved = <0x50>; | |
| qcom,mempool-page-size = <0x40000>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,gpu-pwrlevels"; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x90>; | |
| qcom,bus-min = <0x03>; | |
| qcom,bus-freq = <0x06>; | |
| qcom,bus-max = <0x09>; | |
| qcom,acd-level = <0xa82f5ffd>; | |
| qcom,gpu-freq = <0x24a827c0>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@8 { | |
| qcom,level = <0x34>; | |
| qcom,bus-min = <0x01>; | |
| qcom,bus-freq = <0x01>; | |
| qcom,bus-max = <0x01>; | |
| qcom,gpu-freq = "\apL"; | |
| reg = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,level = <0x38>; | |
| qcom,bus-min = <0x01>; | |
| qcom,bus-freq = <0x03>; | |
| qcom,bus-max = <0x03>; | |
| qcom,acd-level = <0xe02d5ffd>; | |
| qcom,gpu-freq = <0x119557c0>; | |
| reg = <0x06>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0x40>; | |
| qcom,bus-min = <0x01>; | |
| qcom,bus-freq = <0x03>; | |
| qcom,bus-max = <0x04>; | |
| qcom,acd-level = <0xc02a5ffd>; | |
| qcom,gpu-freq = <0x17e6c640>; | |
| reg = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x80>; | |
| qcom,bus-min = <0x02>; | |
| qcom,bus-freq = <0x03>; | |
| qcom,bus-max = <0x07>; | |
| qcom,acd-level = <0xe0285ffd>; | |
| qcom,gpu-freq = <0x20c85580>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0xc0>; | |
| qcom,bus-min = <0x09>; | |
| qcom,bus-freq = <0x09>; | |
| qcom,bus-max = <0x09>; | |
| qcom,acd-level = <0x882e5ffd>; | |
| qcom,gpu-freq = <0x2887fa00>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| qcom,level = <0x34>; | |
| qcom,bus-min = <0x01>; | |
| qcom,bus-freq = <0x01>; | |
| qcom,bus-max = <0x03>; | |
| qcom,acd-level = <0xc02f5ffd>; | |
| qcom,gpu-freq = <0xd1cef00>; | |
| reg = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,level = <0x3c>; | |
| qcom,bus-min = <0x01>; | |
| qcom,bus-freq = <0x03>; | |
| qcom,bus-max = <0x03>; | |
| qcom,acd-level = <0xe02b5ffd>; | |
| qcom,gpu-freq = <0x14be0f00>; | |
| reg = <0x05>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x50>; | |
| qcom,bus-min = <0x01>; | |
| qcom,bus-freq = <0x03>; | |
| qcom,bus-max = <0x05>; | |
| qcom,acd-level = <0xe0285ffd>; | |
| qcom,gpu-freq = <0x1c4fecc0>; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| zap-shader { | |
| memory-region = <0x2ef>; | |
| }; | |
| }; | |
| qcom,pcie@1c08000 { | |
| pinctrl-names = "default", "sleep"; | |
| qcom,no-client-based-bw-voting; | |
| qcom,vreg-0p9-voltage-level = <0xdea80 0xd6d80 0x2f1e8>; | |
| #address-cells = <0x03>; | |
| gdsc-core-vdd-supply = <0x2c7>; | |
| qcom,vreg-qref-voltage-level = <0xd6d80 0xd6d80 0x6464>; | |
| dma-coherent; | |
| clock-suppressible = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| interconnect-names = "icc_path"; | |
| qcom,drv-l1ss-timeout-us = <0x1388>; | |
| pinctrl-0 = <0x2c4 0x2c5>; | |
| clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", "pcie_aux_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_clkref_en", "pcie_slv_q2a_axi_clk", "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk"; | |
| interconnects = <0xed 0x2e 0x4b 0x200>; | |
| reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; | |
| qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>; | |
| qcom,phy-power-down-offset = <0x1240>; | |
| qcom,pcie-phy-ver = <0x64>; | |
| cell-index = <0x01>; | |
| qcom,apss-based-l1ss-sleep; | |
| resets = <0x45 0x08 0x45 0x0b 0x45 0x09 0x45 0x0a>; | |
| qcom,dbi-debug-reg = <0x104 0x110 0x80 0x1f4 0x730 0x734 0x738 0x73c>; | |
| qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x40 0x40 0x5f5e100 0x100 0x100 0x5f5e100>; | |
| interrupts = <0x00 0x132 0x04 0x00 0x1b2 0x04 0x00 0x1b3 0x04 0x00 0x1b6 0x04 0x00 0x1b7 0x04>; | |
| qcom,eq-fmdc-t-min-phase23 = <0x01>; | |
| clocks = <0x45 0x34 0x46 0x00 0x45 0x2c 0x45 0x2e 0x45 0x2f 0x45 0x36 0x5e 0x01 0x45 0x37 0x45 0x32 0x45 0x0e 0x45 0x00 0x45 0x0c 0x45 0x35 0x57 0x45 0x30>; | |
| qcom,smmu-sid-base = <0x1480>; | |
| vreg-1p2-supply = <0x31>; | |
| #size-cells = <0x02>; | |
| qcom,boot-option = <0x00>; | |
| clock-frequency = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| gdsc-phy-vdd-supply = <0x2c8>; | |
| vreg-mx-supply = <0x2a>; | |
| qcom,l1-2-th-scale = <0x02>; | |
| qcom,phy-status-offset = <0x1214>; | |
| qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc 0x11e0 0x11e4 0x11f8 0xb8 0x8b8 0xc4 0x8c4 0x464 0xc64 0x1800 0x1c00 0x1804 0x1c04 0x1808 0x1c08 0x180c 0x1c0c 0x1810 0x1c10 0x1814 0x1c14 0x1818 0x1c18 0x1a20 0x1e20 0x1214 0x1218 0x121c 0x1220 0x1224 0x1228 0x122c 0x1230 0x1234 0x1238 0x123c 0x1400 0x1404>; | |
| vreg-0p9-supply = <0x2c9>; | |
| qcom,drv-name = "lpass"; | |
| pcie-i2c-phandle = <0x2ca>; | |
| vreg-qref-supply = <0x30>; | |
| compatible = "qcom,pci-msm"; | |
| ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>; | |
| msi-map = <0x00 0x2fe 0x1480 0x01 0x100 0x2fe 0x1481 0x01>; | |
| pinctrl-1 = <0x2c4 0x2c6>; | |
| status = "disabled"; | |
| interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; | |
| qcom,num-parf-testbus-sel = <0xb9>; | |
| reg = <0x1c08000 0x3000 0x1c0e000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40001000 0x1000 0x40100000 0x100000>; | |
| linux,pci-domain = <0x01>; | |
| phandle = <0x4c9>; | |
| qcom,aux-clk-freq = <0x11>; | |
| iommu-map = <0x00 0x4c 0x1480 0x01 0x100 0x4c 0x1481 0x01 0x208 0x4c 0x1482 0x01 0x210 0x4c 0x1483 0x01 0x218 0x4c 0x1484 0x01 0x300 0x4c 0x1487 0x01 0x400 0x4c 0x1488 0x01 0x500 0x4c 0x148c 0x01 0x501 0x4c 0x148e 0x01>; | |
| qcom,no-l0s-supported; | |
| reset-names = "pcie_1_core_reset", "pcie_1_phy_reset", "pcie_1_link_down_reset", "pcie_1_phy_nocsr_com_phy_reset"; | |
| qcom,l1-2-th-value = <0x96>; | |
| qcom,ep-latency = <0x0a>; | |
| vreg-cx-supply = <0x27>; | |
| qcom,vreg-1p2-voltage-level = <0x124f80 0x124f80 0x65f4>; | |
| qcom,vreg-cx-voltage-level = <0xffff 0x100 0x00>; | |
| qcom,phy-status-bit = <0x07>; | |
| qcom,slv-addr-space-size = <0x20000000>; | |
| qcom,vreg-mx-voltage-level = <0xffff 0x100 0x00>; | |
| qcom,phy-sequence = <0x1240 0x03 0x00 0x30 0x1d 0x00 0x34 0x03 0x00 0x78 0x01 0x00 0x7c 0x00 0x00 0x80 0x51 0x00 0xac 0x34 0x00 0x208 0x0c 0x00 0x20c 0x0a 0x00 0x218 0x04 0x00 0x220 0x16 0x00 0x234 0x00 0x00 0x29c 0x80 0x00 0x2a0 0x7c 0x00 0x2b4 0x05 0x00 0x2e8 0x0a 0x00 0x30c 0x0d 0x00 0x320 0x0b 0x00 0x348 0x1c 0x00 0x388 0x20 0x00 0x394 0x30 0x00 0x3dc 0x09 0x00 0x3f4 0x14 0x00 0x3f8 0xb3 0x00 0x3fc 0x58 0x00 0x400 0x9a 0x00 0x404 0x26 0x00 0x408 0xb6 0x00 0x40c 0xee 0x00 0x410 0xdb 0x00 0x414 0xdb 0x00 0x418 0xa0 0x00 0x41c 0xdf 0x00 0x420 0x78 0x00 0x424 0x76 0x00 0x428 0xff 0x00 0x830 0x1d 0x00 0x834 0x03 0x00 0x878 0x01 0x00 0x87c 0x00 0x00 0x880 0x51 0x00 0x8ac 0x34 0x00 0xa08 0x0c 0x00 0xa0c 0x0a 0x00 0xa18 0x04 0x00 0xa20 0x16 0x00 0xa34 0x00 0x00 0xa9c 0x80 0x00 0xaa0 0x7c 0x00 0xab4 0x05 0x00 0xae8 0x0a 0x00 0xb0c 0x0d 0x00 0xb20 0x0b 0x00 0xb48 0x1c 0x00 0xb88 0x20 0x00 0xb94 0x30 0x00 0xbdc 0x09 0x00 0xbf4 0x14 0x00 0xbf8 0xb3 0x00 0xbfc 0x58 0x00 0xc00 0x9a 0x00 0xc04 0x26 0x00 0xc08 0xb6 0x00 0xc0c 0xee 0x00 0xc10 0xdb 0x00 0xc14 0xdb 0x00 0xc18 0xa0 0x00 0xc1c 0xdf 0x00 0xc20 0x78 0x00 0xc24 0x76 0x00 0xc28 0xff 0x00 0xea0 0x01 0x00 0xeb4 0x00 0x00 0xec4 0x00 0x00 0xec8 0x1f 0x00 0xed4 0x12 0x00 0xed8 0x12 0x00 0xedc 0xdb 0x00 0xee0 0x9a 0x00 0xee4 0x38 0x00 0xee8 0xb6 0x00 0xeec 0x64 0x00 0xef0 0x1f 0x00 0xef4 0x1f 0x00 0xef8 0x1f 0x00 0xefc 0x1f 0x00 0xf00 0x1f 0x00 0xf04 0x1f 0x00 0xf0c 0x1f 0x00 0xf14 0x1f 0x00 0xf1c 0x1f 0x00 0xf28 0x5b 0x00 0x1000 0x26 0x00 0x1004 0x03 0x00 0x1010 0x06 0x00 0x1014 0x16 0x00 0x1018 0x36 0x00 0x101c 0x04 0x00 0x1020 0x0a 0x00 0x1024 0x1a 0x00 0x1028 0x68 0x00 0x1030 0xab 0x00 0x1034 0xaa 0x00 0x1038 0x02 0x00 0x103c 0x12 0x00 0x1060 0xf8 0x00 0x1064 0x01 0x00 0x1070 0x06 0x00 0x1074 0x16 0x00 0x1078 0x36 0x00 0x107c 0x0a 0x00 0x1080 0x04 0x00 0x1084 0x0d 0x00 0x1088 0x41 0x00 0x1090 0xab 0x00 0x1094 0xaa 0x00 0x1098 0x01 0x00 0x109c 0x00 0x00 0x10bc 0x0a 0x00 0x10c0 0x01 0x00 0x10cc 0x62 0x00 0x10d0 0x02 0x00 0x10d8 0x40 0x00 0x10dc 0x14 0x00 0x10e0 0x90 0x00 0x10e4 0x82 0x00 0x10f4 0x0f 0x00 0x1110 0x08 0x00 0x1120 0x46 0x00 0x1124 0x04 0x00 0x1140 0x14 0x00 0x1164 0x34 0x00 0x1170 0xa0 0x00 0x1174 0x06 0x00 0x1184 0x88 0x00 0x1188 0x14 0x00 0x1198 0x0f 0x00 0x1378 0x2e 0x00 0x1390 0xcc 0x00 0x13f8 0x00 0x00 0x13fc 0x22 0x00 0x141c 0xc1 0x00 0x1490 0x00 0x00 0x14a0 0x16 0x00 0x1508 0x02 0x00 0x155c 0x2e 0x00 0x157c 0x03 0x00 0x1584 0x28 0x00 0x13dc 0x04 0x00 0x13e0 0x02 0x00 0x1418 0xc0 0x00 0x140c 0x1d 0x00 0x158c 0x0f 0x00 0x15ac 0xf2 0x00 0x15c0 0xf2 0x00 0x1200 0x00 0x00 0x1244 0x03 0x00>; | |
| pcie1_rp { | |
| #address-cells = <0x05>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4ca>; | |
| cnss_pci1 { | |
| #address-cells = <0x01>; | |
| memory-region = <0x5e1>; | |
| #size-cells = <0x01>; | |
| qcom,iommu-group = <0x5e2>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x5e5>; | |
| cnss_pci_iommu_group1 { | |
| qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; | |
| phandle = <0x5e2>; | |
| qcom,iommu-msi-size = <0x1000>; | |
| qcom,iommu-pagetable = "coherent"; | |
| qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| }; | |
| qcom,mhi@0 { | |
| #address-cells = <0x01>; | |
| mhi,timeout = <0x7d0>; | |
| interconnect-names = "pcie_to_ddr"; | |
| mhi,name = "sxr"; | |
| interconnects = <0xed 0x2e 0x4b 0x200>; | |
| pci-ids = "17cb:0111"; | |
| #size-cells = <0x01>; | |
| qcom,mhi-bus-bw-cfg = <0x00 0x00 0x3d090 0x00 0x7a120 0x00 0xf4240 0x00 0x1e8480 0x00>; | |
| status = "disabled"; | |
| qcom,iommu-group = <0x2cb>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4cb>; | |
| mhi,max-channels = <0x02>; | |
| mhi_0_iommu_group { | |
| qcom,iommu-dma-addr-pool = <0x20000000 0x1fffffff>; | |
| phandle = <0x2cb>; | |
| qcom,iommu-pagetable = "coherent"; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| }; | |
| pcie1_bus1_dev0_fn0 { | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4cc>; | |
| pcie1_bus2_dev1_fn0 { | |
| reg = <0x800 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4cd>; | |
| }; | |
| pcie1_bus2_dev2_fn0 { | |
| reg = <0x1000 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4ce>; | |
| }; | |
| pcie1_bus2_dev3_fn0 { | |
| reg = <0x1800 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4cf>; | |
| pcie1_ntn3_eth0 { | |
| qcom,iommu-group = <0x2cd>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4d0>; | |
| eth0_pci_iommu_group { | |
| phandle = <0x2cd>; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| }; | |
| pcie0_ntn3_eth1 { | |
| qcom,iommu-group = <0x2ce>; | |
| reg = <0x100 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4d1>; | |
| eth1_pci_iommu_group { | |
| phandle = <0x2ce>; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| }; | |
| qps615_eth1,qps615_eth1@pcie1_rp { | |
| phy-supply = <0x2cc>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,phy-rst-delay-us = <0x3d090>; | |
| qcom,phy-rst-gpio = <0x00>; | |
| interrupts-extended = <0x33 0x2b 0x02>; | |
| compatible = "qcom,ioss-v2-device"; | |
| interrupt-names = "wol_irq"; | |
| reg = <0x100 0x00 0x00 0x00 0x00>; | |
| }; | |
| qps615_eth0,qps615_eth0@pcie1_rp { | |
| phy-supply = <0x2cc>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,phy-rst-delay-us = <0x3d090>; | |
| qcom,phy-rst-gpio = <0x01>; | |
| interrupts-extended = <0x33 0x2b 0x02>; | |
| compatible = "qcom,ioss-v2-device"; | |
| interrupt-names = "wol_irq"; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10c22000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-ipa"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10c22000 0x1000>; | |
| phandle = <0x410>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x107>; | |
| phandle = <0x1a4>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gh-secure-vm-loader@2 { | |
| ext-region = <0x91>; | |
| memory-region = <0x85>; | |
| qcom,pas-id = <0x23>; | |
| compatible = "qcom,gh-secure-vm-loader"; | |
| qcom,vmid = <0x32>; | |
| ext-label = <0x07>; | |
| qcom,firmware-name = "cpusys_vm"; | |
| }; | |
| audio_etm0 { | |
| atid = <0x28 0x29>; | |
| qcom,inst-id = <0x05>; | |
| coresight-name = "coresight-audio-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xef>; | |
| phandle = <0x134>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| clock-controller@3d90000 { | |
| #reset-cells = <0x01>; | |
| clock-names = "bi_tcxo", "gpll0_out_main", "gpll0_out_main_div"; | |
| vdd_mxc-supply = <0x2b>; | |
| clocks = <0x46 0x00 0x45 0x1e 0x45 0x1f>; | |
| #clock-cells = <0x01>; | |
| vdd_mx-supply = <0x2a>; | |
| compatible = "qcom,kalama-gpucc", "syscon"; | |
| reg-name = "cc_base"; | |
| reg = <0x3d90000 0xa000>; | |
| phandle = <0x5d>; | |
| vdd_cx-supply = <0x27>; | |
| }; | |
| tpdm@10d00000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-ddr"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10d00000 0x1000>; | |
| phandle = <0x157>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf9>; | |
| phandle = <0x150>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@adf4058 { | |
| interconnect-names = "mmnoc"; | |
| clock-names = "ahb_clk"; | |
| interconnects = <0xec 0x0b 0xec 0x232>; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x06>; | |
| regulator-name = "cam_cc_titan_top_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| qcom,proxy-consumer-enable; | |
| reg = <0xadf4058 0x04>; | |
| phandle = <0x2d9>; | |
| proxy-supply = <0x2d9>; | |
| }; | |
| timer { | |
| always-on; | |
| interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0c 0xff08>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv8-timer"; | |
| phandle = <0x345>; | |
| }; | |
| qcom,smp2p-cdsp { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x06 0x02 0x01>; | |
| interrupt-parent = <0x4f>; | |
| qcom,remote-pid = <0x05>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x4f 0x06 0x02>; | |
| qcom,smem = <0x5e 0x1b0>; | |
| qcom,smp2p-rdbg5-out { | |
| qcom,entry-name = "rdbg"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x2d4>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x7b>; | |
| interrupt-controller; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x7c>; | |
| }; | |
| qcom,smp2p-rdbg5-in { | |
| qcom,entry-name = "rdbg"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x2d5>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| cti@10b41000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-lpass_lpi_cti1"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10b41000 0x1000>; | |
| phandle = <0x470>; | |
| }; | |
| qcom,userspace-cdev { | |
| compatible = "qcom,userspace-cooling-devices"; | |
| display-fps { | |
| phandle = <0x4f7>; | |
| qcom,max-level = <0x10>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| tpdm@10d43000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x63>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-llcc-3"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10d43000 0x1000>; | |
| phandle = <0x42f>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x129>; | |
| phandle = <0x12d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| wsa2_core_tx_clk { | |
| qcom,codec-ext-clk-src = <0x0f>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| status = "disabled"; | |
| phandle = <0x738>; | |
| qcom,codec-lpass-clk-id = <0x316>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| dsi_panel_pwr_supply { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x751>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x48ff8>; | |
| qcom,supply-post-on-sleep = <0x00>; | |
| qcom,supply-name = "vdd"; | |
| qcom,supply-max-voltage = <0x2ab980>; | |
| reg = <0x01>; | |
| qcom,supply-min-voltage = <0x2ab980>; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x2710>; | |
| qcom,supply-post-on-sleep = <0x00>; | |
| qcom,supply-name = "vci"; | |
| qcom,supply-max-voltage = <0x2dc6c0>; | |
| reg = <0x02>; | |
| qcom,supply-min-voltage = <0x2dc6c0>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-enable-load = <0x30d40>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| }; | |
| }; | |
| qrng@10c3000 { | |
| qcom,no-qrng-config; | |
| compatible = "qcom,msm-rng"; | |
| qcom,no-clock-support; | |
| reg = <0x10c3000 0x1000>; | |
| phandle = <0x35d>; | |
| }; | |
| tpdm@10801000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x43>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-modem-1"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10801000 0x1000>; | |
| phandle = <0x424>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x11c>; | |
| phandle = <0x188>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@10983000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-turing"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10983000 0x1000>; | |
| phandle = <0x43f>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x15d>; | |
| phandle = <0x100>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x15f>; | |
| phandle = <0x15c>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x15e>; | |
| phandle = <0x101>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| source = <0x161>; | |
| remote-endpoint = <0x160>; | |
| phandle = <0x19f>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| source = <0x163>; | |
| remote-endpoint = <0x162>; | |
| phandle = <0x1a2>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x164>; | |
| phandle = <0x1b3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@adf2004 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x06>; | |
| regulator-name = "cam_cc_ife_1_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xadf2004 0x04>; | |
| phandle = <0x4fc>; | |
| }; | |
| syscon@1f40000 { | |
| compatible = "syscon"; | |
| reg = <0x1f40000 0x20000>; | |
| phandle = <0x68>; | |
| }; | |
| tpdm@10844000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-lpass"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10844000 0x1000>; | |
| phandle = <0x40b>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf6>; | |
| phandle = <0x143>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tmc@1004f000 { | |
| iommus = <0x4c 0x500 0x00>; | |
| arm,primecell-periphid = <0xbb961>; | |
| dma-coherent; | |
| arm,scatter-gather; | |
| csr-irqctrl-offset = <0x70>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tmc-base"; | |
| csr-atid-offset = <0x108>; | |
| byte-cntr-class-name = "coresight-tmc-etr1-stream"; | |
| interrupts = <0x00 0x10d 0x01>; | |
| clocks = <0x4e>; | |
| byte-cntr-name = "byte-cntr1"; | |
| coresight-name = "coresight-tmc-etr1"; | |
| compatible = "arm,primecell"; | |
| interrupt-names = "byte-cntr-irq"; | |
| qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; | |
| reg = <0x1004f000 0x1000>; | |
| phandle = <0x45c>; | |
| coresight-csr = <0x1dc>; | |
| qcom,mem_support; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1de>; | |
| phandle = <0x1db>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10cc4000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-tmess_cti_2"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10cc4000 0x1000>; | |
| phandle = <0x47e>; | |
| }; | |
| tpdm@10d40000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x63>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-llcc-0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10d40000 0x1000>; | |
| phandle = <0x42c>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x126>; | |
| phandle = <0x12a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| clock-controller@1fc0000 { | |
| #reset-cells = <0x01>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,kalama-tcsrcc", "syscon"; | |
| reg-name = "cc_base"; | |
| reg = <0x1fc0000 0x30000>; | |
| phandle = <0x5e>; | |
| }; | |
| wsa2_core_clk { | |
| qcom,codec-ext-clk-src = <0x0c>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| status = "disabled"; | |
| phandle = <0x736>; | |
| qcom,codec-lpass-clk-id = <0x310>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| cti@13900000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-apss_cti2"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x13900000 0x1000>; | |
| phandle = <0x476>; | |
| }; | |
| qcom,cpufreq-cdev { | |
| compatible = "qcom,cpufreq-cdev"; | |
| cpu-cluster2 { | |
| qcom,cpus = <0x1f>; | |
| }; | |
| cpu-cluster0 { | |
| qcom,cpus = <0x18 0x19 0x1a>; | |
| }; | |
| cpu-cluster1 { | |
| qcom,cpus = <0x1b 0x1c 0x1d 0x1e>; | |
| }; | |
| }; | |
| qcom,gdsc@adf3280 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x06>; | |
| regulator-name = "cam_cc_sfe_0_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xadf3280 0x04>; | |
| phandle = <0x500>; | |
| }; | |
| clock-controller@ade0000 { | |
| #reset-cells = <0x01>; | |
| vdd_mxa-supply = <0x2a>; | |
| clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; | |
| vdd_mxc-supply = <0x2b>; | |
| clocks = <0x46 0x00 0x46 0x01 0x54 0x45 0x06>; | |
| vdd_mm-supply = <0x28>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,kalama-camcc-v2", "syscon"; | |
| reg-name = "cc_base"; | |
| reg = <0xade0000 0x20000>; | |
| phandle = <0x3b>; | |
| }; | |
| extcon-demo { | |
| compatible = "extcon_demo"; | |
| status = "okay"; | |
| phandle = <0x65e>; | |
| }; | |
| tpdm@10cc1000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x55>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| qcom,hw-enable-check; | |
| coresight-name = "coresight-tpdm-tmess-1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10cc1000 0x1000>; | |
| phandle = <0x42a>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x124>; | |
| phandle = <0x17a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gpu-coresight-gx { | |
| coresight-name = "coresight-gfx"; | |
| coresight-atid = <0x35>; | |
| compatible = "qcom,gpu-coresight-gx"; | |
| phandle = <0x5dd>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5d4>; | |
| phandle = <0x5d5>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| replicator@10b06000 { | |
| arm,primecell-periphid = <0xbb909>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "replicator-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-replicator_swao"; | |
| qcom,replicator-loses-context; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b06000 0x1000>; | |
| phandle = <0x458>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1d4>; | |
| phandle = <0x1d3>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| endpoint { | |
| remote-endpoint = <0x1d5>; | |
| phandle = <0x1d7>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x1d6>; | |
| phandle = <0x1d1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10841000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-prng"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10841000 0x1000>; | |
| phandle = <0x40c>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x103>; | |
| phandle = <0x1a3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_phy1@ae97500 { | |
| pll-label = "dsi_pll_4nm"; | |
| qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
| reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; | |
| qcom,panel-allow-phy-poweroff; | |
| cell-index = <0x01>; | |
| #clock-cells = <0x01>; | |
| label = "dsi-phy-1"; | |
| qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; | |
| compatible = "qcom,dsi-phy-v5.2"; | |
| vdda-0p9-supply = <0x30>; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; | |
| phandle = <0x759>; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x18060>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-max-voltage = <0xd6d80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| }; | |
| }; | |
| }; | |
| qcom,jpegdma0@ac2b000 { | |
| cam_hw_rd_mid = <0x00>; | |
| clock-names = "jpegdma_clk_src", "jpegdma_clk"; | |
| reg-names = "jpegdma_hw", "cam_camnoc"; | |
| reg-cam-base = <0x2b000 0x19000>; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x1db 0x01>; | |
| clocks = <0x3b 0x5e 0x3b 0x5d>; | |
| clock-cntl-level = "nominal"; | |
| cam_hw_pid = <0x10 0x12>; | |
| compatible = "qcom,cam_jpeg_dma_780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "jpegdma_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "jpeg_dma0"; | |
| reg = <0xac2b000 0x1000 0xac19000 0xa080>; | |
| regulator-names = "gdsc"; | |
| phandle = <0x5cb>; | |
| nrt-device; | |
| shared-clks = <0x01 0x00>; | |
| clock-rates = <0x23c34600 0x00>; | |
| cam_hw_wr_mid = <0x01>; | |
| }; | |
| sdhc2-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x63>; | |
| opp-100000000 { | |
| opp-peak-kBps = <0x27100 0x186a0>; | |
| opp-hz = <0x00 0x5f5e100>; | |
| opp-avg-kBps = <0xc350 0x00>; | |
| }; | |
| opp-202000000 { | |
| opp-peak-kBps = <0x30d40 0x1d4c0>; | |
| opp-hz = <0x00 0xc0a4680>; | |
| opp-avg-kBps = <0x19640 0x00>; | |
| }; | |
| }; | |
| qcom,spmi-debug@10b14000 { | |
| #address-cells = <0x02>; | |
| depends-on-supply = <0xe7>; | |
| clock-names = "core_clk"; | |
| reg-names = "core", "fuse"; | |
| clocks = <0x4e>; | |
| #size-cells = <0x00>; | |
| qcom,fuse-enable-bit = <0x12>; | |
| compatible = "qcom,spmi-pmic-arb-debug"; | |
| reg = <0x10b14000 0x60 0x221c8784 0x04>; | |
| phandle = <0x3f4>; | |
| depends-on2-supply = <0xe8>; | |
| qcom,pm8550vs-debug@3 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x03 0x00>; | |
| }; | |
| qcom,pm8550b-debug@7 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x07 0x00>; | |
| }; | |
| qcom,pm8010-debug@d { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| status = "disabled"; | |
| reg = <0x0d 0x00>; | |
| }; | |
| qcom,pmr735d-debug@b { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0b 0x00>; | |
| }; | |
| qcom,pmk8550-debug@0 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x00 0x00>; | |
| }; | |
| qcom,pm8550vs-debug@6 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x06 0x00>; | |
| }; | |
| qcom,pm8550vs-debug@4 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x04 0x00>; | |
| }; | |
| qcom,pm8550ve-debug@5 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x05 0x00>; | |
| }; | |
| qcom,pm8550vs-debug@2 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x02 0x00>; | |
| }; | |
| qcom,pm8010-debug@c { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| status = "disabled"; | |
| reg = <0x0c 0x00>; | |
| }; | |
| qcom,pmr735d-debug@a { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0a 0x00>; | |
| }; | |
| qcom,pm8550-debug@1 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x01 0x00>; | |
| }; | |
| }; | |
| qcom,cci0@ac15000 { | |
| pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; | |
| pinctrl-2 = <0x532 0x533>; | |
| pctrl-idx-mapping = <0x00 0x01>; | |
| pinctrl-0 = <0x52e 0x52f>; | |
| clock-names = "cci_0_clk_src", "cci_0_clk"; | |
| reg-names = "cci"; | |
| reg-cam-base = <0x15000>; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x1aa 0x01>; | |
| clocks = <0x3b 0x09 0x3b 0x08>; | |
| gdscr-supply = <0x2d9>; | |
| pctrl-map-names = "m0", "m1"; | |
| clock-cntl-level = "lowsvs"; | |
| pinctrl-3 = <0x534 0x535>; | |
| compatible = "qcom,cci", "simple-bus"; | |
| src-clock-name = "cci_0_clk_src"; | |
| pinctrl-1 = <0x530 0x531>; | |
| status = "ok"; | |
| interrupt-names = "CCI0"; | |
| reg = <0xac15000 0x1000>; | |
| regulator-names = "gdscr"; | |
| phandle = <0x57a>; | |
| clock-rates = <0x23c3460 0x00>; | |
| qcom,actuator1 { | |
| rgltr-max-voltage = <0x2ab980>; | |
| cell-index = <0x01>; | |
| rgltr-load-current = <0x186a0>; | |
| rgltr-cntrl-support; | |
| cam_vaf-supply = <0x344>; | |
| cci-master = <0x01>; | |
| compatible = "qcom,actuator"; | |
| rgltr-min-voltage = <0x2ab980>; | |
| status = "disabled"; | |
| regulator-names = "cam_vaf"; | |
| phandle = <0x73b>; | |
| }; | |
| qcom,i2c_custom_mode { | |
| hw-tsu-sto = <0x11>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x03>; | |
| hw-thigh = <0x10>; | |
| hw-tlow = <0x16>; | |
| status = "ok"; | |
| hw-thd-dat = <0x10>; | |
| hw-tsu-sta = <0x12>; | |
| hw-scl-stretch-en = <0x01>; | |
| phandle = <0x57d>; | |
| hw-tbuf = <0x18>; | |
| hw-thd-sta = <0x0f>; | |
| }; | |
| qcom,eeprom1 { | |
| rgltr-max-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x558 0x566>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x01>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| clocks = <0x3b 0x61>; | |
| rgltr-load-current = <0xbb8 0x9d3a0 0x00 0x17318 0x19258>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x33b>; | |
| gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; | |
| cam_vaf-supply = <0x33e>; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x339>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80>; | |
| pinctrl-1 = <0x559 0x567>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf"; | |
| phandle = <0x744>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x33 0x65 0x00 0x33 0x75 0x00>; | |
| }; | |
| qcom,cam-sensor2 { | |
| cam_v_custom1-supply = <0x335>; | |
| rgltr-max-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80 0x1b7740>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| eeprom-src = <0x73c>; | |
| pinctrl-0 = <0x55a 0x568>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x02>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| sensor-position-yaw = <0xb4>; | |
| clocks = <0x3b 0x63>; | |
| rgltr-load-current = <0xdac 0xdef30 0x00 0x164a4 0x19258 0xf67c>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x337>; | |
| gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; | |
| cam_vaf-supply = <0x33e>; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x02>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x338>; | |
| cci-master = <0x01>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80 0x1b7740>; | |
| led-flash-src = <0x73a>; | |
| sensor-position-roll = <0x10e>; | |
| pinctrl-1 = <0x55b 0x569>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf", "cam_v_custom1"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x33 0x66 0x00 0x33 0x76 0x00>; | |
| }; | |
| qcom,i2c_standard_mode { | |
| hw-tsu-sto = <0xcc>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0xc9>; | |
| hw-tlow = <0xae>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0xe7>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x57b>; | |
| hw-tbuf = <0xe3>; | |
| hw-thd-sta = <0xa2>; | |
| }; | |
| qcom,cam-sensor0 { | |
| rgltr-max-voltage = <0x1b7740 0x124f80 0x00 0x2ab980 0x2ab980>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x564>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x00>; | |
| gpio-req-tbl-num = <0x01 0x02>; | |
| sensor-position-yaw = <0xb4>; | |
| clocks = <0x3b 0x5f>; | |
| rgltr-load-current = <0x25d78 0xa6040 0x00 0xc350 0x186a0>; | |
| actuator-src = <0x739>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x340>; | |
| gpio-req-tbl-label = "CAM_RESET0", "CAM_STANDBY"; | |
| cam_vaf-supply = <0x341>; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x00>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x33f>; | |
| gpio-standby = <0x02>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x124f80 0x00 0x2ab980 0x2ab980>; | |
| led-flash-src = <0x73a>; | |
| sensor-position-roll = <0x10e>; | |
| pinctrl-1 = <0x565>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x00 0x00>; | |
| gpios = <0x33 0x74 0x00 0x33 0x85 0x00>; | |
| }; | |
| qcom,eeprom2 { | |
| cam_v_custom1-supply = <0x335>; | |
| rgltr-max-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80 0x1b7740>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x55a 0x568>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x02>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| clocks = <0x3b 0x63>; | |
| rgltr-load-current = <0xdac 0xdef30 0x00 0x164a4 0x19258 0xf67c>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x337>; | |
| gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; | |
| cam_vaf-supply = <0x33e>; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x338>; | |
| cci-master = <0x01>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2d2a80 0x1b7740>; | |
| pinctrl-1 = <0x55b 0x569>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf", "cam_v_custom1"; | |
| phandle = <0x73c>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x33 0x66 0x00 0x33 0x76 0x00>; | |
| }; | |
| qcom,actuator0 { | |
| rgltr-max-voltage = <0x2ab980>; | |
| cell-index = <0x00>; | |
| rgltr-load-current = <0x186a0>; | |
| rgltr-cntrl-support; | |
| cam_vaf-supply = <0x341>; | |
| cci-master = <0x00>; | |
| compatible = "qcom,actuator"; | |
| rgltr-min-voltage = <0x2ab980>; | |
| status = "disabled"; | |
| regulator-names = "cam_vaf"; | |
| phandle = <0x739>; | |
| }; | |
| qcom,eeprom0 { | |
| cam_v_custom1-supply = <0x33d>; | |
| rgltr-max-voltage = <0x1b7740 0x14a140 0x00 0x2ab980 0x326a40 0x36ee80>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| cam_v_custom2-supply = <0x65c>; | |
| pinctrl-0 = <0x564>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x00>; | |
| gpio-req-tbl-num = <0x01>; | |
| clocks = <0x3b 0x5f>; | |
| rgltr-load-current = <0x25d78 0xa6040 0x00 0xc350 0x7530 0x2625a0>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x33a>; | |
| gpio-req-tbl-label = "CAM_RESET0"; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x31f>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x124f80 0x00 0x2ab980 0x326a40 0x36ee80>; | |
| pinctrl-1 = <0x565>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; | |
| phandle = <0x743>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x00>; | |
| gpios = <0x33 0x74 0x00>; | |
| }; | |
| qcom,i2c_fast_plus_mode { | |
| hw-tsu-sto = <0x11>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x03>; | |
| hw-thigh = <0x10>; | |
| hw-tlow = <0x16>; | |
| status = "ok"; | |
| hw-thd-dat = <0x10>; | |
| hw-tsu-sta = <0x12>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x57e>; | |
| hw-tbuf = <0x18>; | |
| hw-thd-sta = <0x0f>; | |
| }; | |
| qcom,cam-sensor1 { | |
| rgltr-max-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2ab980>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x558 0x566>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x01>; | |
| gpio-req-tbl-num = <0x00 0x01 0x02>; | |
| sensor-position-yaw = <0xb4>; | |
| clocks = <0x3b 0x61>; | |
| rgltr-load-current = <0xbb8 0x9d3a0 0x00 0x17318 0x186a0>; | |
| actuator-src = <0x73b>; | |
| cam_vio-supply = <0x33c>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x343>; | |
| gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1", "CAM_STANDBY"; | |
| cam_vaf-supply = <0x344>; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x01>; | |
| clock-cntl-level = "nominal"; | |
| cam_vdig-supply = <0x342>; | |
| gpio-standby = <0x02>; | |
| cci-master = <0x01>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x10d880 0x00 0x2ab980 0x2ab980>; | |
| sensor-position-roll = <0x10e>; | |
| pinctrl-1 = <0x559 0x567>; | |
| status = "disabled"; | |
| regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x2d9>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00 0x00>; | |
| gpios = <0x33 0x65 0x00 0x33 0x75 0x00 0x33 0x5b 0x00>; | |
| }; | |
| qcom,i2c_fast_mode { | |
| hw-tsu-sto = <0x28>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0x26>; | |
| hw-tlow = <0x38>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0x28>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x57c>; | |
| hw-tbuf = <0x3e>; | |
| hw-thd-sta = <0x23>; | |
| }; | |
| }; | |
| va_mini_dump { | |
| memory-region = <0x52>; | |
| compatible = "qcom,va-minidump"; | |
| status = "ok"; | |
| }; | |
| cti@13862000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-apss_atb_cti"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x13862000 0x1000>; | |
| phandle = <0x483>; | |
| }; | |
| qcom,csiphy1@ace6000 { | |
| csi-vdd-1p2-supply = <0x31>; | |
| rgltr-max-voltage = <0x00 0x124f80 0xe1d48>; | |
| csi-vdd-0p9-supply = <0x30>; | |
| clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0xe6000>; | |
| cell-index = <0x01>; | |
| interrupts = <0x00 0x1de 0x01>; | |
| clocks = <0x3b 0x1b 0x3b 0x33 0x3b 0x22 0x3b 0x21>; | |
| rgltr-load-current = <0x00 0x4650 0x7dc8>; | |
| gdscr-supply = <0x2d9>; | |
| rgltr-cntrl-support; | |
| clock-cntl-level = "lowsvs", "nominal"; | |
| compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; | |
| rgltr-min-voltage = <0x00 0x124f80 0xd59f8>; | |
| src-clock-name = "csi1phytimer_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "CSIPHY1"; | |
| reg = <0xace6000 0x2000>; | |
| regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; | |
| phandle = <0x573>; | |
| shared-clks = <0x01 0x00 0x00 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; | |
| }; | |
| qcedev@1de0000 { | |
| iommus = <0x4c 0x480 0x00 0x4c 0x481 0x00>; | |
| qcom,ce-hw-shared; | |
| dma-coherent; | |
| interconnect-names = "data_path"; | |
| qcom,ce-device = <0x00>; | |
| interconnects = <0x4a 0x27 0x4b 0x200>; | |
| reg-names = "crypto-base", "crypto-bam-base"; | |
| qcom,bam-pipe-offload-hlos-cpb = <0x03>; | |
| qcom,bam-ee = <0x00>; | |
| interrupts = <0x00 0x110 0x04>; | |
| qcom,bam-pipe-offload-hlos-hlos = <0x04>; | |
| compatible = "qcom,qcedev"; | |
| qcom,no-clock-support; | |
| qcom,bam-pipe-pair = <0x02>; | |
| reg = <0x1de0000 0x20000 0x1dc4000 0x28000>; | |
| phandle = <0x35c>; | |
| qcom,bam-pipe-offload-cpb-hlos = <0x01>; | |
| qcom,smmu-s1-enable; | |
| qcom,offload-ops-support; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,iommu-dma = "atomic"; | |
| qcom_cedev_s_cb { | |
| iommus = <0x4c 0x483 0x00>; | |
| dma-coherent; | |
| qcom,secure-context-bank; | |
| label = "secure_context"; | |
| compatible = "qcom,qcedev,context-bank"; | |
| qcom,iommu-vmid = <0x09>; | |
| }; | |
| qcom_cedev_ns_cb { | |
| iommus = <0x4c 0x481 0x00>; | |
| dma-coherent; | |
| label = "ns_context"; | |
| compatible = "qcom,qcedev,context-bank"; | |
| }; | |
| }; | |
| qcom,mem-buf-msgq { | |
| compatible = "qcom,mem-buf-msgq"; | |
| }; | |
| qcom,rt-cdm1@ac26000 { | |
| clock-names = "cam_cc_cpas_ahb_clk"; | |
| reg-names = "rt-cdm1"; | |
| fifo-depths = <0x40 0x00 0x00 0x00>; | |
| reg-cam-base = <0x26000>; | |
| cdm-client-names = "ife1", "dualife1"; | |
| cell-index = <0x01>; | |
| interrupts = <0x00 0x297 0x01>; | |
| clocks = <0x3b 0x0f>; | |
| label = "rt-cdm"; | |
| clock-cntl-level = "turbo"; | |
| cam_hw_pid = <0x1a>; | |
| compatible = "qcom,cam-rt-cdm2_1"; | |
| gdsc-supply = <0x2d9>; | |
| status = "ok"; | |
| interrupt-names = "rt-cdm1"; | |
| reg = <0xac26000 0x400>; | |
| regulator-names = "gdsc"; | |
| cam-hw-mid = <0x00>; | |
| nrt-device; | |
| single-context-cdm; | |
| clock-rates = <0x00>; | |
| config-fifo; | |
| }; | |
| funnel@10041000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-in0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10041000 0x1000>; | |
| phandle = <0x451>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1b9>; | |
| phandle = <0x10b>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x1ba>; | |
| phandle = <0x10d>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x1bb>; | |
| phandle = <0x1b8>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1bc>; | |
| phandle = <0x1c4>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,sde_rscc@af20000 { | |
| interconnect-names = "qcom,sde-data-bus0"; | |
| qcom,sde-rsc-version = <0x05>; | |
| clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; | |
| interconnects = <0xec 0x3e9 0x4b 0x5e8>; | |
| reg-names = "drv", "wrapper"; | |
| cell-index = <0x00>; | |
| qcom,msm-bus,active-only; | |
| qcom,sde-dram-channels = <0x02>; | |
| clocks = <0x3c 0x47 0x3c 0x41 0x3c 0x46>; | |
| vdd-supply = <0x2da>; | |
| compatible = "qcom,sde-rsc"; | |
| reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; | |
| phandle = <0x74d>; | |
| }; | |
| cti@10962000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-gpu_cortex_m3"; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10962000 0x1000>; | |
| phandle = <0x466>; | |
| }; | |
| qcom,csiphy7@acf2000 { | |
| csi-vdd-1p2-supply = <0x31>; | |
| rgltr-max-voltage = <0x00 0x124f80 0xe1d48>; | |
| csi-vdd-0p9-supply = <0x30>; | |
| clock-names = "cphy_rx_clk_src", "csiphy7_clk", "csi7phytimer_clk_src", "csi7phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0xf2000>; | |
| cell-index = <0x07>; | |
| interrupts = <0x00 0x115 0x01>; | |
| clocks = <0x3b 0x1b 0x3b 0x39 0x3b 0x2e 0x3b 0x2d>; | |
| rgltr-load-current = <0x00 0x4650 0x7dc8>; | |
| gdscr-supply = <0x2d9>; | |
| rgltr-cntrl-support; | |
| clock-cntl-level = "lowsvs", "nominal"; | |
| compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; | |
| rgltr-min-voltage = <0x00 0x124f80 0xd59f8>; | |
| src-clock-name = "csi7phytimer_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "CSIPHY7"; | |
| reg = <0xacf2000 0x2000>; | |
| regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; | |
| phandle = <0x579>; | |
| shared-clks = <0x01 0x00 0x00 0x00>; | |
| clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; | |
| }; | |
| tpdm_lpass_lpi { | |
| atid = <0x1a>; | |
| qcom,dummy-source; | |
| coresight-name = "coresight-tpdm-lpass-lpi"; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x405>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf0>; | |
| phandle = <0x132>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,trust_ui_vm@0xf78f8000 { | |
| reg = <0xf78f8000 0x108000>; | |
| phandle = <0x8c>; | |
| shared-buffers = <0x87 0x88 0x89>; | |
| vm_name = "trustedvm"; | |
| }; | |
| qcom,cam-sync { | |
| compatible = "qcom,cam-sync"; | |
| status = "ok"; | |
| }; | |
| subsystem-sleep-stats@c3f0000 { | |
| compatible = "qcom,subsystem-sleep-stats"; | |
| reg = <0xc3f0000 0x400>; | |
| ddr-freq-update; | |
| }; | |
| gh-secure-vm-loader@0 { | |
| memory-region = <0x84>; | |
| qcom,pas-id = <0x1c>; | |
| compatible = "qcom,gh-secure-vm-loader"; | |
| qcom,vmid = <0x2d>; | |
| qcom,firmware-name = "trustedvm"; | |
| virtio-backends = <0x8d 0x8e>; | |
| }; | |
| qcom,dp_display@ae90000 { | |
| qcom,aux-cfg1-settings = [24 13]; | |
| pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; | |
| qcom,dsc-continuous-pps; | |
| qcom,pll-revision = "4nm-v1.1"; | |
| qcom,aux-cfg6-settings = [38 0a]; | |
| vdda_usb-0p9-supply = <0x30>; | |
| qcom,qos-cpu-mask = <0x0f>; | |
| qcom,altmode-dev = <0x3f7 0x00>; | |
| pinctrl-0 = <0x755>; | |
| qcom,ext-disp = <0x754>; | |
| clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_iface_clk", "link_parent", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; | |
| reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; | |
| qcom,mst-enable; | |
| qcom,aux-cfg2-settings = [28 a4]; | |
| cell-index = <0x00>; | |
| interrupts = <0x0c 0x00>; | |
| clocks = <0x3c 0x0c 0x46 0x00 0x5e 0x05 0x45 0xa5 0x3c 0x0f 0x3c 0x10 0x3c 0x12 0x74e 0x00 0x3c 0x14 0x74e 0x01 0x3c 0x16 0x3c 0x13 0x3c 0x15>; | |
| qcom,max-pclk-frequency-khz = <0xa4cb8>; | |
| qcom,aux-cfg7-settings = [3c 03]; | |
| qcom,dsc-feature-enable; | |
| #clock-cells = <0x01>; | |
| interrupt-parent = <0x752>; | |
| vdd_mx-supply = <0x2a>; | |
| qcom,aux-cfg3-settings = ","; | |
| vdda-1p2-supply = <0x31>; | |
| qcom,aux-cfg8-settings = [40 b7]; | |
| qcom,fec-feature-enable; | |
| compatible = "qcom,dp-display"; | |
| qcom,qos-cpu-latency-us = <0x12c>; | |
| pinctrl-1 = <0x756>; | |
| vdda-0p9-supply = <0x2b7>; | |
| usb-controller = <0x4c4>; | |
| qcom,aux-cfg4-settings = [30 0a]; | |
| reg = <0xae90000 0xfc 0xae90200 0xc0 0xae90400 0x770 0xae91000 0x98 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xae91400 0x98 0xaf09000 0x14>; | |
| usb-phy = <0x2b6>; | |
| qcom,phy-version = <0x600>; | |
| phandle = <0x74e>; | |
| qcom,aux-en-gpio = <0x33 0x8c 0x00>; | |
| qcom,aux-cfg9-settings = [44 03]; | |
| qcom,aux-cfg0-settings = " "; | |
| qcom,aux-sel-gpio = <0x33 0x8d 0x00>; | |
| qcom,aux-cfg5-settings = [34 26]; | |
| qcom,widebus-enable; | |
| dp_phy_gdsc-supply = <0x2b8>; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x7594>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| }; | |
| }; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x1c138>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-max-voltage = <0xdea80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0xdea80>; | |
| }; | |
| qcom,phy-supply-entry@1 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x4edb8>; | |
| qcom,supply-name = "vdda_usb-0p9"; | |
| qcom,supply-max-voltage = <0xd6d80>; | |
| reg = <0x01>; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| }; | |
| }; | |
| qcom,pll-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,pll-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "vdd_mx"; | |
| qcom,supply-max-voltage = <0xffff>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x180>; | |
| }; | |
| }; | |
| }; | |
| cti@10881000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-spss_cti"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x10881000 0x1000>; | |
| phandle = <0x486>; | |
| }; | |
| tpdm_lpicc { | |
| atid = <0x1b>; | |
| qcom,dummy-source; | |
| coresight-name = "coresight-tpdm-lpicc"; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x42b>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x125>; | |
| phandle = <0x12f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,oem_vm@f7afc000 { | |
| reg = <0xf7afc000 0x104000>; | |
| phandle = <0x8f>; | |
| shared-buffers = <0x8a 0x8b>; | |
| vm_name = "oemvm"; | |
| }; | |
| qcom,camera-flash2 { | |
| cell-index = <0x02>; | |
| torch-source = <0x61f 0x620>; | |
| switch-source = <0x625>; | |
| compatible = "qcom,camera-flash"; | |
| status = "ok"; | |
| phandle = <0x741>; | |
| flash-source = <0x61b 0x61c>; | |
| }; | |
| mini_dump_mode { | |
| compatible = "qcom,minidump"; | |
| status = "ok"; | |
| }; | |
| limits-stat { | |
| compatible = "qcom,limits-stat"; | |
| phandle = <0x4f8>; | |
| qcom,limits-stat-sensor-names = "cpu-0-0", "cpu-0-1", "cpu-0-2", "cpu-1-0", "cpu-1-1", "cpu-1-2", "cpu-1-3", "cpu-1-4", "gpuss-0", "gpuss-1", "nspss-0", "nspss-1", "nspss-2"; | |
| }; | |
| tpda@13863000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x03 0x40>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpda-apss"; | |
| qcom,dsb-elem-size = <0x02 0x20 0x04 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x42>; | |
| reg = <0x13863000 0x1000>; | |
| phandle = <0x44c>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x193>; | |
| phandle = <0x116>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x195>; | |
| phandle = <0x119>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x194>; | |
| phandle = <0x117>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x197>; | |
| phandle = <0x11a>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x196>; | |
| phandle = <0x118>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x198>; | |
| phandle = <0x19a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10c09000 { | |
| arm,primecell-periphid = <0xbb922>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-cti-dlmm_cti0"; | |
| qcom,extended_cti; | |
| compatible = "arm,coresight-cti", "arm,primecell"; | |
| reg = <0x10c09000 0x1000>; | |
| phandle = <0x460>; | |
| }; | |
| qcom,mem-buf { | |
| qcom,mem-buf-capabilities = "supplier"; | |
| compatible = "qcom,mem-buf"; | |
| qcom,vmid = <0x03>; | |
| }; | |
| wsa_spkr_en1_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x69c>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x69d>; | |
| status = "disabled"; | |
| phandle = <0x668>; | |
| }; | |
| qcom,guestvm_loader@80a00000 { | |
| memory-region = <0x85>; | |
| qcom,pas-id = <0x23>; | |
| compatible = "qcom,guestvm-loader"; | |
| qcom,vmid = <0x32>; | |
| qcom,firmware-name = "cpusys_vm"; | |
| }; | |
| tgu@10b0f000 { | |
| arm,primecell-periphid = <0xbb999>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tgu-base"; | |
| clocks = <0x4e>; | |
| tgu-regs = <0x09>; | |
| tgu-steps = <0x03>; | |
| coresight-name = "coresight-tgu-spmi0"; | |
| tgu-conditions = <0x04>; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b0f000 0x1000>; | |
| phandle = <0x48f>; | |
| tgu-timer-counters = <0x08>; | |
| }; | |
| qcom,sfe1@aca6000 { | |
| sfe1-supply = <0x501>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; | |
| reg-names = "sfe1"; | |
| reg-cam-base = "", "\n`"; | |
| cell-index = <0x01>; | |
| interrupts = <0x00 0x1b1 0x01>; | |
| clocks = <0x3b 0x93 0x3b 0x92 0x3b 0x91 0x3b 0x1a>; | |
| rt-wrapper-base = <0x62000>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| cam_hw_pid = <0x0c 0x05>; | |
| compatible = "qcom,sfe780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "sfe_1_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "sfe1"; | |
| reg = <0xaca6000 0x8000>; | |
| regulator-names = "gdsc", "sfe1"; | |
| phandle = <0x5b9>; | |
| clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; | |
| }; | |
| funnel@10846000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-funnel-lpass"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10846000 0x1000>; | |
| phandle = <0x438>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x143>; | |
| phandle = <0xf6>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x144>; | |
| phandle = <0x1aa>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gic-interrupt-router { | |
| qcom,gic-class1-cpus = <0x03 0x04 0x05 0x06 0x07>; | |
| qcom,gic-class0-cpus = <0x00 0x01 0x02>; | |
| compatible = "qcom,gic-intr-routing"; | |
| }; | |
| spf_core_platform { | |
| compatible = "qcom,spf-core-platform"; | |
| phandle = <0x51d>; | |
| lpass-cdc { | |
| qcom,num-macros = <0x03>; | |
| qcom,lpass-cdc-version = <0x07>; | |
| #address-cells = <0x01>; | |
| clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; | |
| clocks = <0x517 0x00 0x518 0x00>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,lpass-cdc"; | |
| phandle = <0x521>; | |
| wcd938x-codec { | |
| qcom,rx-slave = <0x66e>; | |
| qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; | |
| qcom,cdc-vdd-mic-bias-current = <0x7530>; | |
| qcom,wcd-rst-gpio-node = <0x66d>; | |
| qcom,tx-slave = <0x66f>; | |
| qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; | |
| qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; | |
| qcom,cdc-micbias2-mv = <0x708>; | |
| qcom,cdc-vdd-rxtx-voltage = <0x1b7740 0x1b7740>; | |
| qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15>; | |
| qcom,cdc-vdd-rxtx-current = <0x7530>; | |
| cdc-vdd-buck-supply = <0x30f>; | |
| qcom,cdc-vddio-lpm-supported = <0x01>; | |
| qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddio", "cdc-vdd-mic-bias"; | |
| cdc-vdd-rxtx-supply = <0x30f>; | |
| qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
| compatible = "qcom,wcd938x-codec"; | |
| qcom,cdc-vdd-buck-current = <0x9eb10>; | |
| qcom,cdc-vddio-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-micbias4-mv = <0x708>; | |
| cdc-vdd-mic-bias-supply = <0x312>; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| qcom,cdc-vddio-current = <0x7530>; | |
| cdc-vddio-supply = <0x30f>; | |
| phandle = <0x664>; | |
| qcom,cdc-vdd-buck-lpm-supported = <0x01>; | |
| qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; | |
| qcom,cdc-vdd-rxtx-lpm-supported = <0x01>; | |
| qcom,split-codec = <0x01>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| }; | |
| rx-macro@6AC0000 { | |
| qcom,default-clk-id = <0x05>; | |
| clock-names = "rx_mclk2_2x_clk"; | |
| clocks = <0x666 0x00>; | |
| qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; | |
| compatible = "qcom,lpass-cdc-rx-macro"; | |
| reg = <0x6ac0000 0x00>; | |
| qcom,rx-bcl-pmic-params = [00 03 48]; | |
| phandle = <0x72b>; | |
| qcom,rx-swr-gpios = <0x665>; | |
| rx_swr_master { | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; | |
| qcom,swr-num-dev = <0x02>; | |
| interrupts = <0x00 0x9b 0x04>; | |
| clocks = <0x517 0x00 0x518 0x00>; | |
| swrm-io-base = <0x6ad0000 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,swr_master_id = <0x02>; | |
| compatible = "qcom,swr-mstr"; | |
| qcom,mipi-sdw-block-packing-mode = <0x01>; | |
| interrupt-names = "swr_master_irq"; | |
| qcom,swr-port-mapping = <0x01 0x0e 0x01 0x01 0x0f 0x02 0x02 0x12 0x03 0x03 0x10 0x01 0x03 0x11 0x02 0x04 0x13 0x01 0x05 0x14 0x01 0x05 0x15 0x02 0x06 0x16 0x01 0x07 0x17 0x03 0x08 0x18 0x03 0x09 0x19 0x03 0x0a 0x1a 0x03 0x0b 0x1b 0x03 0x0c 0x1c 0x03>; | |
| phandle = <0x72c>; | |
| qcom,swr-num-ports = <0x0c>; | |
| swr_haptics@f0170220 { | |
| qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; | |
| compatible = "qcom,pm8550b-swr-haptics"; | |
| status = "disabled"; | |
| swr-slave-supply = <0x62c>; | |
| reg = <0x02 0xf0170220>; | |
| phandle = <0x673>; | |
| }; | |
| wcd938x-rx-slave { | |
| compatible = "qcom,wcd938x-slave"; | |
| reg = <0x0d 0x1170224>; | |
| phandle = <0x66e>; | |
| }; | |
| }; | |
| }; | |
| va-macro@6D44000 { | |
| qcom,default-clk-id = <0x00>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,va-clk-mux-select = <0x01>; | |
| clocks = <0x518 0x00>; | |
| qcom,va-dmic-sample-rate = <0x927c0>; | |
| qcom,use-clk-id = <0x03>; | |
| compatible = "qcom,lpass-cdc-va-macro"; | |
| qcom,va-swr-gpios = <0x663>; | |
| qcom,va-island-mode-muxsel = <0x6e28000>; | |
| reg = <0x6d44000 0x00>; | |
| phandle = <0x724>; | |
| qcom,is-used-swr-gpio = <0x01>; | |
| va_swr_master { | |
| qcom,is-always-on = <0x01>; | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; | |
| qcom,swr-num-dev = <0x05>; | |
| interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; | |
| clocks = <0x517 0x00 0x518 0x00>; | |
| swrm-io-base = <0x6d30000 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,swr_master_id = <0x03>; | |
| compatible = "qcom,swr-mstr"; | |
| qcom,mipi-sdw-block-packing-mode = <0x01>; | |
| interrupt-names = "swr_master_irq", "swr_wake_irq"; | |
| qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; | |
| phandle = <0x725>; | |
| qcom,swr-wakeup-required = <0x01>; | |
| qcom,swr-mstr-irq-wakeup-capable = <0x01>; | |
| qcom,swr-num-ports = <0x05>; | |
| dmic_swr@58350220 { | |
| qcom,swr-dmic-supply = <0x03>; | |
| qcom,wcd-handle = <0x664>; | |
| sound-name-prefix = "SWR_MIC0"; | |
| compatible = "qcom,swr-dmic"; | |
| qcom,codec-name = "swr-dmic.01"; | |
| status = "disabled"; | |
| reg = <0x08 0x58350220>; | |
| phandle = <0x729>; | |
| }; | |
| dmic_swr@58350223 { | |
| qcom,swr-dmic-supply = <0x03>; | |
| qcom,wcd-handle = <0x664>; | |
| sound-name-prefix = "SWR_MIC3"; | |
| compatible = "qcom,swr-dmic"; | |
| qcom,codec-name = "swr-dmic.04"; | |
| status = "disabled"; | |
| reg = <0x08 0x58350223>; | |
| phandle = <0x726>; | |
| }; | |
| dmic_swr@58350221 { | |
| qcom,swr-dmic-supply = <0x01>; | |
| qcom,wcd-handle = <0x664>; | |
| sound-name-prefix = "SWR_MIC1"; | |
| compatible = "qcom,swr-dmic"; | |
| qcom,codec-name = "swr-dmic.02"; | |
| status = "disabled"; | |
| reg = <0x08 0x58350221>; | |
| phandle = <0x728>; | |
| }; | |
| wcd938x-tx-slave { | |
| compatible = "qcom,wcd938x-slave"; | |
| reg = <0x0d 0x1170223>; | |
| phandle = <0x66f>; | |
| }; | |
| dmic_swr@58350222 { | |
| qcom,swr-dmic-supply = <0x01>; | |
| qcom,wcd-handle = <0x664>; | |
| sound-name-prefix = "SWR_MIC2"; | |
| compatible = "qcom,swr-dmic"; | |
| qcom,codec-name = "swr-dmic.03"; | |
| status = "disabled"; | |
| reg = <0x08 0x58350222>; | |
| phandle = <0x727>; | |
| }; | |
| }; | |
| }; | |
| tx-macro@6AE0000 { | |
| qcom,default-clk-id = <0x00>; | |
| qcom,tx-dmic-sample-rate = <0x249f00>; | |
| compatible = "qcom,lpass-cdc-tx-macro"; | |
| reg = <0x6ae0000 0x00>; | |
| phandle = <0x72a>; | |
| qcom,is-used-swr-gpio = <0x00>; | |
| }; | |
| wsa2-macro@6AA0000 { | |
| qcom,default-clk-id = <0x07>; | |
| qcom,wsa2-bcl-pmic-params = [00 03 48]; | |
| qcom,thermal-max-state = <0x0b>; | |
| qcom,noise-gate-mode = <0x02>; | |
| compatible = "qcom,lpass-cdc-wsa2-macro"; | |
| status = "disabled"; | |
| qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; | |
| reg = <0x6aa0000 0x00>; | |
| phandle = <0x66c>; | |
| qcom,wsa2-swr-gpios = <0x66b>; | |
| qcom,wsa-bat-cfgs = <0x01 0x01>; | |
| #cooling-cells = <0x02>; | |
| qcom,wsa-rloads = <0x02 0x02>; | |
| wsa2_swr_master { | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; | |
| qcom,swr-num-dev = <0x00>; | |
| interrupts = <0x00 0xab 0x04>; | |
| qcom,dynamic-port-map-supported = <0x00>; | |
| clocks = <0x517 0x00 0x518 0x00>; | |
| swrm-io-base = <0x6ab0000 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,swr_master_id = <0x04>; | |
| compatible = "qcom,swr-mstr"; | |
| status = "disabled"; | |
| qcom,mipi-sdw-block-packing-mode = <0x00>; | |
| interrupt-names = "swr_master_irq"; | |
| qcom,swr-port-mapping = <0x01 0x01 0x01 0x02 0x02 0x0f 0x03 0x03 0x03 0x04 0x04 0x01 0x05 0x05 0x0f 0x06 0x06 0x03 0x07 0x07 0x03 0x08 0x08 0x03 0x09 0x09 0x03 0x0a 0x0a 0x03 0x0b 0x0b 0x03 0x0c 0x0c 0x03 0x0d 0x0d 0x03>; | |
| phandle = <0x730>; | |
| qcom,swr-num-ports = <0x0d>; | |
| wsa884x@02170220 { | |
| qcom,wsa-macro-handle = <0x66c>; | |
| qcom,lpass-cdc-handle = <0x521>; | |
| qcom,cdc-vdd-1p8-lpm-supported = <0x01>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; | |
| sound-name-prefix = "Spkr2Left"; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| compatible = "qcom,wsa884x_2"; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| status = "disabled"; | |
| reg = <0x04 0x2170220>; | |
| qcom,spkr-sd-n-node = <0x668>; | |
| phandle = <0x731>; | |
| cdc-vdd-1p8-supply = <0x30f>; | |
| }; | |
| wsa884x@02170221 { | |
| qcom,wsa-macro-handle = <0x66c>; | |
| qcom,lpass-cdc-handle = <0x521>; | |
| qcom,cdc-vdd-1p8-lpm-supported = <0x01>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; | |
| sound-name-prefix = "Spkr2Right"; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| compatible = "qcom,wsa884x_2"; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| status = "disabled"; | |
| reg = <0x04 0x2170221>; | |
| qcom,spkr-sd-n-node = <0x66a>; | |
| phandle = <0x732>; | |
| cdc-vdd-1p8-supply = <0x30f>; | |
| }; | |
| }; | |
| }; | |
| lpass-cdc-clk-rsc-mngr { | |
| clock-names = "tx_core_clk", "rx_core_clk", "rx_tx_core_clk", "va_core_clk"; | |
| qcom,va_mclk_mode_muxsel = <0x6e28000>; | |
| clocks = <0x65f 0x00 0x660 0x00 0x661 0x00 0x662 0x00>; | |
| qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; | |
| qcom,fs-gen-sequence = <0x3000 0x01 0x01 0x3004 0x03 0x03 0x3004 0x03 0x01 0x3080 0x02 0x02>; | |
| compatible = "qcom,lpass-cdc-clk-rsc-mngr"; | |
| }; | |
| wsa-macro@6B00000 { | |
| qcom,wsa-swr-gpios = <0x667>; | |
| qcom,default-clk-id = <0x06>; | |
| qcom,wsa-bcl-pmic-params = [00 03 48]; | |
| qcom,thermal-max-state = <0x0b>; | |
| qcom,noise-gate-mode = <0x02>; | |
| compatible = "qcom,lpass-cdc-wsa-macro"; | |
| status = "disabled"; | |
| qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; | |
| reg = <0x6b00000 0x00>; | |
| phandle = <0x669>; | |
| qcom,wsa-bat-cfgs = <0x01 0x01>; | |
| #cooling-cells = <0x02>; | |
| qcom,wsa-rloads = <0x02 0x02>; | |
| wsa_swr_master { | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; | |
| qcom,swr-num-dev = <0x00>; | |
| interrupts = <0x00 0xaa 0x04>; | |
| qcom,dynamic-port-map-supported = <0x00>; | |
| clocks = <0x517 0x00 0x518 0x00>; | |
| swrm-io-base = <0x6b10000 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,swr_master_id = <0x01>; | |
| compatible = "qcom,swr-mstr"; | |
| status = "disabled"; | |
| qcom,mipi-sdw-block-packing-mode = <0x00>; | |
| interrupt-names = "swr_master_irq"; | |
| qcom,swr-port-mapping = <0x01 0x01 0x01 0x02 0x02 0x0f 0x03 0x03 0x03 0x04 0x04 0x01 0x05 0x05 0x0f 0x06 0x06 0x03 0x07 0x07 0x03 0x08 0x08 0x03 0x09 0x09 0x03 0x0a 0x0a 0x03 0x0b 0x0b 0x03 0x0c 0x0c 0x03 0x0d 0x0d 0x03>; | |
| phandle = <0x72d>; | |
| qcom,swr-num-ports = <0x0d>; | |
| wsa884x@02170220 { | |
| qcom,wsa-macro-handle = <0x669>; | |
| qcom,lpass-cdc-handle = <0x521>; | |
| qcom,cdc-vdd-1p8-lpm-supported = <0x01>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; | |
| sound-name-prefix = "SpkrLeft"; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| compatible = "qcom,wsa884x"; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| status = "disabled"; | |
| reg = <0x04 0x2170220>; | |
| qcom,spkr-sd-n-node = <0x668>; | |
| phandle = <0x72e>; | |
| cdc-vdd-1p8-supply = <0x30f>; | |
| }; | |
| wsa884x@02170221 { | |
| qcom,wsa-macro-handle = <0x669>; | |
| qcom,lpass-cdc-handle = <0x521>; | |
| qcom,cdc-vdd-1p8-lpm-supported = <0x01>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; | |
| sound-name-prefix = "SpkrRight"; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| compatible = "qcom,wsa884x"; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| status = "disabled"; | |
| reg = <0x04 0x2170221>; | |
| qcom,spkr-sd-n-node = <0x66a>; | |
| phandle = <0x72f>; | |
| cdc-vdd-1p8-supply = <0x30f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| wsa_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x676 0x677>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x678 0x679>; | |
| status = "disabled"; | |
| phandle = <0x667>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| cdc_dmic01_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x68c 0x68d>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x68e 0x68f>; | |
| phandle = <0x670>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| cdc_dmic45_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x694 0x695>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x696 0x697>; | |
| phandle = <0x672>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| qcom,msm-audio-ion { | |
| iommus = <0x4c 0x1001 0x80 0x4c 0x1061 0x00>; | |
| dma-coherent; | |
| qcom,smmu-enabled; | |
| qcom,smmu-sid-mask = <0x00 0x0f>; | |
| compatible = "qcom,msm-audio-ion"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>; | |
| phandle = <0x51e>; | |
| qcom,smmu-version = <0x02>; | |
| }; | |
| qcom,msm-audio-ion-cma { | |
| compatible = "qcom,msm-audio-ion-cma"; | |
| phandle = <0x51f>; | |
| }; | |
| tx_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x684 0x685 0x686 0x687>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x688 0x689 0x68a 0x68b>; | |
| phandle = <0x663>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| sound { | |
| qcom,audio-routing = "AMIC1", "Analog Mic1", "AMIC1", "MIC BIAS1", "AMIC2", "Analog Mic2", "AMIC2", "MIC BIAS2", "AMIC5", "Analog Mic5", "AMIC5", "MIC BIAS4", "DMIC2", "Digital Mic2", "DMIC2", "MIC BIAS3", "DMIC3", "Digital Mic3", "DMIC3", "MIC BIAS3", "VA AMIC1", "Analog Mic1", "VA AMIC1", "VA MIC BIAS1", "VA AMIC2", "Analog Mic2", "VA AMIC2", "VA MIC BIAS2", "VA AMIC5", "Analog Mic5", "VA AMIC5", "VA MIC BIAS4", "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", "IN3_AUX", "AUX_OUT", "RX_TX DEC0_INP", "TX DEC0 MUX", "RX_TX DEC1_INP", "TX DEC1 MUX", "RX_TX DEC2_INP", "TX DEC2 MUX", "RX_TX DEC3_INP", "TX DEC3 MUX", "TX SWR_INPUT", "WCD_TX_OUTPUT", "VA SWR_INPUT", "VA_SWR_CLK", "VA SWR_INPUT", "WCD_TX_OUTPUT", "VA_AIF1 CAP", "VA_SWR_CLK", "VA_AIF2 CAP", "VA_SWR_CLK", "VA_AIF3 CAP", "VA_SWR_CLK"; | |
| qcom,ext-disp-audio-rx = <0x01>; | |
| qcom,upd_ear_pa_reg_addr = <0x300a>; | |
| qcom,msm-mbhc-gnd-swh = <0x01>; | |
| qcom,sec-mi2s-gpios = <0x675>; | |
| qcom,tdm-max-slots = <0x08>; | |
| asoc-codec = <0x519 0x521 0x664 0x673>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,cdc-dmic01-gpios = <0x670>; | |
| qcom,afe-rxtx-lb = <0x00>; | |
| asoc-codec-names = "msm-stub-codec.1", "lpass-cdc", "wcd938x_codec", "swr-haptics"; | |
| clocks = <0x518 0x00>; | |
| qcom,msm-mbhc-usbc-audio-supported = <0x00>; | |
| qcom,msm_audio_ssr_devs = <0x52c 0x520 0x521>; | |
| qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01>; | |
| qcom,msm-mi2s-master = <0x01 0x01 0x01 0x01 0x01 0x01>; | |
| qcom,model = "kalama-qrd-snd-card"; | |
| qcom,cdc-dmic45-gpios = <0x672>; | |
| compatible = "qcom,kalama-asoc-snd"; | |
| qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01>; | |
| fsa4480-i2c-handle = <0x4bc>; | |
| qcom,upd_backends_used = "wcd"; | |
| qcom,wcn-bt = <0x01>; | |
| qcom,msm-mbhc-hphl-swh = <0x01>; | |
| qcom,auxpcm-audio-intf = <0x01>; | |
| qcom,mi2s-tdm-is-hw-vote-needed = <0x01 0x01 0x01 0x01 0x01 0x01>; | |
| phandle = <0x733>; | |
| qcom,mi2s-audio-intf = <0x01>; | |
| qcom,wsa-max-devs = <0x00>; | |
| qcom,upd_lpass_reg_addr = <0x418 0x33b0300>; | |
| qcom,cdc-dmic23-gpios = <0x671>; | |
| qcom,sep-mi2s-gpios = <0x674>; | |
| }; | |
| lpi_pinctrl@6E80000 { | |
| qcom,gpios-count = <0x17>; | |
| clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; | |
| gpio-controller; | |
| qcom,lpi-slew-offset-tbl = <0x00 0x02 0x04 0x08 0x0a 0x0c 0x00 0x00 0x00 0x00 0x10 0x12 0x00 0x00 0x06 0x14 0x16 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| clocks = <0x517 0x00 0x518 0x00>; | |
| qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000>; | |
| compatible = "qcom,lpi-pinctrl"; | |
| reg = <0x6e80000 0x00>; | |
| phandle = <0x520>; | |
| #gpio-cells = <0x02>; | |
| qcom,slew-reg = <0x725a000 0x00>; | |
| lpi_tdm3_sd0 { | |
| lpi_tdm3_sd0_sleep { | |
| phandle = <0x6ec>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm3_sd0_active { | |
| phandle = <0x6ed>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd1 { | |
| quat_mi2s_sd1_sleep { | |
| phandle = <0x6ae>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd1_active { | |
| phandle = <0x6af>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd3 { | |
| quat_aux_sd3_active { | |
| phandle = <0x703>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd3_sleep { | |
| phandle = <0x702>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sck { | |
| lpi_aux1_sck_active { | |
| phandle = <0x705>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sck_sleep { | |
| phandle = <0x704>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_clk_active { | |
| phandle = <0x67e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| dmic67_clk_sleep { | |
| phandle = <0x69a>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| lpi_i2s2_sck { | |
| lpi_i2s2_sck_sleep { | |
| phandle = <0x6bc>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sck_active { | |
| phandle = <0x6bd>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_sd1 { | |
| lpi_aux3_sd1_active { | |
| phandle = <0x71b>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_sd1_sleep { | |
| phandle = <0x71a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_ws { | |
| lpi_aux2_ws_active { | |
| phandle = <0x70f>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux2_ws_sleep { | |
| phandle = <0x70e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd1 { | |
| quat_aux_sd1_active { | |
| phandle = <0x6ff>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd1_sleep { | |
| phandle = <0x6fe>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_clk_sleep { | |
| phandle = <0x681>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_ws { | |
| quat_tdm_ws_active { | |
| phandle = <0x6cf>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_ws_sleep { | |
| phandle = <0x6ce>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sd0 { | |
| lpi_aux1_sd0_active { | |
| phandle = <0x709>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sd0_sleep { | |
| phandle = <0x708>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic45_data_sleep { | |
| phandle = <0x697>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s4_ws { | |
| lpi_i2s4_ws_active { | |
| phandle = <0x6c7>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s4_ws_sleep { | |
| phandle = <0x6c6>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data1_active { | |
| phandle = <0x680>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_i2s4_sd1 { | |
| lpi_i2s4_sd1_sleep { | |
| phandle = <0x6ca>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio22"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s4_sd1_active { | |
| phandle = <0x6cb>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio22"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s1_ws { | |
| lpi_i2s1_ws_active { | |
| phandle = <0x6b7>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_ws_sleep { | |
| phandle = <0x6b6>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm4_sck { | |
| lpi_tdm4_sck_active { | |
| phandle = <0x6f1>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm4_sck_sleep { | |
| phandle = <0x6f0>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic45_data_active { | |
| phandle = <0x695>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd0 { | |
| lpi_i2s2_sd0_sleep { | |
| phandle = <0x6c0>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd0_active { | |
| phandle = <0x6c1>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_sd1 { | |
| lpi_tdm2_sd1_active { | |
| phandle = <0x6e7>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sd1_sleep { | |
| phandle = <0x6e6>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic01_clk_active { | |
| phandle = <0x68c>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| dmic01_clk_sleep { | |
| phandle = <0x68e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| lpi_tdm4_sd0 { | |
| lpi_tdm4_sd0_active { | |
| phandle = <0x6f5>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm4_sd0_sleep { | |
| phandle = <0x6f4>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data0_sleep { | |
| phandle = <0x689>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm4_ws { | |
| lpi_tdm4_ws_active { | |
| phandle = <0x6f3>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm4_ws_sleep { | |
| phandle = <0x6f2>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_sck { | |
| lpi_aux2_sck_sleep { | |
| phandle = <0x70c>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sck_active { | |
| phandle = <0x70d>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_ws { | |
| lpi_tdm1_ws_active { | |
| phandle = <0x6db>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_ws_sleep { | |
| phandle = <0x6da>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_ws { | |
| quat_aux_ws_sleep { | |
| phandle = <0x6fa>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_ws_active { | |
| phandle = <0x6fb>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s3_sck { | |
| lpi_i2s3_sck_active { | |
| phandle = <0x6a0>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s3_sck_sleep { | |
| phandle = <0x6a4>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data_active { | |
| phandle = <0x67f>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| dmic23_data_sleep { | |
| phandle = <0x693>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux4_sd1 { | |
| lpi_aux4_sd1_sleep { | |
| phandle = <0x722>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio22"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux4_sd1_active { | |
| phandle = <0x723>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio22"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s1_sd1 { | |
| lpi_i2s1_sd1_active { | |
| phandle = <0x6bb>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sd1_sleep { | |
| phandle = <0x6ba>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_sd0 { | |
| lpi_aux2_sd0_sleep { | |
| phandle = <0x710>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sd0_active { | |
| phandle = <0x711>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sck { | |
| lpi_tdm1_sck_active { | |
| phandle = <0x6d9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sck_sleep { | |
| phandle = <0x6d8>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| wsa_swr_data_pin { | |
| wsa_swr_data_active { | |
| phandle = <0x677>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| wsa_swr_data_sleep { | |
| phandle = <0x679>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data_sleep { | |
| phandle = <0x682>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd2 { | |
| quat_tdm_sd2_sleep { | |
| phandle = <0x6d4>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd2_active { | |
| phandle = <0x6d5>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sck { | |
| quat_tdm_sck_active { | |
| phandle = <0x6cd>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_sck_sleep { | |
| phandle = <0x6cc>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux4_ws { | |
| lpi_aux4_ws_sleep { | |
| phandle = <0x71e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux4_ws_active { | |
| phandle = <0x71f>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s3_sd0 { | |
| lpi_i2s3_sd0_active { | |
| phandle = <0x6a2>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s3_sd0_sleep { | |
| phandle = <0x6a6>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm3_sd1 { | |
| lpi_tdm3_sd1_active { | |
| phandle = <0x6ef>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm3_sd1_sleep { | |
| phandle = <0x6ee>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_ws { | |
| lpi_aux1_ws_active { | |
| phandle = <0x707>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_ws_sleep { | |
| phandle = <0x706>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic45_clk_sleep { | |
| phandle = <0x696>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| quat_mi2s_sd2 { | |
| quat_mi2s_sd2_sleep { | |
| phandle = <0x6b0>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd2_active { | |
| phandle = <0x6b1>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sck { | |
| quat_mi2s_sck_sleep { | |
| phandle = <0x6a8>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sck_active { | |
| phandle = <0x6a9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s3_ws { | |
| lpi_i2s3_ws_active { | |
| phandle = <0x6a1>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s3_ws_sleep { | |
| phandle = <0x6a5>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sd0 { | |
| lpi_tdm1_sd0_active { | |
| phandle = <0x6dd>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sd0_sleep { | |
| phandle = <0x6dc>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_ws { | |
| quat_mi2s_ws_sleep { | |
| phandle = <0x6aa>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_ws_active { | |
| phandle = <0x6ab>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd0 { | |
| quat_tdm_sd0_sleep { | |
| phandle = <0x6d0>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd0_active { | |
| phandle = <0x6d1>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| dmic67_clk_active { | |
| phandle = <0x698>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_sck { | |
| lpi_aux3_sck_active { | |
| phandle = <0x715>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_sck_sleep { | |
| phandle = <0x714>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data1_sleep { | |
| phandle = <0x68a>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd0 { | |
| quat_mi2s_sd0_sleep { | |
| phandle = <0x6ac>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd0_active { | |
| phandle = <0x6ad>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| dmic01_data_sleep { | |
| phandle = <0x68f>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_sd2 { | |
| quat_aux_sd2_active { | |
| phandle = <0x701>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd2_sleep { | |
| phandle = <0x700>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic23_data_active { | |
| phandle = <0x691>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_sck { | |
| quat_aux_sck_active { | |
| phandle = <0x6f9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sck_sleep { | |
| phandle = <0x6f8>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sd1 { | |
| lpi_aux1_sd1_active { | |
| phandle = <0x70b>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sd1_sleep { | |
| phandle = <0x70a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data1_sleep { | |
| phandle = <0x683>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s4_sck { | |
| lpi_i2s4_sck_sleep { | |
| phandle = <0x6c4>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s_sck_active { | |
| phandle = <0x6c5>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm3_ws { | |
| lpi_tdm3_ws_sleep { | |
| phandle = <0x6ea>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm3_ws_active { | |
| phandle = <0x6eb>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s2_sd1 { | |
| lpi_i2s2_sd1_sleep { | |
| phandle = <0x6c2>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd1_active { | |
| phandle = <0x6c3>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_sd0 { | |
| lpi_aux3_sd0_active { | |
| phandle = <0x719>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_sd0_sleep { | |
| phandle = <0x718>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_sck { | |
| lpi_tdm2_sck_active { | |
| phandle = <0x6e1>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sck_sleep { | |
| phandle = <0x6e0>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| wsa2_swr_clk_pin { | |
| wsa2_swr_clk_active { | |
| phandle = <0x67a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| wsa2_swr_clk_sleep { | |
| phandle = <0x67c>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd0 { | |
| quat_aux_sd0_active { | |
| phandle = <0x6fd>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd0_sleep { | |
| phandle = <0x6fc>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s4_sd0 { | |
| lpi_i2s4_sd0_active { | |
| phandle = <0x6c9>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s4_sd0_sleep { | |
| phandle = <0x6c8>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm4_sd1 { | |
| lpi_tdm4_sd1_active { | |
| phandle = <0x6f7>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio22"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm4_sd1_sleep { | |
| phandle = <0x6f6>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio22"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| spkr_02_sd_n { | |
| spkr_02_sd_n_active { | |
| phandle = <0x69c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| spkr_02_sd_n_sleep { | |
| phandle = <0x69d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_clk_sleep { | |
| phandle = <0x688>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_tdm2_sd0 { | |
| lpi_tdm2_sd0_active { | |
| phandle = <0x6e5>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sd0_sleep { | |
| phandle = <0x6e4>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio15"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic45_clk_active { | |
| phandle = <0x694>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| dmic67_data_active { | |
| phandle = <0x699>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| tx_swr_clk_active { | |
| phandle = <0x684>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_aux3_ws { | |
| lpi_aux3_ws_active { | |
| phandle = <0x717>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux3_ws_sleep { | |
| phandle = <0x716>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data0_active { | |
| phandle = <0x685>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| wsa_swr_clk_pin { | |
| wsa_swr_clk_active { | |
| phandle = <0x676>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| wsa_swr_clk_sleep { | |
| phandle = <0x678>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux4_sck { | |
| lpi_aux4_sck_sleep { | |
| phandle = <0x71c>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux4_sck_active { | |
| phandle = <0x71d>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio19"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s2_ws { | |
| lpi_i2s2_ws_sleep { | |
| phandle = <0x6be>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_ws_active { | |
| phandle = <0x6bf>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s1_sck { | |
| lpi_i2s1_sck_active { | |
| phandle = <0x6b5>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sck_sleep { | |
| phandle = <0x6b4>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data1_active { | |
| phandle = <0x686>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| tx_swr_data2_sleep { | |
| phandle = <0x68b>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio14"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| spkr_13_sd_n { | |
| spkr_13_sd_n_active { | |
| phandle = <0x69e>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| spkr_13_sd_n_sleep { | |
| phandle = <0x69f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_sd1 { | |
| lpi_aux2_sd1_sleep { | |
| phandle = <0x712>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sd1_active { | |
| phandle = <0x713>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| dmic23_clk_sleep { | |
| phandle = <0x692>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| wsa2_swr_data_pin { | |
| wsa2_swr_data_sleep { | |
| phandle = <0x67d>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| wsa2_swr_data_active { | |
| phandle = <0x67b>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd3 { | |
| quat_tdm_sd3_sleep { | |
| phandle = <0x6d6>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd3_active { | |
| phandle = <0x6d7>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data2_active { | |
| phandle = <0x687>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio14"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_i2s3_sd1 { | |
| lpi_i2s3_sd1_active { | |
| phandle = <0x6a3>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s3_sd1_sleep { | |
| phandle = <0x6a7>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux4_sd0 { | |
| lpi_aux4_sd0_active { | |
| phandle = <0x721>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux4_sd0_sleep { | |
| phandle = <0x720>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm3_sck { | |
| lpi_tdm3_sck_sleep { | |
| phandle = <0x6e8>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm3_sck_active { | |
| phandle = <0x6e9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| dmic67_data_sleep { | |
| phandle = <0x69b>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s1_sd0 { | |
| lpi_i2s1_sd0_active { | |
| phandle = <0x6b9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sd0_sleep { | |
| phandle = <0x6b8>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd3 { | |
| quat_mi2s_sd3_sleep { | |
| phandle = <0x6b2>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd3_active { | |
| phandle = <0x6b3>; | |
| mux { | |
| function = "func3"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sd1 { | |
| lpi_tdm1_sd1_active { | |
| phandle = <0x6df>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sd1_sleep { | |
| phandle = <0x6de>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_ws { | |
| lpi_tdm2_ws_sleep { | |
| phandle = <0x6e2>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm2_ws_active { | |
| phandle = <0x6e3>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd1 { | |
| quat_tdm_sd1_active { | |
| phandle = <0x6d3>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_sd1_sleep { | |
| phandle = <0x6d2>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic23_clk_active { | |
| phandle = <0x690>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| dmic01_data_active { | |
| phandle = <0x68d>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| sec_i2s1_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x3be 0x3c0 0x3c2>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x3bd 0x3bf 0x3c1>; | |
| phandle = <0x675>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| cdc_dmic23_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x690 0x691>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x692 0x693>; | |
| phandle = <0x671>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| sep_lpi_i2s3_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x6a0 0x6a1 0x6a2 0x6a3>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x6a4 0x6a5 0x6a6 0x6a7>; | |
| phandle = <0x674>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| wsa2_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x67a 0x67b>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x67c 0x67d>; | |
| status = "disabled"; | |
| phandle = <0x66b>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| rx_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x67e 0x67f 0x680>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x681 0x682 0x683>; | |
| phandle = <0x665>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| cdc_dmic67_pinctrl { | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x698 0x699>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x69a 0x69b>; | |
| phandle = <0x734>; | |
| #gpio-cells = <0x00>; | |
| }; | |
| }; | |
| tpda@10882000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpda-spss"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x46>; | |
| status = "disabled"; | |
| reg = <0x10882000 0x1000>; | |
| phandle = <0x41b>; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x113>; | |
| phandle = <0x111>; | |
| }; | |
| }; | |
| }; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x112>; | |
| phandle = <0x165>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10830000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-video"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10830000 0x1000>; | |
| phandle = <0x16b>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xfb>; | |
| phandle = <0x13d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| google,debug-kinfo { | |
| memory-region = <0xe9>; | |
| compatible = "google,debug-kinfo"; | |
| }; | |
| qcom,ife0@ac62000 { | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; | |
| clocks-option = <0x3b 0x43>; | |
| reg-names = "ife", "cam_camnoc"; | |
| clock-rates-option = <0x2367b880>; | |
| reg-cam-base = <0x62000 0x19000>; | |
| ife0-supply = <0x4fb>; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x25a 0x01>; | |
| clocks = <0x3b 0x45 0x3b 0x42 0x3b 0x41 0x3b 0x13>; | |
| rt-wrapper-base = <0x62000>; | |
| ubwc-static-cfg = <0x1026 0x1036>; | |
| clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; | |
| cam_hw_pid = <0x10 0x14 0x18 0x08>; | |
| compatible = "qcom,vfe780"; | |
| gdsc-supply = <0x2d9>; | |
| src-clock-name = "ife_0_clk_src"; | |
| status = "ok"; | |
| clock-names-option = "ife_dsp_clk"; | |
| interrupt-names = "ife0"; | |
| reg = <0xac62000 0xf000 0xac19000 0xa080>; | |
| regulator-names = "gdsc", "ife0"; | |
| phandle = <0x5bb>; | |
| clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; | |
| }; | |
| qcom,switch-gpio { | |
| compatible = "qcom,switch-gpio"; | |
| }; | |
| tpdm@10b0c000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-swao-prio-3"; | |
| compatible = "arm,primecell"; | |
| reg = <0x10b0c000 0x1000>; | |
| phandle = <0x40a>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf5>; | |
| phandle = <0x1c9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| wsa_core_tx_clk { | |
| qcom,codec-ext-clk-src = <0x0e>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| status = "disabled"; | |
| phandle = <0x737>; | |
| qcom,codec-lpass-clk-id = <0x314>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| qcom,gpu-coresight-cx { | |
| coresight-name = "coresight-gfx-cx"; | |
| coresight-atid = <0x34>; | |
| compatible = "qcom,gpu-coresight-cx"; | |
| phandle = <0x5dc>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5d3>; | |
| phandle = <0x5d6>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm_gsi { | |
| compatible = "qcom,msm_gsi"; | |
| }; | |
| qcom,cpufreq-hw { | |
| clock-names = "xo", "alternate"; | |
| reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; | |
| #freq-domain-cells = <0x01>; | |
| interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x13 0x04>; | |
| clocks = <0x46 0x00 0x45 0x18>; | |
| compatible = "qcom,cpufreq-epss"; | |
| interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int"; | |
| reg = <0x17d91000 0x1000 0x17d92000 0x1000 0x17d93000 0x1000>; | |
| phandle = <0x06>; | |
| }; | |
| tpdm@138b0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| atid = <0x42>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x4e>; | |
| coresight-name = "coresight-tpdm-llm-gold"; | |
| compatible = "arm,primecell"; | |
| reg = <0x138b0000 0x1000>; | |
| phandle = <0x41f>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x117>; | |
| phandle = <0x194>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@adf2294 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x5dc>; | |
| parent-supply = <0x2d8>; | |
| qcom,retain-regs; | |
| clocks = <0x45 0x06>; | |
| regulator-name = "cam_cc_ife_2_gdsc"; | |
| qcom,support-cfg-gdscr; | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| reg = <0xadf2294 0x04>; | |
| phandle = <0x4fd>; | |
| }; | |
| qcom,mdss_dsi_phy0@ae95500 { | |
| pll-label = "dsi_pll_4nm"; | |
| qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
| reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; | |
| qcom,panel-allow-phy-poweroff; | |
| cell-index = <0x00>; | |
| #clock- |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment