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June 3, 2025 00:52
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| /dts-v1/; | |
| / { | |
| model = "Qualcomm Technologies, Inc. Ravelin IDP Overlay"; | |
| #size-cells = <0x02>; | |
| qcom,msm-id = <0x28d 0x10000 0x28e 0x10000>; | |
| #address-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| compatible = "qcom,ravelin-idp\0qcom,ravelin\0qcom,idp"; | |
| qcom,board-id = <0x22 0x00>; | |
| mem-offline { | |
| offline-sizes = <0x01 0x40000000 0x00 0x40000000 0x01 0xc0000000 0x00 0x80000000 0x02 0xc0000000 0x01 0x40000000>; | |
| compatible = "qcom,mem-offline"; | |
| granule = <0x200>; | |
| mboxes = <0x02 0x00>; | |
| }; | |
| idle-states { | |
| entry-method = "psci"; | |
| gold-c3 { | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x40000003>; | |
| idle-state-name = "pc"; | |
| entry-latency-us = <0x190>; | |
| compatible = "arm,idle-state"; | |
| phandle = <0x14>; | |
| exit-latency-us = <0x60e>; | |
| min-residency-us = <0x89f>; | |
| }; | |
| gold-c4 { | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x40000004>; | |
| idle-state-name = "rail-pc"; | |
| entry-latency-us = <0x258>; | |
| compatible = "arm,idle-state"; | |
| phandle = <0x15>; | |
| exit-latency-us = <0x60e>; | |
| min-residency-us = <0x12b7>; | |
| }; | |
| silver-c4 { | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x40000004>; | |
| idle-state-name = "rail-pc"; | |
| entry-latency-us = <0x320>; | |
| compatible = "arm,idle-state"; | |
| phandle = <0x05>; | |
| exit-latency-us = <0x2ee>; | |
| min-residency-us = <0xffa>; | |
| }; | |
| cx-ret { | |
| arm,psci-suspend-param = <0x41003344>; | |
| idle-state-name = "cx-ret"; | |
| entry-latency-us = <0x619>; | |
| compatible = "domain-idle-state"; | |
| phandle = <0x12c>; | |
| exit-latency-us = <0xaf1>; | |
| min-residency-us = <0x2166>; | |
| }; | |
| cluster-d4 { | |
| arm,psci-suspend-param = <0x41000044>; | |
| idle-state-name = "l3-off"; | |
| entry-latency-us = <0x41a>; | |
| compatible = "domain-idle-state"; | |
| phandle = <0x12b>; | |
| exit-latency-us = <0x9c4>; | |
| min-residency-us = <0x14bd>; | |
| }; | |
| silver-c3 { | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x40000003>; | |
| idle-state-name = "pc"; | |
| entry-latency-us = <0x15e>; | |
| compatible = "arm,idle-state"; | |
| phandle = <0x04>; | |
| exit-latency-us = <0x384>; | |
| min-residency-us = <0x6ee>; | |
| }; | |
| }; | |
| cpus { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| cpu@200 { | |
| power-domains = <0x0c>; | |
| dynamic-power-coefficient = <0x64>; | |
| device_type = "cpu"; | |
| reg = <0x00 0x200>; | |
| enable-method = "psci"; | |
| compatible = "qcom,kryo"; | |
| next-level-cache = <0x0d>; | |
| power-domain-names = "psci"; | |
| cpu-idle-states = <0x04 0x05>; | |
| phandle = <0x1c>; | |
| #cooling-cells = <0x02>; | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x07 0x00 0x08>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x09>; | |
| phandle = <0x0d>; | |
| }; | |
| }; | |
| cpu@300 { | |
| power-domains = <0x0e>; | |
| dynamic-power-coefficient = <0x64>; | |
| device_type = "cpu"; | |
| reg = <0x00 0x300>; | |
| enable-method = "psci"; | |
| compatible = "qcom,kryo"; | |
| next-level-cache = <0x0f>; | |
| power-domain-names = "psci"; | |
| cpu-idle-states = <0x04 0x05>; | |
| phandle = <0x1d>; | |
| #cooling-cells = <0x02>; | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x07 0x00 0x08>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x09>; | |
| phandle = <0x0f>; | |
| }; | |
| }; | |
| cpu@700 { | |
| power-domains = <0x18>; | |
| dynamic-power-coefficient = <0x1e3>; | |
| device_type = "cpu"; | |
| reg = <0x00 0x700>; | |
| enable-method = "psci"; | |
| compatible = "qcom,kryo"; | |
| next-level-cache = <0x19>; | |
| power-domain-names = "psci"; | |
| cpu-idle-states = <0x14 0x15>; | |
| phandle = <0x21>; | |
| #cooling-cells = <0x02>; | |
| capacity-dmips-mhz = <0x799>; | |
| qcom,freq-domain = <0x07 0x01 0x08>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x09>; | |
| phandle = <0x19>; | |
| }; | |
| }; | |
| cpu@100 { | |
| power-domains = <0x0a>; | |
| dynamic-power-coefficient = <0x64>; | |
| device_type = "cpu"; | |
| reg = <0x00 0x100>; | |
| enable-method = "psci"; | |
| compatible = "qcom,kryo"; | |
| next-level-cache = <0x0b>; | |
| power-domain-names = "psci"; | |
| cpu-idle-states = <0x04 0x05>; | |
| phandle = <0x1b>; | |
| #cooling-cells = <0x02>; | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x07 0x00 0x08>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x09>; | |
| phandle = <0x0b>; | |
| }; | |
| }; | |
| cpu@600 { | |
| power-domains = <0x16>; | |
| dynamic-power-coefficient = <0x1e3>; | |
| device_type = "cpu"; | |
| reg = <0x00 0x600>; | |
| enable-method = "psci"; | |
| compatible = "qcom,kryo"; | |
| next-level-cache = <0x17>; | |
| power-domain-names = "psci"; | |
| cpu-idle-states = <0x14 0x15>; | |
| phandle = <0x20>; | |
| #cooling-cells = <0x02>; | |
| capacity-dmips-mhz = <0x799>; | |
| qcom,freq-domain = <0x07 0x01 0x08>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x09>; | |
| phandle = <0x17>; | |
| }; | |
| }; | |
| cpu@400 { | |
| power-domains = <0x10>; | |
| dynamic-power-coefficient = <0x64>; | |
| device_type = "cpu"; | |
| reg = <0x00 0x400>; | |
| enable-method = "psci"; | |
| compatible = "qcom,kryo"; | |
| next-level-cache = <0x11>; | |
| power-domain-names = "psci"; | |
| cpu-idle-states = <0x04 0x05>; | |
| phandle = <0x1e>; | |
| #cooling-cells = <0x02>; | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x07 0x00 0x08>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x09>; | |
| phandle = <0x11>; | |
| }; | |
| }; | |
| cpu@0 { | |
| power-domains = <0x06>; | |
| dynamic-power-coefficient = <0x64>; | |
| device_type = "cpu"; | |
| reg = <0x00 0x00>; | |
| enable-method = "psci"; | |
| compatible = "qcom,kryo"; | |
| next-level-cache = <0x08>; | |
| power-domain-names = "psci"; | |
| cpu-idle-states = <0x04 0x05>; | |
| phandle = <0x1a>; | |
| #cooling-cells = <0x02>; | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x07 0x00 0x08>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x09>; | |
| phandle = <0x08>; | |
| l3-cache { | |
| cache-level = <0x03>; | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x09>; | |
| }; | |
| }; | |
| }; | |
| cpu@500 { | |
| power-domains = <0x12>; | |
| dynamic-power-coefficient = <0x64>; | |
| device_type = "cpu"; | |
| reg = <0x00 0x500>; | |
| enable-method = "psci"; | |
| compatible = "qcom,kryo"; | |
| next-level-cache = <0x13>; | |
| power-domain-names = "psci"; | |
| cpu-idle-states = <0x04 0x05>; | |
| phandle = <0x1f>; | |
| #cooling-cells = <0x02>; | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x07 0x00 0x08>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x09>; | |
| phandle = <0x13>; | |
| }; | |
| }; | |
| cpu-map { | |
| cluster0 { | |
| core4 { | |
| cpu = <0x1e>; | |
| }; | |
| core1 { | |
| cpu = <0x1b>; | |
| }; | |
| core3 { | |
| cpu = <0x1d>; | |
| }; | |
| core2 { | |
| cpu = <0x1c>; | |
| }; | |
| core0 { | |
| cpu = <0x1a>; | |
| }; | |
| core5 { | |
| cpu = <0x1f>; | |
| }; | |
| }; | |
| cluster1 { | |
| core1 { | |
| cpu = <0x21>; | |
| }; | |
| core0 { | |
| cpu = <0x20>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| __symbols__ { | |
| VDD_LPI_CX_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-lcxlvl/regulator-pm6450-l2-level"; | |
| tpdm_spdm_out_tpda_qdss_1 = "/soc/tpdm@1000f000/out-ports/port/endpoint"; | |
| trusted_apps_mem = "/reserved-memory/trusted_apps_region@e9480000"; | |
| tpdm_shrm_out_funnel_ddr_dl0 = "/soc/tpdm@10d01000/out-ports/port/endpoint"; | |
| qupv3_se6_spi_sleep = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_sleep"; | |
| funnel_dl_south_in_tpdm_dl_south0 = "/soc/funnel@109c3000/in-ports/port@2/endpoint"; | |
| spkr_2_sd_n_sleep = "/soc/pinctrl@f000000/spkr_2_sd_n/spkr_2_sd_n_sleep"; | |
| qupv3_se4_i2c = "/soc/i2c@990000"; | |
| tpdm_swao_out_tpda_aoss_4 = "/soc/tpdm@10b0d000/out-ports/port/endpoint"; | |
| ts_spi_int_suspend = "/soc/pinctrl@f000000/pmx_ts_int_suspend/ts_spi_int_suspend"; | |
| tpdm_dlct1_out_tpda_dl_center2_27 = "/soc/tpdm@10ac1000/out-ports/port/endpoint"; | |
| va_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-0-tx"; | |
| bwmon_ddr = "/soc/qcom,bwmon-ddr@19091000"; | |
| qupv3_se3_4uart_tx_active = "/soc/pinctrl@f000000/qupv3_se3_4uart_pins/qupv3_se3_4uart_tx_active"; | |
| qupv3_se9_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_clk_active"; | |
| tpdm_swao_prio_0_out_tpda_aoss_0 = "/soc/tpdm@10b09000/out-ports/port/endpoint"; | |
| funnel_dl_lpass_out_funnel_dl_center2 = "/soc/funnel@10c3b000/out-ports/port/endpoint"; | |
| CPU_PD5 = "/soc/psci/cpu-pd5"; | |
| scmi_plh = "/soc/qcom,scmi/protocol@81"; | |
| qupv3_se0_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_scl_active"; | |
| CPU_PD2 = "/soc/psci/cpu-pd2"; | |
| dai_sec_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-sec-rx/qcom,msm-dai-q6-tdm-sec-rx-0"; | |
| ete5_out_funnel_ete = "/soc/etm5/out-ports/port/endpoint"; | |
| qupv3_se3_4uart_pins = "/soc/pinctrl@f000000/qupv3_se3_4uart_pins"; | |
| tpda_modem_1_in_tpdm_modem_1 = "/soc/tpda@10803000/in-ports/port@1/endpoint"; | |
| tpdm_shrm = "/soc/tpdm@10d01000"; | |
| stm_out_funnel_in0 = "/soc/stm@10002000/out-ports/port/endpoint"; | |
| funnel_aoss_in_tpda_aoss = "/soc/funnel@10b04000/in-ports/port@6/endpoint"; | |
| funnel_wpss_in_tpdm_wpss_1 = "/soc/funnel@10c73000/in-ports/port@1/endpoint"; | |
| qupv3_se8_spi = "/soc/spi@a8c000"; | |
| bluetooth_qca6490 = "/soc/bt_qca6490"; | |
| funnel_modem_out_funnel_in1 = "/soc/funnel@10804000/out-ports/port/endpoint"; | |
| qupv3_se4_spi = "/soc/spi@990000"; | |
| msm_gpu = "/soc/qcom,kgsl-3d0@3d00000"; | |
| qupv3_se3_4uart_sleep = "/soc/pinctrl@f000000/qupv3_se3_4uart_pins/qupv3_se3_4uart_sleep"; | |
| pm8010l_l1 = "/soc/rsc@17a00000/rpmh-regulator-ldoe1/regulator-pm8010-l1"; | |
| video_aggre_noc = "/soc/interconnect@1760000"; | |
| qupv3_se8_spi_pins = "/soc/pinctrl@f000000/qupv3_se8_spi_pins"; | |
| tpdm_tmess_0_out_tpda_tmess_1 = "/soc/tpdm@10cc0000/out-ports/port/endpoint"; | |
| cnss_wlan_en_active = "/soc/pinctrl@f000000/cnss_pins/cnss_wlan_en_active"; | |
| non_secure_display_dma_buf = "/soc/qcom,dma-heaps/qcom,display"; | |
| funnel_dl_south_in_tpdm_dl_south1 = "/soc/funnel@109c3000/in-ports/port@3/endpoint"; | |
| funnel_lpass_lpi_in_audio_etm0 = "/soc/funnel@10b44000/in-ports/port@0/endpoint"; | |
| sleep_clk = "/soc/clocks/sleep_clk"; | |
| tsens1 = "/soc/thermal-sensor@c265000"; | |
| pm8010_l6 = "/soc/rsc@17a00000/rpmh-regulator-ldoe6/regulator-pm8010-l6"; | |
| incall_record_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-rx"; | |
| cpu4_emerg = "/soc/thermal-zones/cpu-0-4/trips/cpu4-emerg-cfg"; | |
| tpda_dl_center_5_in_funnel_wpss = "/soc/tpda@10c2b000/in-ports/port@5/endpoint"; | |
| wcd_reset_sleep = "/soc/pinctrl@f000000/wcd_reset_sleep"; | |
| sdr0_lte_dsc = "/soc/qmi-tmd-devices/modem/sdr0_lte_dsc"; | |
| tpda_dl_center2_27_in_tpdm_dlct1 = "/soc/tpda@10ac3000/in-ports/port@1b/endpoint"; | |
| funnel_lpass = "/soc/funnel@10846000"; | |
| qupv3_se1_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_cs_active"; | |
| pa_nr_sdr0_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_sub1_dsc"; | |
| boot_config = "/soc/qfprom@221c8000/boot_config@600"; | |
| smp2p_wlan_2_out = "/soc/qcom,smp2p-wpss/qcom,smp2p-wlan-2-out"; | |
| sdhc2_opp_table = "/soc/sdhc2-opp-table"; | |
| funnel_dl_lpass_in_tpda_dl_lpass = "/soc/funnel@10c3b000/in-ports/port/endpoint"; | |
| L2_0 = "/cpus/cpu@0/l2-cache"; | |
| ipa_smmu_11ad = "/soc/qcom,ipa@3e00000/ipa_smmu_11ad"; | |
| gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; | |
| dai_quat_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quat-rx/qcom,msm-dai-q6-tdm-quat-rx-0"; | |
| cam_cc_bps_gdsc = "/soc/qcom,gdsc@ad10004"; | |
| tpda_dl_center = "/soc/tpda@10c2b000"; | |
| bt_sco_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-tx"; | |
| usb_audio_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-tx"; | |
| qupv3_se2_default_cts = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins/qupv3_se2_default_cts"; | |
| funnel_aoss_in_funnel_qdss = "/soc/funnel@10b04000/in-ports/port@7/endpoint"; | |
| gpu_cortex_m3 = "/soc/cti@10962000"; | |
| video_cc_mvs1_gdsc = "/soc/qcom,gdsc@aaf8244"; | |
| tpdm_gpu_out_funnel_gfx_dl = "/soc/tpdm@10900000/out-ports/port/endpoint"; | |
| afe_proxy_tx_1 = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-tx-1"; | |
| L4B = "/soc/rsc@17a00000/rpmh-regulator-ldob4/regulator-pm6450-l4"; | |
| pa_nr_sdr1_scg_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr1_scg"; | |
| sf1_vreg_mode = "/soc/rsc@17a00000/rpmh-regulator-sf1-vreg-mode/regulator-sf1-vreg-mode"; | |
| disp1_cc_mdss_core_int2_gdsc = "/soc/qcom,disp1-gdsc@1570b000"; | |
| lpass_lpi_cti = "/soc/cti@10b41000"; | |
| tpda_dl_center_6_in_funnel_wpss = "/soc/tpda@10c2b000/in-ports/port@6/endpoint"; | |
| qcom_dcvs = "/soc/qcom,dcvs"; | |
| pcie0 = "/soc/qcom,pcie@1c00000"; | |
| usb_nop_phy = "/soc/usb_nop_phy"; | |
| cam_cc_ipe_0_gdsc = "/soc/qcom,gdsc@ad11004"; | |
| qcom_qseecom = "/soc/qseecom@c1700000"; | |
| sf1_vreg_enable = "/soc/rsc@17a00000/rpmh-regulator-sf1-vreg-enable/regulator-sf1-vreg-enable"; | |
| dai_quin_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quin-rx/qcom,msm-dai-q6-tdm-quin-rx-0"; | |
| msm_dai_mi2s = "/soc/qcom,msm-dai-mi2s"; | |
| ufshc_mem = "/soc/ufshc@1d84000"; | |
| lpi_tlmm = "/soc/spf_core_platform/lpi_pinctrl@3440000"; | |
| tmc_etf_in_funnel_aoss = "/soc/tmc@10b05000/in-ports/port/endpoint"; | |
| qupv3_se5_i2c = "/soc/i2c@a80000"; | |
| qupv3_se8_spi_sleep = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_sleep"; | |
| tpdm_rdpm_out_funnel_dl_center_1 = "/soc/tpdm@10c00000/out-ports/port/endpoint"; | |
| qupv3_se8_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sda_active"; | |
| sleepstate_smp2p_in = "/soc/qcom,smp2p-adsp/qcom,sleepstate-in"; | |
| S1B_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-msslvl/regulator-pm6450-s1-level"; | |
| wsa_cdc_dma_0_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-0-rx"; | |
| tpda_dl_west_in_tpdm_sdcc2 = "/soc/tpda@10c4a000/in-ports/port@0/endpoint"; | |
| qupv3_se3_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sda_active"; | |
| dai_sec_spdif_rx = "/soc/qcom,msm-dai-q6-spdif-sec-rx"; | |
| cam_cc_ife_0_gdsc = "/soc/qcom,gdsc@ad13004"; | |
| funnel_in1_in_funnel_dl_center2 = "/soc/funnel@10042000/in-ports/port@7/endpoint"; | |
| modem_diag_out_funnel_modem_q6 = "/soc/modem_diag/out-ports/port/endpoint"; | |
| tpdm_gcc = "/soc/tpdm@1082c000"; | |
| funnel_dl_south = "/soc/funnel@109c3000"; | |
| tpdm_swao_1 = "/soc/tpdm@10b0d000"; | |
| pcie_tbu = "/soc/apps-smmu@15000000/pcie_tbu@151f9000"; | |
| cpu7_hotplug = "/soc/qcom,cpu-hotplug/cpu7-hotplug"; | |
| ddr_dl_1_cti_0 = "/soc/cti@10d0c000"; | |
| funnel_in0_in_snoc = "/soc/funnel@10041000/in-ports/port@0/endpoint"; | |
| funnel_modem_q6_dup_out_funnel_modem_q6 = "/soc/funnel@1080d000/out-ports/port/endpoint"; | |
| dump_mem = "/reserved-memory/mem_dump_region"; | |
| qupv3_se0_2uart_rx_active = "/soc/pinctrl@f000000/qupv3_se0_2uart_pins/qupv3_se0_2uart_rx_active"; | |
| gcc_pcie_2_gdsc = "/soc/qcom,pcie2-gdsc@19d004"; | |
| sdr1_nr_dsc = "/soc/qmi-tmd-devices/modem/sdr1_nr_dsc"; | |
| gpu_microcode_mem = "/reserved-memory/gpu_microcode_region@8941a000"; | |
| L26B = "/soc/rsc@17a00000/rpmh-regulator-ldob26/regulator-pm6450-l26"; | |
| spkr_1_sd_n_sleep = "/soc/pinctrl@f000000/spkr_1_sd_n/spkr_1_sd_n_sleep"; | |
| tpda_dl_center_11_in_funnel_ddr = "/soc/tpda@10c2b000/in-ports/port@c/endpoint"; | |
| sram = "/sram@17D09100"; | |
| lpass_dl_cti = "/soc/cti@10845000"; | |
| qupv3_se2_default_tx = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins/qupv3_se2_default_tx"; | |
| wcss1 = "/soc/cti@109ad000"; | |
| tmc_etr_in_replicator_etr = "/soc/tmc@10048000/in-ports/port/endpoint"; | |
| rx_cdc_dma_4_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-4-rx"; | |
| sdc1_off = "/soc/pinctrl@f000000/sdc1_off"; | |
| qupv3_se5_spi_sleep = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_sleep"; | |
| apss_cti1 = "/soc/cti@128f0000"; | |
| lpass_stm_out_funnel_lpass_lpi = "/soc/lpass_stm/out-ports/port/endpoint"; | |
| funnel_dl_center_in_tpda_dl_center = "/soc/funnel@10c2c000/in-ports/port@0/endpoint"; | |
| tpda_tmess = "/soc/tpda@10cc4000"; | |
| qupv3_se9_spi_sleep = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_sleep"; | |
| modem_nr_scg_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_scg_dsc"; | |
| trust_ui_vm_qrtr = "/reserved-memory/trust_ui_vm_qrtr@e55f3000"; | |
| CPU_PD3 = "/soc/psci/cpu-pd3"; | |
| ddrqos_dcvs_sp = "/soc/qcom,dcvs/ddrqos/sp"; | |
| qupv3_se2_rts = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins/qupv3_se2_rts"; | |
| qupv3_se0_2uart_sleep = "/soc/pinctrl@f000000/qupv3_se0_2uart_pins/qupv3_se0_2uart_sleep"; | |
| tpdm_dcc = "/soc/tpdm@10003000"; | |
| tpdm_lpass_lpi_out_funnel_lpass_lpi = "/soc/tpdm_lpass_lpi/out-ports/port/endpoint"; | |
| pa_nr_sdr1_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr1_dsc"; | |
| mccc = "/soc/syscon@190ba000"; | |
| qupv3_se5_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_sleep"; | |
| funnel_dl_center_1_out_tpda_dl_center_11 = "/soc/funnel@10c02000/out-ports/port@1/endpoint"; | |
| apps_bcm_voter = "/soc/rsc@17a00000/bcm_voter"; | |
| qupv3_se4_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_cs_active"; | |
| intc = "/soc/interrupt-controller@17200000"; | |
| funnel_modem_in_modem2_etm0 = "/soc/funnel@10804000/in-ports/port@1/endpoint"; | |
| tpdm_swao_prio_1_out_tpda_aoss_1 = "/soc/tpdm@10b0a000/out-ports/port/endpoint"; | |
| dsi_pll_codes_data = "/soc/dsi_pll_codes"; | |
| tpda_modem_out_funnel_modem = "/soc/tpda@10803000/out-ports/port/endpoint"; | |
| pm6450_l26 = "/soc/rsc@17a00000/rpmh-regulator-ldob26/regulator-pm6450-l26"; | |
| sleepstate_smp2p_out = "/soc/qcom,smp2p-adsp/sleepstate-out"; | |
| qupv3_se3_4uart_rx_active = "/soc/pinctrl@f000000/qupv3_se3_4uart_pins/qupv3_se3_4uart_rx_active"; | |
| tlmm = "/soc/pinctrl@f000000"; | |
| kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; | |
| qmp_tme = "/soc/qcom,qmp-tme"; | |
| modem_nr_scg_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_scg_sub1_dsc"; | |
| msm_audio_ion = "/soc/spf_core_platform/qcom,msm-audio-ion"; | |
| pm6450_l25 = "/soc/rsc@17a00000/rpmh-regulator-ldob25/regulator-pm6450-l25"; | |
| dcc = "/soc/dcc_v2@100ff000"; | |
| tpdm_vsense_out_tpda_dl_center_22 = "/soc/tpdm@10840000/out-ports/port/endpoint"; | |
| tpda_dl_lpass = "/soc/tpda@10c3a000"; | |
| qupv3_se2_default_rx = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins/qupv3_se2_default_rx"; | |
| L16B = "/soc/rsc@17a00000/rpmh-regulator-ldob16/regulator-pm6450-l16"; | |
| qupv3_se3_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_scl_active"; | |
| wcss2 = "/soc/cti@109Ae000"; | |
| ucsi = "/soc/qcom,pmic_glink/qcom,ucsi"; | |
| L21B = "/soc/rsc@17a00000/rpmh-regulator-ldob21/regulator-pm6450-l21"; | |
| L2_1 = "/cpus/cpu@100/l2-cache"; | |
| tpda_aoss_1_in_tpdm_swao_prio_1 = "/soc/tpda@10b08000/in-ports/port@1/endpoint"; | |
| qupv3_se7_2uart_rx_active = "/soc/pinctrl@f000000/qupv3_se7_2uart_pins/qupv3_se7_2uart_rx_active"; | |
| proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-rx"; | |
| pa_lte_sdr0_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_lte_sdr0_sub1_dsc"; | |
| qcom_tzlog = "/soc/tz-log@146AA720"; | |
| dai_mi2s0 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-prim"; | |
| tpda_dl_center2_8_in_funnel_dl_south = "/soc/tpda@10ac3000/in-ports/port@8/endpoint"; | |
| gpu_isdb_cti = "/soc/cti@10961000"; | |
| wpss_etm0_out_funnel_wpss = "/soc/wpss_etm0/out-ports/port/endpoint"; | |
| mss_q6_cti = "/soc/cti@1080b000"; | |
| qupv3_se2_4uart = "/soc/qcom,qup_uart@988000"; | |
| pm8010_l4 = "/soc/rsc@17a00000/rpmh-regulator-ldoe4/regulator-pm8010-l4"; | |
| pcie0_clkreq_default = "/soc/pinctrl@f000000/pcie0/pcie0_clkreq_default"; | |
| qupv3_se8_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_mosi_active"; | |
| tpdm_rdpm_mx = "/soc/tpdm@10c01000"; | |
| VDD_EBI_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-ebilvl/regulator-pm6450-s6-level"; | |
| tpdm_sdcc_out_tpda_dl_lpass_0 = "/soc/tpdm@10c23000/out-ports/port/endpoint"; | |
| wsa_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-0-tx"; | |
| qupv3_se5_spi_pins = "/soc/pinctrl@f000000/qupv3_se5_spi_pins"; | |
| pm8010_l5 = "/soc/rsc@17a00000/rpmh-regulator-ldoe5/regulator-pm8010-l5"; | |
| disp1_cc_mdss_core_gdsc = "/soc/qcom,disp1-gdsc@15709000"; | |
| pm6450_s9 = "/soc/rsc@17a00000/rpmh-regulator-smpb9/regulator-pm6450-s9"; | |
| trust_ui_vm_swiotlb = "/reserved-memory/trust_ui_vm_swiotlb@e5600000"; | |
| qupv3_se1_i2c_pins = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins"; | |
| tpda_dl_center2_out_funnel_dl_center2 = "/soc/tpda@10ac3000/out-ports/port/endpoint"; | |
| tpdm_pimem_out_tpda_dl_center_25 = "/soc/tpdm@10850000/out-ports/port/endpoint"; | |
| tpda_dl_center2 = "/soc/tpda@10ac3000"; | |
| dai_quin_auxpcm = "/soc/qcom,msm-quin-auxpcm"; | |
| pm8010l_l3 = "/soc/rsc@17a00000/rpmh-regulator-ldoe3/regulator-pm8010-l3"; | |
| gfx_1_tbu = "/soc/kgsl-smmu@3da0000/gfx_1_tbu@3dc9000"; | |
| funnel_dl_west_in_tpda_dl_west = "/soc/funnel@10c4b000/in-ports/port/endpoint"; | |
| GOLD_CPU_RAIL_OFF = "/idle-states/gold-c4"; | |
| tpdm_swao_prio_3_out_tpda_aoss_3 = "/soc/tpdm@10b0c000/out-ports/port/endpoint"; | |
| qseecom_mem = "/reserved-memory/qseecom_region"; | |
| tpdm_ipcc = "/soc/tpdm@10c29000"; | |
| qupv3_se2_4uart_pins = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins"; | |
| smp2p_wlan_1_out = "/soc/qcom,smp2p-wpss/qcom,smp2p-wlan-1-out"; | |
| pm6450_l24 = "/soc/rsc@17a00000/rpmh-regulator-ldob24/regulator-pm6450-l24"; | |
| ts_spi_release = "/soc/pinctrl@f000000/pmx_ts_release/ts_spi_release"; | |
| pm8010_l7 = "/soc/rsc@17a00000/rpmh-regulator-ldoe7/regulator-pm8010-l7"; | |
| L3E = "/soc/rsc@17a00000/rpmh-regulator-ldoe3/regulator-pm8010-l3"; | |
| afe_pcm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-tx"; | |
| mnoc_hf_0_tbu = "/soc/apps-smmu@15000000/mnoc_hf_0_tbu@151ed000"; | |
| cpu0_hotplug = "/soc/qcom,cpu-hotplug/cpu0-hotplug"; | |
| qupv3_se9_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_miso_active"; | |
| L17B = "/soc/rsc@17a00000/rpmh-regulator-ldob17/regulator-pm6450-l17"; | |
| dai_sec_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-sec-tx/qcom,msm-dai-q6-tdm-sec-tx-0"; | |
| dai_quat_auxpcm = "/soc/qcom,msm-quat-auxpcm"; | |
| CPU_PD6 = "/soc/psci/cpu-pd6"; | |
| tpda_dl_center_27_in_tpdm_ipcc = "/soc/tpda@10c2b000/in-ports/port@1b/endpoint"; | |
| funnel_wpss_out_tpda_dl_center_5 = "/soc/funnel@10c73000/out-ports/port@0/endpoint"; | |
| tpda_dl_center_22_in_tpdm_vsense = "/soc/tpda@10c2b000/in-ports/port@16/endpoint"; | |
| ddrss_shrm2 = "/soc/cti@10d11000"; | |
| stub_codec = "/soc/qcom,msm-stub-codec"; | |
| tpda_dl_center_24_in_tpdm_ipa = "/soc/tpda@10c2b000/in-ports/port@18/endpoint"; | |
| gpu_cc_gx_gdsc = "/soc/qcom,gdsc@3d9905c"; | |
| gcc_pcie_1_gdsc = "/soc/qcom,gdsc@19d004"; | |
| tdm_quin_tx = "/soc/qcom,msm-dai-tdm-quin-tx"; | |
| pm6450_l19 = "/soc/rsc@17a00000/rpmh-regulator-ldob19/regulator-pm6450-l19"; | |
| qfprom = "/soc/qfprom@221c8000"; | |
| va_macro = "/soc/spf_core_platform/lpass-cdc/va-macro@33F0000"; | |
| pa_nr_sdr0_scg_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_scg"; | |
| L13B = "/soc/rsc@17a00000/rpmh-regulator-ldob13/regulator-pm6450-l13"; | |
| user_contig_mem = "/reserved-memory/user_contig_region"; | |
| tpda_modem = "/soc/tpda@10803000"; | |
| tpdm_dcc_out_tpda_qdss_0 = "/soc/tpdm@10003000/out-ports/port/endpoint"; | |
| funnel_apss_in_tpda_apss = "/soc/funnel@12810000/in-ports/port@3/endpoint"; | |
| audio_gpr = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr"; | |
| bluetooth = "/soc/bt_wcn3990"; | |
| tpda_dl_center_9_in_funnel_ddr = "/soc/tpda@10c2b000/in-ports/port@9/endpoint"; | |
| tpdm_wpss_out_funnel_wpss = "/soc/tpdm@10c70000/out-ports/port/endpoint"; | |
| compr = "/soc/qcom,msm-compr-dsp"; | |
| qupv3_se4_spi_sleep = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_sleep"; | |
| aop_cmd_db_mem = "/reserved-memory/aop_cmd_db_region@80860000"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc = "/soc/qcom,gdsc@18d088"; | |
| qupv3_se3_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sleep"; | |
| CPU0 = "/cpus/cpu@0"; | |
| qupv3_se6_spi_pins = "/soc/pinctrl@f000000/qupv3_se6_spi_pins"; | |
| tpdm_dl_center2_cmb = "/soc/tpdm@10ac1000"; | |
| pm6450_l3 = "/soc/rsc@17a00000/rpmh-regulator-ldob3/regulator-pm6450-l3"; | |
| L6B = "/soc/rsc@17a00000/rpmh-regulator-ldob6/regulator-pm6450-l6"; | |
| dai_tert_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-tert-tx/qcom,msm-dai-q6-tdm-tert-tx-0"; | |
| tpdm_sdcc = "/soc/tpdm@10c20000"; | |
| tpda_aoss_4_in_tpdm_swao = "/soc/tpda@10b08000/in-ports/port@4/endpoint"; | |
| ete2_out_funnel_ete = "/soc/etm2/out-ports/port/endpoint"; | |
| L5E = "/soc/rsc@17a00000/rpmh-regulator-ldoe5/regulator-pm8010-l5"; | |
| pm6450_l11 = "/soc/rsc@17a00000/rpmh-regulator-ldob11/regulator-pm6450-l11"; | |
| scmi_pmu = "/soc/qcom,scmi/protocol@86"; | |
| cpu6_pause = "/soc/qcom,cpu-pause/cpu6-pause"; | |
| L4E = "/soc/rsc@17a00000/rpmh-regulator-ldoe4/regulator-pm8010-l4"; | |
| tpda_dl_center_26_in_tpdm_dlct = "/soc/tpda@10c2b000/in-ports/port@1a/endpoint"; | |
| dispcc = "/soc/clock-controller@af00000"; | |
| ddr_cdev = "/soc/qcom,ddr-cdev"; | |
| replicator_swao_out_eud = "/soc/replicator@10b06000/out-ports/port@1/endpoint"; | |
| smp2p_wlan_3_out = "/soc/qcom,smp2p-wpss/qcom,smp2p-wlan-3-out"; | |
| tpda_dl_center_20_in_tpdm_qm = "/soc/tpda@10c2b000/in-ports/port@14/endpoint"; | |
| tpdm_dl_south0_out_funnel_dl_south = "/soc/tpdm@109c0000/out-ports/port/endpoint"; | |
| hlos1_vote_turing_mmu_tbu0_gdsc = "/soc/qcom,gdsc@18d05c"; | |
| qupv3_se0_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sleep"; | |
| tdm_tert_tx = "/soc/qcom,msm-dai-tdm-tert-tx"; | |
| replicator_qdss_out_replicator_etr = "/soc/replicator@10046000/out-ports/port@0/endpoint"; | |
| funnel_ddr_dl0_in_tpdm_ddr_dl0 = "/soc/funnel@10d03000/in-ports/port@2/endpoint"; | |
| hdmi_dba = "/soc/qcom,msm-hdmi-dba-codec-rx"; | |
| qupv3_se4_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_mosi_active"; | |
| tdm_sec_rx = "/soc/qcom,msm-dai-tdm-sec-rx"; | |
| rx_cdc_dma_3_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-3-rx"; | |
| apss_atb_cti = "/soc/cti@12862000"; | |
| tsens0 = "/soc/thermal-sensor@c263000"; | |
| funnel_modem_q6_dup_in_modem_etm0 = "/soc/funnel@1080d000/in-ports/port@0/endpoint"; | |
| pm6450_l13 = "/soc/rsc@17a00000/rpmh-regulator-ldob13/regulator-pm6450-l13"; | |
| pcm0 = "/soc/qcom,msm-pcm"; | |
| bt_en_sleep = "/soc/pinctrl@f000000/bt_en_sleep"; | |
| funnel_lpass_lpi_out_funnel_aoss = "/soc/funnel@10b44000/out-ports/port/endpoint"; | |
| mdss_mdp = "/soc/qcom,mdss_mdp@ae00000"; | |
| CPU_PD4 = "/soc/psci/cpu-pd4"; | |
| min_temp_0_trip = "/soc/thermal-zones/zeroc-0-step/trips/cold-trip"; | |
| cpu6_emerg1 = "/soc/thermal-zones/cpu-1-1/trips/cpu6-emerg1-cfg"; | |
| smp2p_ipa_1_out = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-out"; | |
| pm6450_s5_level_ao = "/soc/rsc@17a00000/rpmh-regulator-cxlvl/regulator-pm6450-s5-level-ao"; | |
| tpdm_swao_prio_3 = "/soc/tpdm@10b0c000"; | |
| ipa_smmu_wlan = "/soc/qcom,ipa@3e00000/ipa_smmu_wlan"; | |
| VDD_LPI_MX_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-lmxlvl/regulator-pm6450-l8-level"; | |
| funnel_etm = "/soc/funnel@12800000"; | |
| rx_cdc_dma_6_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-6-rx"; | |
| qupv3_se2_tx = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins/qupv3_se2_tx"; | |
| tpdm_dlct_out_tpda_dl_center_26 = "/soc/tpdm@10c28000/out-ports/port/endpoint"; | |
| ufsphy_mem = "/soc/ufsphy_mem@1d87000"; | |
| pm6450_l22 = "/soc/rsc@17a00000/rpmh-regulator-ldob22/regulator-pm6450-l22"; | |
| lpass_cdc = "/soc/spf_core_platform/lpass-cdc"; | |
| gpi_dma1 = "/soc/qcom,gpi-dma@a00000"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = "/soc/qcom,gdsc@18d050"; | |
| gcc_pcie_0_gdsc = "/soc/qcom,gdsc@17b004"; | |
| qupv3_se2_cts = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins/qupv3_se2_cts"; | |
| funnel_in0_out_funnel_qdss = "/soc/funnel@10041000/out-ports/port/endpoint"; | |
| dai_sen_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-sen-tx/qcom,msm-dai-q6-tdm-sen-tx-0"; | |
| tdm_quat_tx = "/soc/qcom,msm-dai-tdm-quat-tx"; | |
| apss_cti2 = "/soc/cti@12900000"; | |
| pcm_noirq = "/soc/qcom,msm-pcm-dsp-noirq"; | |
| tpdm_modem_0 = "/soc/tpdm@10800000"; | |
| SILVER_CPU_RAIL_OFF = "/idle-states/silver-c4"; | |
| slimbus = "/soc/slim@3340000/ngd@1/btfmslim-driver"; | |
| disp0_cc_mdss_core_gdsc = "/soc/qcom,disp0-gdsc@af09000"; | |
| sdc1_on = "/soc/pinctrl@f000000/sdc1_on"; | |
| cpu4_pause = "/soc/qcom,cpu-pause/cpu4-pause"; | |
| tdm_sen_tx = "/soc/qcom,msm-dai-tdm-sen-tx"; | |
| ufs_phy_rx_symbol_0_clk = "/soc/clocks/ufs_phy_rx_symbol_0_clk"; | |
| qc_cti = "/soc/cti@10010000"; | |
| camcc = "/soc/clock-controller@ade0000"; | |
| dai_pri_spdif_rx = "/soc/qcom,msm-dai-q6-spdif-pri-rx"; | |
| funnel_in1_out_funnel_qdss = "/soc/funnel@10042000/out-ports/port/endpoint"; | |
| funnel_dl_west_out_funnel_in1 = "/soc/funnel@10c4b000/out-ports/port/endpoint"; | |
| funnel_tmess_in_tpda_tmess = "/soc/funnel@10cc5000/in-ports/port/endpoint"; | |
| incall_music_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-rx"; | |
| qmi_sensor = "/soc/qmi-ts-sensors"; | |
| loopback = "/soc/qcom,msm-pcm-loopback"; | |
| icnss2 = "/soc/qcom,wcn6750"; | |
| cpu1_hotplug = "/soc/qcom,cpu-hotplug/cpu1-hotplug"; | |
| cpu_6_7_pause = "/soc/qcom,cpu-pause/cpu-6-7-pause"; | |
| CLUSTER_PD = "/soc/psci/cluster-pd"; | |
| cam_cc_ife_2_gdsc = "/soc/qcom,gdsc@ad14078"; | |
| tpdm_actpm = "/soc/tpdm@12860000"; | |
| cx_pe = "/soc/cx_rdpm_pe@635000"; | |
| qupv3_se4_spi_pins = "/soc/pinctrl@f000000/qupv3_se4_spi_pins"; | |
| wlan_msa_mem = "/reserved-memory/wlan_msa_mem_region@82a00000"; | |
| mpss_mem = "/reserved-memory/mpss_region@8a000000"; | |
| cam_cc_camss_top_gdsc = "/soc/qcom,gdsc@adf4004"; | |
| L8B_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-lmxlvl/regulator-pm6450-l8-level"; | |
| funnel_ete_in_ete7 = "/soc/funnel@12800000/in-ports/port@7/endpoint"; | |
| tcsr_mutex_block = "/soc/syscon@1f40000"; | |
| tpdm_swao_prio_0 = "/soc/tpdm@10b09000"; | |
| ddr_freq_table = "/soc/ddr-freq-table"; | |
| gcc_pcie_1_phy_gdsc = "/soc/qcom,gdsc@19e000"; | |
| feat_conf13 = "/soc/qfprom@221c8000/feat_conf13@0134"; | |
| ddrqos_gold_lat = "/soc/qcom,memlat/ddrqos/gold"; | |
| cam_cc_titan_top_gdsc = "/soc/qcom,gdsc@ad15120"; | |
| pm6450_l6 = "/soc/rsc@17a00000/rpmh-regulator-ldob6/regulator-pm6450-l6"; | |
| aop_config_mem = "/reserved-memory/aop_config_region@80880000"; | |
| tpda_qdss_0_in_tpdm_dcc = "/soc/tpda@10004000/in-ports/port@0/endpoint"; | |
| aop_image_mem = "/reserved-memory/aop_image_region@80800000"; | |
| adsp_notify = "/soc/qcom,msm-adsp-notify"; | |
| qupv3_se2_default_rts = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins/qupv3_se2_default_rts"; | |
| dai_mi2s4 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quin"; | |
| dai_quat_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quat-tx/qcom,msm-dai-q6-tdm-quat-tx-0"; | |
| snoc = "/soc/snoc"; | |
| funnel_dl_west = "/soc/funnel@10c4b000"; | |
| tpdm_modem_0_out_tpda_modem_0 = "/soc/tpdm@10800000/out-ports/port/endpoint"; | |
| tpdm_swao_prio_1 = "/soc/tpdm@10b0a000"; | |
| spmi0_bus = "/soc/qcom,spmi@c42d000"; | |
| afe = "/soc/qcom,msm-pcm-afe"; | |
| tpda_apss_out_funnel_apss = "/soc/tpda@12863000/out-ports/port/endpoint"; | |
| qupv3_se8_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_clk_active"; | |
| dai_mi2s5 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-senary"; | |
| dai_mi2s1 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-sec"; | |
| usb_port0 = "/soc/ssusb@a600000/port/endpoint"; | |
| tdm_pri_rx = "/soc/qcom,msm-dai-tdm-pri-rx"; | |
| pm6450_l23 = "/soc/rsc@17a00000/rpmh-regulator-ldob23/regulator-pm6450-l23"; | |
| disp0_cc_mdss_core_int2_gdsc = "/soc/qcom,disp0-gdsc@af0b000"; | |
| funnel_dl_south_out_tpda_dl_center2_8 = "/soc/funnel@109c3000/out-ports/port@1/endpoint"; | |
| cpu7_pause = "/soc/qcom,cpu-pause/cpu7-pause"; | |
| cnoc3 = "/soc/interconnect@1510000"; | |
| ddr_dl_0_cti_0 = "/soc/cti@10d02000"; | |
| L1B = "/soc/rsc@17a00000/rpmh-regulator-ldob1/regulator-pm6450-l1"; | |
| pm6450_s5_level = "/soc/rsc@17a00000/rpmh-regulator-cxlvl/regulator-pm6450-s5-level"; | |
| tpdm_ipcc_out_tpda_dl_center_27 = "/soc/tpdm@10c29000/out-ports/port/endpoint"; | |
| qupv3_se8_i2c = "/soc/i2c@a8c000"; | |
| qupv3_se9_spi = "/soc/spi@a90000"; | |
| ipcc_mproc = "/soc/qcom,ipcc@ed18000"; | |
| cpu_pmu = "/soc/cpu-pmu"; | |
| wsa2_macro = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@31E0000"; | |
| funnel_in0_in_tpda_qdss = "/soc/funnel@10041000/in-ports/port@6/endpoint"; | |
| tpdm_modem_1 = "/soc/tpdm@10801000"; | |
| funnel_apss_in_funnel_ete = "/soc/funnel@12810000/in-ports/port@0/endpoint"; | |
| qupv3_se3_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_cs_active"; | |
| hlos1_vote_turing_mmu_tbu1_gdsc = "/soc/qcom,gdsc@18d060"; | |
| ipa_smmu_ap = "/soc/qcom,ipa@3e00000/ipa_smmu_ap"; | |
| cx_cdev = "/soc/rsc@17a00000/rpmh-regulator-cxlvl/regulator-cdev"; | |
| modem_smp2p_in = "/soc/qcom,smp2p-modem/slave-kernel"; | |
| qupv3_se9_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_scl_active"; | |
| cpu0_emerg = "/soc/thermal-zones/cpu-0-0/trips/cpu0-emerg-cfg"; | |
| pm6450_l28 = "/soc/rsc@17a00000/rpmh-regulator-ldob28/regulator-pm6450-l28"; | |
| wlan_q6_cti = "/soc/cti@10C7B000"; | |
| logbuf = "/soc/qcom,logbuf-vendor-hooks"; | |
| aliases = "/aliases"; | |
| gcc_venus_gdsc = "/soc/qcom,gdsc@1b6020"; | |
| wpss_pas = "/soc/remoteproc-wpss@8a00000"; | |
| slim_msm = "/soc/slim@3340000"; | |
| reserved_memory = "/reserved-memory"; | |
| qupv3_se0_2uart_pins = "/soc/pinctrl@f000000/qupv3_se0_2uart_pins"; | |
| tz_stat_mem = "/reserved-memory/tz_stat_region@e8800000"; | |
| tpda_aoss_3_in_tpdm_swao_prio_3 = "/soc/tpda@10b08000/in-ports/port@3/endpoint"; | |
| pm6450_s6_level = "/soc/rsc@17a00000/rpmh-regulator-ebilvl/regulator-pm6450-s6-level"; | |
| tpda_dl_west_in_tpdm_dl_west = "/soc/tpda@10c4a000/in-ports/port@10/endpoint"; | |
| qupv3_se1_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_mosi_active"; | |
| nfc_int_suspend = "/soc/pinctrl@f000000/nfc/nfc_int_suspend"; | |
| tme_crash_dump_mem = "/reserved-memory/tme_crash_dump_region@808a0000"; | |
| pcie0_rp = "/soc/qcom,pcie@1c00000/pcie0_rp"; | |
| L2_5 = "/cpus/cpu@500/l2-cache"; | |
| modem_nr_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_dsc"; | |
| tx_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-1-tx"; | |
| funnel_gfx_dl_in_tpdm_gpu = "/soc/funnel@10902000/in-ports/port/endpoint"; | |
| funnel_dlct_1 = "/soc/funnel@10c02000"; | |
| qupv3_se1_spi_pins = "/soc/pinctrl@f000000/qupv3_se1_spi_pins"; | |
| tpda_qdss_out_funnel_in0 = "/soc/tpda@10004000/out-ports/port/endpoint"; | |
| usb2_phy0 = "/soc/hsphy@88e3000"; | |
| sde_rscc = "/soc/qcom,sde_rscc@af20000"; | |
| L14B = "/soc/rsc@17a00000/rpmh-regulator-ldob14/regulator-pm6450-l14"; | |
| qupv3_se6_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sda_active"; | |
| pm6450_l8_level = "/soc/rsc@17a00000/rpmh-regulator-lmxlvl/regulator-pm6450-l8-level"; | |
| firmware = "/firmware"; | |
| mdss_dsi0 = "/soc/qcom,mdss_dsi_ctrl0@ae94000"; | |
| cpu2_hotplug = "/soc/qcom,cpu-hotplug/cpu2-hotplug"; | |
| riscv_cti = "/soc/cti@1282b000"; | |
| gpu_cc_gx_domain_addr = "/soc/syscon@3d99504"; | |
| pcm_dtmf = "/soc/qcom,msm-pcm-dtmf"; | |
| tpda_qdss_1_in_tpdm_spdm = "/soc/tpda@10004000/in-ports/port@1/endpoint"; | |
| tcsr = "/soc/syscon@1fc0000"; | |
| gpu_tj_cfg = "/soc/thermal-zones/gpuss/trips/tj_cfg"; | |
| ipa_fw_mem = "/reserved-memory/ipa_fw_region@89400000"; | |
| wpss_moselle_mem = "/reserved-memory/wpss_moselle_region@85300000"; | |
| L24B = "/soc/rsc@17a00000/rpmh-regulator-ldob24/regulator-pm6450-l24"; | |
| tpdm_modem_1_out_tpda_modem_1 = "/soc/tpdm@10801000/out-ports/port/endpoint"; | |
| usb_port0_connector = "/soc/qcom,pmic_glink/qcom,ucsi/connector/port/endpoint"; | |
| thermal_zones = "/soc/thermal-zones"; | |
| camera_mem = "/reserved-memory/camera_region@84b00000"; | |
| qtee_mem = "/reserved-memory/qtee_region@e8f80000"; | |
| qupv3_se3_4uart = "/soc/qcom,qup_uart@98c000"; | |
| qcom_ddrqos_dcvs_hw = "/soc/qcom,dcvs/ddrqos"; | |
| tpdm_tmess_0 = "/soc/tpdm@10cc0000"; | |
| adsp_smp2p_in = "/soc/qcom,smp2p-adsp/slave-kernel"; | |
| gcc_apcs_gdsc_sleep_ctrl = "/soc/syscon@162204"; | |
| tpda_tmess_1_in_tpdm_tmess_0 = "/soc/tpda@10cc4000/in-ports/port@1/endpoint"; | |
| va_md_mem = "/reserved-memory/va_md_mem_region"; | |
| ts_int_suspend = "/soc/pinctrl@f000000/pmx_ts_int_suspend/ts_int_suspend"; | |
| wpss_etm = "/soc/wpss_etm0"; | |
| lpass_core_hw_vote = "/soc/vote_lpass_core_hw"; | |
| ipcc_self_ping_adsp = "/soc/ipcc-self-ping-adsp"; | |
| cpufreq_hw = "/soc/qcom,cpufreq-hw"; | |
| tpdm_vsense = "/soc/tpdm@10840000"; | |
| pm6450_l27 = "/soc/rsc@17a00000/rpmh-regulator-ldob27/regulator-pm6450-l27"; | |
| pm6450_l14 = "/soc/rsc@17a00000/rpmh-regulator-ldob14/regulator-pm6450-l14"; | |
| cpu7_emerg1 = "/soc/thermal-zones/cpu-1-3/trips/cpu7-emerg1-cfg"; | |
| qupv3_se0_2uart_tx_active = "/soc/pinctrl@f000000/qupv3_se0_2uart_pins/qupv3_se0_2uart_tx_active"; | |
| Sierra_A6 = "/soc/cti@10C13000"; | |
| qupv3_se8_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_scl_active"; | |
| rx_cdc_dma_7_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-7-rx"; | |
| funnel_ete_in_ete0 = "/soc/funnel@12800000/in-ports/port@0/endpoint"; | |
| L7B = "/soc/rsc@17a00000/rpmh-regulator-ldob7/regulator-pm6450-l7"; | |
| tpda_apss = "/soc/tpda@12863000"; | |
| disp_bcm_voter = "/soc/rsc@af20000/bcm_voter"; | |
| tmc_etf = "/soc/tmc@10b05000"; | |
| trust_ui_vm_mem = "/reserved-memory/trust_ui_vm_region@e0b00000"; | |
| qupv3_se6_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_cs_active"; | |
| usb3phy_portselect_default = "/soc/pinctrl@f000000/usb_phy_ps/usb3phy_portselect_default"; | |
| tpda_apss_0_in_tpdm_llm_silver = "/soc/tpda@12863000/in-ports/port@0/endpoint"; | |
| funnel_modem_in_funnel_modem_q6 = "/soc/funnel@10804000/in-ports/port@3/endpoint"; | |
| tpdm_wcss_out_funnel_dl_south = "/soc/tpdm@109A4000/out-ports/port/endpoint"; | |
| dai_quin_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quin-tx/qcom,msm-dai-q6-tdm-quin-tx-0"; | |
| loopback1 = "/soc/qcom,msm-pcm-loopback-low-latency"; | |
| dai_tert_auxpcm = "/soc/qcom,msm-tert-auxpcm"; | |
| CPU7 = "/cpus/cpu@700"; | |
| nfc_enable_suspend = "/soc/pinctrl@f000000/nfc/nfc_enable_suspend"; | |
| qupv3_se6_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sleep"; | |
| adsp_mem_heap = "/reserved-memory/adsp_heap_region"; | |
| dai_dp1 = "/soc/qcom,msm-dai-q6-dp1"; | |
| L9B = "/soc/rsc@17a00000/rpmh-regulator-ldob9/regulator-pm6450-l9"; | |
| csr = "/soc/csr@10001000"; | |
| L2_7 = "/cpus/cpu@700/l2-cache"; | |
| pm6450_s8 = "/soc/rsc@17a00000/rpmh-regulator-smpb8/regulator-pm6450-s8"; | |
| qupv3_se4_i2c_pins = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins"; | |
| tpdm_lpass = "/soc/tpdm@10844000"; | |
| qupv3_se2_rx = "/soc/pinctrl@f000000/qupv3_se2_4uart_pins/qupv3_se2_rx"; | |
| mdss_dsi_phy0 = "/soc/qcom,mdss_dsi_phy0@ae94900"; | |
| tpdm_dl_west_out_tpda_dl_west = "/soc/tpdm@10C48000/out-ports/port/endpoint"; | |
| funnel_wpss_out_funnel_dl_center = "/soc/funnel@10c73000/out-ports/port@2/endpoint"; | |
| video_cc_mvs1c_gdsc = "/soc/qcom,gdsc@aaf8124"; | |
| swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@3200000/rx_swr_master"; | |
| sb_7_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-rx"; | |
| L19B = "/soc/rsc@17a00000/rpmh-regulator-ldob19/regulator-pm6450-l19"; | |
| soc = "/soc"; | |
| south_cti = "/soc/cti@109C2000"; | |
| modem_pas = "/soc/remoteproc-mss@04080000"; | |
| tpda_dl_center_11_in_funnel_dl_center_1 = "/soc/tpda@10ac3000/in-ports/port@e/endpoint"; | |
| lpass_q6_cti = "/soc/cti@10b4b000"; | |
| funnel_apss = "/soc/funnel@12810000"; | |
| replicator_swao = "/soc/replicator@10b06000"; | |
| turing_dl_cti_0 = "/soc/cti@10982000"; | |
| apps_smmu = "/soc/apps-smmu@15000000"; | |
| L6E = "/soc/rsc@17a00000/rpmh-regulator-ldoe6/regulator-pm8010-l6"; | |
| tdm_sen_rx = "/soc/qcom,msm-dai-tdm-sen-rx"; | |
| L2_4 = "/cpus/cpu@400/l2-cache"; | |
| qupv3_se5_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_mosi_active"; | |
| pcie_anoc = "/soc/interconnect@16C0000"; | |
| L20B = "/soc/rsc@17a00000/rpmh-regulator-ldob20/regulator-pm6450-l20"; | |
| pm6450_l16 = "/soc/rsc@17a00000/rpmh-regulator-ldob16/regulator-pm6450-l16"; | |
| rimps = "/soc/qcom,rimps@17400000"; | |
| qupv3_se1_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sda_active"; | |
| cpu2_pause = "/soc/qcom,cpu-pause/cpu2-pause"; | |
| dai_tert_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-tert-rx/qcom,msm-dai-q6-tdm-tert-rx-0"; | |
| routing = "/soc/qcom,msm-pcm-routing"; | |
| funnel_tmess_out_funnel_in0 = "/soc/funnel@10cc5000/out-ports/port/endpoint"; | |
| usb_qmp_dp_phy = "/soc/ssphy@88e8000"; | |
| tdm_quat_rx = "/soc/qcom,msm-dai-tdm-quat-rx"; | |
| gcc_apcs_gdsc_vote_ctrl = "/soc/syscon@162128"; | |
| funnel_ete_in_ete5 = "/soc/funnel@12800000/in-ports/port@5/endpoint"; | |
| tmc_etr1 = "/soc/tmc@1004f000"; | |
| pm6450_l17 = "/soc/rsc@17a00000/rpmh-regulator-ldob17/regulator-pm6450-l17"; | |
| funnel_aoss_in_funnel_lpass_lpi = "/soc/funnel@10b04000/in-ports/port@5/endpoint"; | |
| cx_pe_config1 = "/soc/thermal-zones/cx-pe/trips/cx-pe-config1"; | |
| S5B_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-cxlvl/regulator-pm6450-s5-level"; | |
| tags_mem = "/reserved-memory/tags_region@e8900000"; | |
| qupv3_se1_spi = "/soc/spi@984000"; | |
| aggre1_noc = "/soc/interconnect@16e0000"; | |
| funnel_in1_in_funnel_dl_center = "/soc/funnel@10042000/in-ports/port@6/endpoint"; | |
| qupv3_se3_i2c = "/soc/i2c@98c000"; | |
| xbl_sc_mem = "/reserved-memory/xbl_sc_region@a6e00000"; | |
| funnel_dlct0 = "/soc/funnel@10c2c000"; | |
| funnel_wpss_in_wpss_etm0 = "/soc/funnel@10c73000/in-ports/port@2/endpoint"; | |
| pdc = "/soc/interrupt-controller@b220000"; | |
| modem_lte_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_lte_sub1_dsc"; | |
| tpdm_lpass_lpi = "/soc/tpdm_lpass_lpi"; | |
| tpdm_dl_lpass = "/soc/tpdm@10c38000"; | |
| turing_q6_cti = "/soc/cti@1098b000"; | |
| spmi_tgu1 = "/soc/tgu@10b10000"; | |
| msm_vidc = "/soc/qcom,vidc@aa00000"; | |
| tpdm_ddr_dl0_out_funnel_ddr_dl0 = "/soc/tpdm@10d00000/out-ports/port/endpoint"; | |
| VDD_CX_LEVEL_AO = "/soc/rsc@17a00000/rpmh-regulator-cxlvl/regulator-pm6450-s5-level-ao"; | |
| non_secure_display_memory = "/reserved-memory/non_secure_display_region"; | |
| CPU4 = "/cpus/cpu@400"; | |
| L5B = "/soc/rsc@17a00000/rpmh-regulator-ldob5/regulator-pm6450-l5"; | |
| dai_mi2s3 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quat"; | |
| replicator_swao_in_tmc_etf = "/soc/replicator@10b06000/in-ports/port/endpoint"; | |
| tpdm_qm = "/soc/tpdm@109d0000"; | |
| xbl_dtlog_mem = "/reserved-memory/xbl_dtlog_region@80600000"; | |
| rx_cdc_dma_2_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-2-rx"; | |
| mmss_noc = "/soc/interconnect@1740000"; | |
| funnel_qdss_out_funnel_aoss = "/soc/funnel@10045000/out-ports/port/endpoint"; | |
| pa_nr_sdr0_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_dsc"; | |
| funnel_dl_center_1_in_tpdm_rdpm = "/soc/funnel@10c02000/in-ports/port@1/endpoint"; | |
| rx_cdc_dma_0_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-0-rx"; | |
| pm6450_l20 = "/soc/rsc@17a00000/rpmh-regulator-ldob20/regulator-pm6450-l20"; | |
| tpdm_dlct0_out_tpda_dl_center2_26 = "/soc/tpdm@10ac0000/out-ports/port/endpoint"; | |
| funnel_ddr_ch01 = "/soc/funnel@10d22000"; | |
| lpass_tbu = "/soc/apps-smmu@15000000/lpass_tbu@151f5000"; | |
| slimbam = "/soc/bamdma@3304000"; | |
| qcom_memlat = "/soc/qcom,memlat"; | |
| qupv3_se5_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_clk_active"; | |
| L23B = "/soc/rsc@17a00000/rpmh-regulator-ldob23/regulator-pm6450-l23"; | |
| L10B = "/soc/rsc@17a00000/rpmh-regulator-ldob10/regulator-pm6450-l10"; | |
| qupv3_se0_2uart = "/soc/qcom,qup_uart@980000"; | |
| funnel_ddr_out_tpda_dl_center_11 = "/soc/funnel@10d03000/out-ports/port@1/endpoint"; | |
| clk_virt = "/soc/interconnect@0"; | |
| ipa_hw = "/soc/qcom,ipa@3e00000"; | |
| CPU5 = "/cpus/cpu@500"; | |
| pa_lte_sdr1_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_lte_sdr1_sub1_dsc"; | |
| memtimer = "/soc/timer@17420000"; | |
| L27B = "/soc/rsc@17a00000/rpmh-regulator-ldob27/regulator-pm6450-l27"; | |
| modem_vdd = "/soc/qmi-tmd-devices/modem/modem_vdd"; | |
| feat_conf12 = "/soc/qfprom@221c8000/feat_conf12@0130"; | |
| snoc_out_funnel_in0 = "/soc/snoc/out-ports/port/endpoint"; | |
| qupv3_se7_2uart_sleep = "/soc/pinctrl@f000000/qupv3_se7_2uart_pins/qupv3_se7_2uart_sleep"; | |
| ete3_out_funnel_ete = "/soc/etm3/out-ports/port/endpoint"; | |
| tx_cdc_dma_5_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-5-tx"; | |
| tpdm_tmess_prng = "/soc/tpdm@10cc9000"; | |
| qupv3_se5_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_scl_active"; | |
| funnel_dl_center_out_funnel_in1 = "/soc/funnel@10c2c000/out-ports/port/endpoint"; | |
| VDD_MODEM_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-msslvl/regulator-pm6450-s1-level"; | |
| smp2p_wlan_1_in = "/soc/qcom,smp2p-wpss/qcom,smp2p-wlan-1-in"; | |
| ddr_dcvs_sp = "/soc/qcom,dcvs/ddr/sp"; | |
| ts_spi_active = "/soc/pinctrl@f000000/pmx_ts_active/ts_spi_active"; | |
| L2B_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-lcxlvl/regulator-pm6450-l2-level"; | |
| anoc_1_tbu = "/soc/apps-smmu@15000000/anoc_1_tbu@151e5000"; | |
| funnel_lpass_lpi = "/soc/funnel@10b44000"; | |
| qupv3_se6_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_clk_active"; | |
| tmc_etf_out_replicator_swao = "/soc/tmc@10b05000/out-ports/port/endpoint"; | |
| qmi_wlan = "/soc/qmi-tmd-devices/modem/wlan"; | |
| funnel_ddr_dl0_in_funnel_ddr_ch01 = "/soc/funnel@10d03000/in-ports/port@0/endpoint"; | |
| SILVER_CPU_OFF = "/idle-states/silver-c3"; | |
| funnel_dl_center2_in_funnel_dl_south = "/soc/funnel@10ac4000/in-ports/port@4/endpoint"; | |
| cpu3_pause = "/soc/qcom,cpu-pause/cpu3-pause"; | |
| ts_reset_suspend = "/soc/pinctrl@f000000/pmx_ts_reset_suspend/ts_reset_suspend"; | |
| funnel_modem_q6 = "/soc/funnel@1080c000"; | |
| qmp_aop = "/soc/qcom,qmp-aop"; | |
| tpda_aoss = "/soc/tpda@10b08000"; | |
| sdr1_lte_dsc = "/soc/qmi-tmd-devices/modem/sdr1_lte_dsc"; | |
| ipa_gsi_mem = "/reserved-memory/ipa_gsi_region@89410000"; | |
| tpda_apss_3_in_tpdm_apss0 = "/soc/tpda@12863000/in-ports/port@3/endpoint"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc = "/soc/qcom,gdsc@18d08c"; | |
| gcc_usb30_prim_gdsc = "/soc/qcom,gdsc@149004"; | |
| funnel_ddr_dl0_in_tpdm_shrm = "/soc/funnel@10d03000/in-ports/port@3/endpoint"; | |
| dai_pri_auxpcm = "/soc/qcom,msm-pri-auxpcm"; | |
| pm6450_l10 = "/soc/rsc@17a00000/rpmh-regulator-ldob10/regulator-pm6450-l10"; | |
| wdog = "/soc/qcom,wdt@17410000"; | |
| qupv3_se1_spi_sleep = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_sleep"; | |
| qupv3_se9_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sleep"; | |
| tpdm_apss = "/soc/tpdm@12861000"; | |
| tx_cdc_dma_3_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-3-tx"; | |
| swao_csr = "/soc/csr@10b11000"; | |
| mnoc_hf_1_tbu = "/soc/apps-smmu@15000000/mnoc_hf_1_tbu@151f1000"; | |
| spf_core_platform = "/soc/spf_core_platform"; | |
| cpu6_hotplug = "/soc/qcom,cpu-hotplug/cpu6-hotplug"; | |
| funnel_in1 = "/soc/funnel@10042000"; | |
| disp_cc_mdss_core_int2_gdsc = "/soc/qcom,gdsc@af0b000"; | |
| cpucp_fw_mem = "/reserved-memory/cpucp_fw_region@80b00000"; | |
| dai_pri_spdif_tx = "/soc/qcom,msm-dai-q6-spdif-pri-tx"; | |
| voice = "/soc/qcom,msm-pcm-voice"; | |
| funnel_dl_center_1_in_tpdm_rdpm_mx = "/soc/funnel@10c02000/in-ports/port@2/endpoint"; | |
| compress = "/soc/qcom,msm-compress-dsp"; | |
| ts_release = "/soc/pinctrl@f000000/pmx_ts_release/ts_release"; | |
| proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-tx"; | |
| qupv3_se5_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_cs_active"; | |
| chipinfo_mem = "/reserved-memory/chipinfo_region@808f4000"; | |
| tpdm_gpu = "/soc/tpdm@10900000"; | |
| ete1_out_funnel_ete = "/soc/etm1/out-ports/port/endpoint"; | |
| gpucc = "/soc/clock-controller@3d90000"; | |
| afe_proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-tx"; | |
| qupv3_se4_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sleep"; | |
| qupv3_se8_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_miso_active"; | |
| smp2p_rdbg2_in = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-in"; | |
| smp2p_ipa_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-in"; | |
| tpda_tmess_2_in_tpdm_tmess_1 = "/soc/tpda@10cc4000/in-ports/port@2/endpoint"; | |
| tpdm_llm_silver = "/soc/tpdm@128a0000"; | |
| min_temp_1_trip = "/soc/thermal-zones/zeroc-1-step/trips/cold-trip"; | |
| dai_pri_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-pri-tx/qcom,msm-dai-q6-tdm-pri-tx-0"; | |
| CPU_PD1 = "/soc/psci/cpu-pd1"; | |
| cpu3_hotplug = "/soc/qcom,cpu-hotplug/cpu3-hotplug"; | |
| qupv3_se3_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_mosi_active"; | |
| modem_nr_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_sub1_dsc"; | |
| mem_client_3_size = "/soc/qcom,memshare/qcom,client_3"; | |
| funnel_tmess = "/soc/funnel@10cc5000"; | |
| eud = "/soc/qcom,msm-eud@88e0000"; | |
| qupv3_se4_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_scl_active"; | |
| dai_sec_spdif_tx = "/soc/qcom,msm-dai-q6-spdif-sec-tx"; | |
| funnel_ete_in_ete1 = "/soc/funnel@12800000/in-ports/port@1/endpoint"; | |
| display_fps = "/soc/qcom,userspace-cdev/display-fps"; | |
| rpmhcc = "/soc/rsc@17a00000/qcom,rpmhclk"; | |
| thermal_ddr_freq_table = "/soc/thermal-ddr-freq-table"; | |
| tpda_aoss_out_funnel_aoss = "/soc/tpda@10b08000/out-ports/port/endpoint"; | |
| cam_cc_ife_1_gdsc = "/soc/qcom,gdsc@ad14004"; | |
| funnel_ete_in_ete4 = "/soc/funnel@12800000/in-ports/port@4/endpoint"; | |
| uefi_log_mem = "/reserved-memory/uefi_log_region@808e4000"; | |
| tpda_aoss_0_in_tpdm_swao_prio_0 = "/soc/tpda@10b08000/in-ports/port@0/endpoint"; | |
| funnel_dl_center2_in_tpda_dl_center2 = "/soc/funnel@10ac4000/in-ports/port@0/endpoint"; | |
| funnel_dl_center_in_funnel_apss = "/soc/funnel@10c2c000/in-ports/port@7/endpoint"; | |
| cnoc2 = "/soc/interconnect@1500000"; | |
| qupv3_se8_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_cs_active"; | |
| gcc_pcie_0_phy_gdsc = "/soc/qcom,gdsc@17c000"; | |
| kgsl_smmu = "/soc/kgsl-smmu@3da0000"; | |
| replicator_swao_out_replicator_qdss = "/soc/replicator@10b06000/out-ports/port@0/endpoint"; | |
| scmi_cpufreqstat = "/soc/qcom,scmi/protocol@84"; | |
| aoss_qmp = "/soc/power-controller@c300000"; | |
| dai_sen_auxpcm = "/soc/qcom,msm-sen-auxpcm"; | |
| usb_phy_ps = "/soc/pinctrl@f000000/usb_phy_ps"; | |
| wpss_smp2p_out = "/soc/qcom,smp2p-wpss/master-kernel"; | |
| funnel_in0 = "/soc/funnel@10041000"; | |
| spkr_1_sd_n_active = "/soc/pinctrl@f000000/spkr_1_sd_n/spkr_1_sd_n_active"; | |
| sdr0_nr_dsc = "/soc/qmi-tmd-devices/modem/sdr0_nr_dsc"; | |
| pcie0_wake_default = "/soc/pinctrl@f000000/pcie0/pcie0_wake_default"; | |
| qupv3_se0_i2c_pins = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins"; | |
| qcom_l3_dcvs_hw = "/soc/qcom,dcvs/l3"; | |
| xo_board = "/soc/clocks/xo_board"; | |
| int_fm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-rx"; | |
| adsp_loader = "/soc/qcom,msm-adsp-loader"; | |
| dai_sen_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-sen-rx/qcom,msm-dai-q6-tdm-sen-rx-0"; | |
| smmu_sde_unsec = "/soc/qcom,smmu_sde_unsec_cb"; | |
| funnel_merg = "/soc/funnel@10045000"; | |
| gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; | |
| tcsr_mutex = "/soc/hwlock"; | |
| tpdm_dl_south1 = "/soc/tpdm@109c1000"; | |
| CPU_PD0 = "/soc/psci/cpu-pd0"; | |
| funnel_ddr_ch01_out_funnel_ddr_dl0 = "/soc/funnel@10d22000/out-ports/port/endpoint"; | |
| dummy_eud = "/soc/dummy_sink"; | |
| rx_cdc_dma_1_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-1-rx"; | |
| funnel_lpass_lpi_in_tpdm_lpass_lpi = "/soc/funnel@10b44000/in-ports/port@5/endpoint"; | |
| lpass_audio_hw_vote = "/soc/vote_lpass_audio_hw"; | |
| wpss_smp2p_in = "/soc/qcom,smp2p-wpss/slave-kernel"; | |
| hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = "/soc/qcom,gdsc@18d054"; | |
| tpda_dl_center_10_in_funnel_dl_center_1 = "/soc/tpda@10ac3000/in-ports/port@d/endpoint"; | |
| pcie0_clkreq_sleep = "/soc/pinctrl@f000000/pcie0/pcie0_clkreq_sleep"; | |
| arch_timer = "/soc/timer"; | |
| wsa_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-1-tx"; | |
| tpdm_wpss_1_out_funnel_wpss = "/soc/tpdm@10c71000/out-ports/port/endpoint"; | |
| funnel_dl_center2_out_funnel_in1 = "/soc/funnel@10ac4000/out-ports/port/endpoint"; | |
| gpu_cc_gx_sw_reset = "/soc/syscon@3d99058"; | |
| tpdm_tmess_prng_out_tpda_tmess_0 = "/soc/tpdm@10cc9000/out-ports/port/endpoint"; | |
| qupv3_se4_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sda_active"; | |
| fsa4480 = "/soc/i2c@a8c000/fsa4480@42"; | |
| funnel_qdss_in_funnel_in0 = "/soc/funnel@10045000/in-ports/port@0/endpoint"; | |
| qupv3_se8_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sleep"; | |
| icnss_cdev_wpss = "/soc/qcom,wcn6750/qcom,icnss_cdev2"; | |
| pm6450_l5 = "/soc/rsc@17a00000/rpmh-regulator-ldob5/regulator-pm6450-l5"; | |
| usb3_phy_wrapper_gcc_usb30_pipe_clk = "/soc/clocks/usb3_phy_wrapper_gcc_usb30_pipe_clk"; | |
| tpdm_emmc = "/soc/tpdm@10c23000"; | |
| funnel_lpass_out_tpda_dl_lpass_2 = "/soc/funnel@10846000/out-ports/port/endpoint"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = "/soc/qcom,gdsc@18d058"; | |
| ete4_out_funnel_ete = "/soc/etm4/out-ports/port/endpoint"; | |
| funnel_dl_south_out_funnel_dl_center2 = "/soc/funnel@109c3000/out-ports/port@2/endpoint"; | |
| L2_3 = "/cpus/cpu@300/l2-cache"; | |
| tpda_tmess_0_in_tpdm_tmess_prng = "/soc/tpda@10cc4000/in-ports/port@0/endpoint"; | |
| tpdm_prng_out_tpda_dl_center_19 = "/soc/tpdm@10841000/out-ports/port/endpoint"; | |
| qupv3_se5_spi = "/soc/spi@a80000"; | |
| tmess_cti_0 = "/soc/cti@10cc2000"; | |
| S8B = "/soc/rsc@17a00000/rpmh-regulator-smpb8/regulator-pm6450-s8"; | |
| qupv3_se1_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_clk_active"; | |
| L3B = "/soc/rsc@17a00000/rpmh-regulator-ldob3/regulator-pm6450-l3"; | |
| qupv3_se1_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_miso_active"; | |
| smp2p_wlan_2_in = "/soc/qcom,smp2p-wpss/qcom,smp2p-wlan-2-in"; | |
| cnss_pci0 = "/soc/qcom,pcie@1c00000/pcie0_rp/cnss_pci0"; | |
| tpda_dl_center_12_in_funnel_ddr = "/soc/tpda@10c2b000/in-ports/port@d/endpoint"; | |
| pcie0_perst_default = "/soc/pinctrl@f000000/pcie0/pcie0_perst_default"; | |
| tpda_dl_lpass_out_funnel_dl_lpass = "/soc/tpda@10c3a000/out-ports/port/endpoint"; | |
| qupv3_se6_i2c = "/soc/i2c@a84000"; | |
| funnel_ddr_dl0 = "/soc/funnel@10d03000"; | |
| gem_noc = "/soc/interconnect@19100000"; | |
| rimps_log = "/soc/qcom,rimps_log@17d09c00"; | |
| gpu_cc_gx_acd_iroot_reset = "/soc/syscon@3d9958c"; | |
| funnel_wpss = "/soc/funnel@10c73000"; | |
| ete6_out_funnel_ete = "/soc/etm6/out-ports/port/endpoint"; | |
| qcom_cedev = "/soc/qcedev@1de0000"; | |
| anoc_2_tbu = "/soc/apps-smmu@15000000/anoc_2_tbu@151e9000"; | |
| ts_spi_reset_suspend = "/soc/pinctrl@f000000/pmx_ts_reset_suspend/ts_spi_reset_suspend"; | |
| qupv3_se8_i2c_pins = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins"; | |
| usb_audio_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-rx"; | |
| funnel_qdss_in_funnel_in1 = "/soc/funnel@10045000/in-ports/port@1/endpoint"; | |
| usb0 = "/soc/ssusb@a600000"; | |
| smp2p_rdbg2_out = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-out"; | |
| scmi = "/soc/qcom,scmi"; | |
| video_cc_mvsc_gdsc = "/soc/qcom,gdsc@aaf5004"; | |
| L3_0 = "/cpus/cpu@0/l2-cache/l3-cache"; | |
| chosen = "/chosen"; | |
| funnel_dl_center2_in_funnel_dl_lpass = "/soc/funnel@10ac4000/in-ports/port@6/endpoint"; | |
| qupv3_se5_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_miso_active"; | |
| glink_edge = "/soc/remoteproc-adsp@03000000/glink-edge"; | |
| L2_2 = "/cpus/cpu@200/l2-cache"; | |
| tpdm_llm_silver_out_tpda_apss_0 = "/soc/tpdm@128a0000/out-ports/port/endpoint"; | |
| sdhc_2 = "/soc/sdhci@8804000"; | |
| pm6450_l9 = "/soc/rsc@17a00000/rpmh-regulator-ldob9/regulator-pm6450-l9"; | |
| audio_etm0_out_funnel_lpass_lpi = "/soc/audio_etm0/out-ports/port/endpoint"; | |
| funnel_in0_in_funnel_tmess = "/soc/funnel@10041000/in-ports/port@1/endpoint"; | |
| pm6450_l4 = "/soc/rsc@17a00000/rpmh-regulator-ldob4/regulator-pm6450-l4"; | |
| qupv3_se4_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_miso_active"; | |
| pm6450_l2_level = "/soc/rsc@17a00000/rpmh-regulator-lcxlvl/regulator-pm6450-l2-level"; | |
| tpda_dl_lpass_2_in_funnel_lpass = "/soc/tpda@10c3a000/in-ports/port@2/endpoint"; | |
| funnel_in1_in_funnel_modem = "/soc/funnel@10042000/in-ports/port@4/endpoint"; | |
| cortex_m3 = "/soc/cti@10b13000"; | |
| L28B_PBS = "/soc/rsc@17a00000/rpmh-regulator-vrmpx2/regulator-pm6450-l28-pbs"; | |
| pm6450_l24_pbs = "/soc/rsc@17a00000/rpmh-regulator-vrmsd/regulator-pm6450-l24-pbs"; | |
| qupv3_se6_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_scl_active"; | |
| replicator_qdss_in_replicator_swao = "/soc/replicator@10046000/in-ports/port/endpoint"; | |
| funnel_ete_in_ete2 = "/soc/funnel@12800000/in-ports/port@2/endpoint"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc = "/soc/qcom,gdsc@18d078"; | |
| tpdm_sdcc2_out_tpda_dl_west = "/soc/tpdm@10c20000/out-ports/port/endpoint"; | |
| voip = "/soc/qcom,msm-voip-dsp"; | |
| qupv3_se6_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_miso_active"; | |
| incall_record_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-tx"; | |
| cpu5_hotplug = "/soc/qcom,cpu-hotplug/cpu5-hotplug"; | |
| funnel_gfx_dl = "/soc/funnel@10902000"; | |
| tpdm_tmess_1_out_tpda_tmess_2 = "/soc/tpdm@10cc1000/out-ports/port/endpoint"; | |
| funnel_gfx_out_tpda_dl_center2_17 = "/soc/funnel@10902000/out-ports/port/endpoint"; | |
| qupv3_se3_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_miso_active"; | |
| funnel_aoss = "/soc/funnel@10b04000"; | |
| hyp_core_ctl = "/soc/qcom,hyp-core-ctl"; | |
| VDD_CX_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-cxlvl/regulator-pm6450-s5-level"; | |
| ete0_out_funnel_ete = "/soc/etm0/out-ports/port/endpoint"; | |
| replicator_qdss = "/soc/replicator@10046000"; | |
| sdc2_off = "/soc/pinctrl@f000000/sdc2_off"; | |
| tx_cdc_dma_4_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-4-tx"; | |
| qupv3_1 = "/soc/qcom,qupv3_1_geni_se@ac0000"; | |
| tpdm_ddr_ch01_out_funnel_ddr_ch01 = "/soc/tpdm@10d20000/out-ports/port/endpoint"; | |
| tpdm_dl_west = "/soc/tpdm@10C48000"; | |
| icnss_cdev_apss = "/soc/qcom,wcn6750/qcom,icnss_cdev1"; | |
| modem_smp2p_out = "/soc/qcom,smp2p-modem/master-kernel"; | |
| ddr_config0 = "/soc/thermal-zones/ddr/trips/ddr0-config"; | |
| mc_virt = "/soc/interconnect@1"; | |
| bluetooth_wcn6750 = "/soc/bt_wcn6750"; | |
| adsp_smp2p_out = "/soc/qcom,smp2p-adsp/master-kernel"; | |
| funnel_ete_out_funnel_apss = "/soc/funnel@12800000/out-ports/port/endpoint"; | |
| cnss_wlan_en_sleep = "/soc/pinctrl@f000000/cnss_pins/cnss_wlan_en_sleep"; | |
| funnel_modem_q6_in_modem_diag = "/soc/funnel@1080c000/in-ports/port@2/endpoint"; | |
| tpdm_gcc_out_tpda_dl_center_21 = "/soc/tpdm@1082c000/out-ports/port/endpoint"; | |
| qupv3_se6_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_mosi_active"; | |
| cpu1_pause = "/soc/qcom,cpu-pause/cpu1-pause"; | |
| gpi_dma0 = "/soc/qcom,gpi-dma@900000"; | |
| funnel_aoss_out_tmc_etf = "/soc/funnel@10b04000/out-ports/port/endpoint"; | |
| pm6450_l18 = "/soc/rsc@17a00000/rpmh-regulator-ldob18/regulator-pm6450-l18"; | |
| S7B = "/soc/rsc@17a00000/rpmh-regulator-smpb7/regulator-pm6450-s7"; | |
| pmg1110_s1_level = "/soc/rsc@17a00000/rpmh-regulator-mxlvl/regulator-pmg1110-s1-level"; | |
| funnel_ete_in_ete6 = "/soc/funnel@12800000/in-ports/port@6/endpoint"; | |
| cpu2_emerg = "/soc/thermal-zones/cpu-0-2/trips/cpu2-emerg-cfg"; | |
| tpda_dl_lpass_10_in_tpdm_dl_lpass = "/soc/tpda@10c3a000/in-ports/port@10/endpoint"; | |
| qupv3_se9_i2c_pins = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins"; | |
| apss_cti0 = "/soc/cti@128e0000"; | |
| CX_RET = "/idle-states/cx-ret"; | |
| cpu5_pause = "/soc/qcom,cpu-pause/cpu5-pause"; | |
| tpdm_wcss = "/soc/tpdm@109A4000"; | |
| qupv3_se9_spi_pins = "/soc/pinctrl@f000000/qupv3_se9_spi_pins"; | |
| ipcb_tgu = "/soc/tgu@10b0e000"; | |
| smmu_rot_sec = "/soc/qcom,mdss_rotator/qcom,smmu_rot_sec_cb"; | |
| tx_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-0-tx"; | |
| tpdm_tmess_1 = "/soc/tpdm@10cc1000"; | |
| qupv3_se1_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_scl_active"; | |
| global_sync_mem = "/reserved-memory/global_sync_region@a6f00000"; | |
| lpass_ag_noc = "/soc/interconnect@3C40000"; | |
| l3_dcvs_sp = "/soc/qcom,dcvs/l3/sp"; | |
| tpda_tmess_out_funnel_tmess = "/soc/tpda@10cc4000/out-ports/port/endpoint"; | |
| tpdm_pimem = "/soc/tpdm@10850000"; | |
| L22B = "/soc/rsc@17a00000/rpmh-regulator-ldob22/regulator-pm6450-l22"; | |
| gcc = "/soc/clock-controller@100000"; | |
| tpdm_spdm = "/soc/tpdm@1000f000"; | |
| wsa_macro = "/soc/spf_core_platform/lpass-cdc/wsa-macro@3240000"; | |
| qupv3_se7_2uart_tx_active = "/soc/pinctrl@f000000/qupv3_se7_2uart_pins/qupv3_se7_2uart_tx_active"; | |
| qupv3_se6_spi = "/soc/spi@a84000"; | |
| L28B = "/soc/rsc@17a00000/rpmh-regulator-ldob28/regulator-pm6450-l28"; | |
| qupv3_0 = "/soc/qcom,qupv3_0_geni_se@9c0000"; | |
| cti0 = "/soc/cti@10c2a000"; | |
| pm6450_l1 = "/soc/rsc@17a00000/rpmh-regulator-ldob1/regulator-pm6450-l1"; | |
| gfx_0_tbu = "/soc/kgsl-smmu@3da0000/gfx_0_tbu@3dc5000"; | |
| pcie_0_pipe_clk = "/soc/clocks/pcie_0_pipe_clk"; | |
| cpu1_emerg = "/soc/thermal-zones/cpu-0-1/trips/cpu1-emerg-cfg"; | |
| pa_lte_sdr0_dsc = "/soc/qmi-tmd-devices/modem/pa_lte_sdr0_dsc"; | |
| S5B_LEVEL_AO = "/soc/rsc@17a00000/rpmh-regulator-cxlvl/regulator-pm6450-s5-level-ao"; | |
| qupv3_se3_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_clk_active"; | |
| funnel_ddr_out_tpda_dl_center_12 = "/soc/funnel@10d03000/out-ports/port@2/endpoint"; | |
| pm6450_l12 = "/soc/rsc@17a00000/rpmh-regulator-ldob12/regulator-pm6450-l12"; | |
| tmc_etr = "/soc/tmc@10048000"; | |
| tdm_pri_tx = "/soc/qcom,msm-dai-tdm-pri-tx"; | |
| tpdm_prng = "/soc/tpdm@10841000"; | |
| replicator_etr_out_tmc_etr1 = "/soc/replicator@1004e000/out-ports/port@1/endpoint"; | |
| funnel_lpass_lpi_in_lpass_stm = "/soc/funnel@10b44000/in-ports/port@1/endpoint"; | |
| int_fm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-tx"; | |
| spmi_bus = "/soc/qcom,spmi@c42d000"; | |
| funnel_dl_center2 = "/soc/funnel@10ac4000"; | |
| qupv3_se7_2uart = "/soc/qcom,qup_uart@a88000"; | |
| system_cma = "/reserved-memory/linux,cma"; | |
| tpda_dl_west_out_funnel_dl_west = "/soc/tpda@10c4a000/out-ports/port/endpoint"; | |
| smmu_sde_sec = "/soc/qcom,smmu_sde_sec_cb"; | |
| tpda_dl_west = "/soc/tpda@10c4a000"; | |
| modem_diag = "/soc/modem_diag"; | |
| ddrqos_freq_table = "/soc/ddrqos-freq-table"; | |
| L1E = "/soc/rsc@17a00000/rpmh-regulator-ldoe1/regulator-pm8010-l1"; | |
| qupv3_se5_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_sda_active"; | |
| spkr_2_sd_n_active = "/soc/pinctrl@f000000/spkr_2_sd_n/spkr_2_sd_n_active"; | |
| adsp_mem = "/reserved-memory/adsp_region@87300000"; | |
| gpu_cc_gx_acd_reset = "/soc/syscon@3d99358"; | |
| aggre2_noc = "/soc/interconnect@1700000"; | |
| qupv3_se3_spi_sleep = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_sleep"; | |
| dai_pri_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-pri-rx/qcom,msm-dai-q6-tdm-pri-rx-0"; | |
| lpass_stm = "/soc/lpass_stm"; | |
| cnss_pci_iommu_group0 = "/soc/qcom,pcie@1c00000/pcie0_rp/cnss_pci0/cnss_pci_iommu_group0"; | |
| hwver_gpio_default = "/soc/pinctrl@f000000/hwver_gpio_default/hwver_gpio_default"; | |
| funnel_dl_center_1_out_tpda_dl_center_10 = "/soc/funnel@10c02000/out-ports/port@0/endpoint"; | |
| tpdm_dl_south0 = "/soc/tpdm@109c0000"; | |
| VDD_MX_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-mxlvl/regulator-pmg1110-s1-level"; | |
| tpdm_wpss = "/soc/tpdm@10c70000"; | |
| replicator_etr_out_tmc_etr = "/soc/replicator@1004e000/out-ports/port@0/endpoint"; | |
| msm_fastrpc = "/soc/qcom,msm_fastrpc"; | |
| funnel_modem = "/soc/funnel@10804000"; | |
| cpu0_pause = "/soc/qcom,cpu-pause/cpu0-pause"; | |
| tpdm_apps1_out_tpda_apss_4 = "/soc/tpdm@12861000/out-ports/port/endpoint"; | |
| audio_pkt_core_platform = "/soc/qcom,audio-pkt-core-platform"; | |
| funnel_ddr_ch01_in_tpdm_ddr_ch01 = "/soc/funnel@10d22000/in-ports/port/endpoint"; | |
| mss_vq6_cti = "/soc/cti@10813000"; | |
| qcom_pmu = "/soc/qcom,pmu"; | |
| pa_lte_sdr1_dsc = "/soc/qmi-tmd-devices/modem/pa_lte_sdr1_dsc"; | |
| cpusys_vm_mem = "/reserved-memory/cpusys_vm_region@e0600000"; | |
| funnel_wpss_in_tpdm_wpss = "/soc/funnel@10c73000/in-ports/port@0/endpoint"; | |
| pa_nr_sdr1_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr1_sub1_dsc"; | |
| disp_rsc = "/soc/rsc@af20000"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc = "/soc/qcom,gdsc@18d07c"; | |
| cnss_wlan_mem = "/reserved-memory/cnss_wlan_region"; | |
| cpu7_emerg0 = "/soc/thermal-zones/cpu-1-2/trips/cpu7-emerg0-cfg"; | |
| pm6450_l28_pbs = "/soc/rsc@17a00000/rpmh-regulator-vrmpx2/regulator-pm6450-l28-pbs"; | |
| smem_mem = "/reserved-memory/smem_region@80900000"; | |
| va_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-2-tx"; | |
| L2_6 = "/cpus/cpu@600/l2-cache"; | |
| qupv3_se9_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_mosi_active"; | |
| cpu3_emerg = "/soc/thermal-zones/cpu-0-3/trips/cpu3-emerg-cfg"; | |
| funnel_dl_lpass = "/soc/funnel@10c3b000"; | |
| vendor_hooks = "/soc/qcom,cpu-vendor-hooks"; | |
| L12B = "/soc/rsc@17a00000/rpmh-regulator-ldob12/regulator-pm6450-l12"; | |
| tpda_modem_0_in_tpdm_modem_0 = "/soc/tpda@10803000/in-ports/port@0/endpoint"; | |
| tdm_quin_rx = "/soc/qcom,msm-dai-tdm-quin-rx"; | |
| CPU1 = "/cpus/cpu@100"; | |
| CPU2 = "/cpus/cpu@200"; | |
| eud_in_replicator_swao = "/soc/dummy_sink/in-ports/port/endpoint"; | |
| wcss0 = "/soc/cti@109AC000"; | |
| modem2_etm0_out_funnel_modem = "/soc/modem2_etm0/out-ports/port/endpoint"; | |
| tpdm_ipa = "/soc/tpdm@10c22000"; | |
| va_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-1-tx"; | |
| qcom_ddr_dcvs_hw = "/soc/qcom,dcvs/ddr"; | |
| qupv3_se9_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_cs_active"; | |
| tpda_aoss_2_in_tpdm_swao_prio_2 = "/soc/tpda@10b08000/in-ports/port@2/endpoint"; | |
| funnel_ete_in_ete3 = "/soc/funnel@12800000/in-ports/port@3/endpoint"; | |
| swao_cti = "/soc/cti@10b00000"; | |
| smmu_rot_unsec = "/soc/qcom,mdss_rotator/qcom,smmu_rot_unsec_cb"; | |
| L11B = "/soc/rsc@17a00000/rpmh-regulator-ldob11/regulator-pm6450-l11"; | |
| funnel_dl_center_in_funnel_wpss = "/soc/funnel@10c2c000/in-ports/port@4/endpoint"; | |
| funnel_in0_in_stm = "/soc/funnel@10041000/in-ports/port@7/endpoint"; | |
| gpu_cc_cx_gdsc = "/soc/qcom,gdsc@3d99108"; | |
| S6B_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-ebilvl/regulator-pm6450-s6-level"; | |
| tpda_apss_4_in_tpdm_apps1 = "/soc/tpda@12863000/in-ports/port@4/endpoint"; | |
| adsp_pas = "/soc/remoteproc-adsp@03000000"; | |
| qcom_rng = "/soc/qrng@10c3000"; | |
| pm6450_l21 = "/soc/rsc@17a00000/rpmh-regulator-ldob21/regulator-pm6450-l21"; | |
| funnel_lpass_in_tpdm_lpass = "/soc/funnel@10846000/in-ports/port/endpoint"; | |
| funnel_dl_south_out_tpda_dl_center2_7 = "/soc/funnel@109c3000/out-ports/port@0/endpoint"; | |
| tpda_dl_center_out_funnel_dl_center = "/soc/tpda@10c2b000/out-ports/port/endpoint"; | |
| tpda_dl_lpass_0_in_tpdm_sdcc = "/soc/tpda@10c3a000/in-ports/port@0/endpoint"; | |
| qupv3_se5_i2c_pins = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins"; | |
| tmess_cpu = "/soc/cti@10cd1000"; | |
| system_noc = "/soc/interconnect@1680000"; | |
| video_cc_mvs0c_gdsc = "/soc/qcom,gdsc@aaf8084"; | |
| scmi_shared_rail = "/soc/qcom,scmi/protocol@88"; | |
| tpda_qdss = "/soc/tpda@10004000"; | |
| afe_pcm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-rx"; | |
| tpdm_lpass_out_funnel_lpass = "/soc/tpdm@10844000/out-ports/port/endpoint"; | |
| trust_ui_vm_vblk0_ring = "/reserved-memory/trust_ui_vm_vblk0_ring@e55fc000"; | |
| tpda_dl_center2_26_in_tpdm_dlct0 = "/soc/tpda@10ac3000/in-ports/port@1a/endpoint"; | |
| tmc_etr1_in_replicator_etr = "/soc/tmc@1004f000/in-ports/port/endpoint"; | |
| tme_log_mem = "/reserved-memory/tme_log_region@808e0000"; | |
| pm6450_s7 = "/soc/rsc@17a00000/rpmh-regulator-smpb7/regulator-pm6450-s7"; | |
| tpdm_dl_center2_dsb = "/soc/tpdm@10ac0000"; | |
| spmi0_debug_bus = "/soc/qcom,spmi-debug@10b14000"; | |
| CPU_PD7 = "/soc/psci/cpu-pd7"; | |
| qupv3_se3_i2c_pins = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins"; | |
| tpdm_dl_south1_out_funnel_dl_south = "/soc/tpdm@109c1000/out-ports/port/endpoint"; | |
| ufs_phy_tx_symbol_0_clk = "/soc/clocks/ufs_phy_tx_symbol_0_clk"; | |
| ipcc_self_ping_cdsp = "/soc/ipcc-self-ping-cdsp"; | |
| sdc2_on = "/soc/pinctrl@f000000/sdc2_on"; | |
| waipio_snd = "/soc/spf_core_platform/sound"; | |
| L24B_PBS = "/soc/rsc@17a00000/rpmh-regulator-vrmsd/regulator-pm6450-l24-pbs"; | |
| afe_proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-rx"; | |
| replicator_etr_in_replicator_qdss = "/soc/replicator@1004e000/in-ports/port/endpoint"; | |
| incall_music_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-2-rx"; | |
| audio_prm = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr/q6prm"; | |
| pm6450_l7 = "/soc/rsc@17a00000/rpmh-regulator-ldob7/regulator-pm6450-l7"; | |
| pcm2 = "/soc/qcom,msm-ultra-low-latency"; | |
| cpu5_emerg = "/soc/thermal-zones/cpu-0-5/trips/cpu5-emerg-cfg"; | |
| tpda_dl_center_21_in_tpdm_gcc = "/soc/tpda@10c2b000/in-ports/port@15/endpoint"; | |
| S1G_LEVEL = "/soc/rsc@17a00000/rpmh-regulator-mxlvl/regulator-pmg1110-s1-level"; | |
| funnel_in1_in_funnel_dl_west = "/soc/funnel@10042000/in-ports/port@5/endpoint"; | |
| bt_sco_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-rx"; | |
| qupv3_se0_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sda_active"; | |
| video_cc_mvs0_gdsc = "/soc/qcom,gdsc@aaf81a4"; | |
| dai_hdmi = "/soc/qcom,msm-dai-q6-hdmi"; | |
| tx_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-2-tx"; | |
| video_mem = "/reserved-memory/video_region@86c00000"; | |
| cpu_scp_lpri = "/sram@17D09100/scp-shmem@0"; | |
| modem_etm0_out_funnel_modem_q6_dup = "/soc/modem_etm0/out-ports/port/endpoint"; | |
| gpu_cc_cx_hw_ctrl = "/soc/syscon@3d9953c"; | |
| altmode = "/soc/qcom,pmic_glink/qcom,altmode"; | |
| pcm1 = "/soc/qcom,msm-pcm-low-latency"; | |
| tdm_sec_tx = "/soc/qcom,msm-dai-tdm-sec-tx"; | |
| qupv3_se4_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_clk_active"; | |
| funnel_dl_south_in_tpdm_wcss = "/soc/funnel@109c3000/in-ports/port@4/endpoint"; | |
| spmi_tgu0 = "/soc/tgu@10b0f000"; | |
| nfc_enable_active = "/soc/pinctrl@f000000/nfc/nfc_enable_active"; | |
| tpda_dl_center_25_in_tpdm_pimem = "/soc/tpda@10c2b000/in-ports/port@19/endpoint"; | |
| modem_lte_dsc = "/soc/qmi-tmd-devices/modem/modem_lte_dsc"; | |
| ufs_phy_rx_symbol_1_clk = "/soc/clocks/ufs_phy_rx_symbol_1_clk"; | |
| tpda_dl_center2_17_in_funnel_gfx = "/soc/tpda@10ac3000/in-ports/port@11/endpoint"; | |
| tpdm_rdpm_mx_out_funnel_dl_center_1 = "/soc/tpdm@10c01000/out-ports/port/endpoint"; | |
| funnel_wpss_out_tpda_dl_center_6 = "/soc/funnel@10c73000/out-ports/port@1/endpoint"; | |
| ts_active = "/soc/pinctrl@f000000/pmx_ts_active/ts_active"; | |
| ipcc_self_ping_apss = "/soc/ipcc-self-ping-apss"; | |
| tpdm_qm_out_tpda_dl_center_20 = "/soc/tpdm@109d0000/out-ports/port/endpoint"; | |
| qfprom_sys = "/soc/qfprom@0"; | |
| CPU6 = "/cpus/cpu@600"; | |
| msm_dai_cdc_dma = "/soc/qcom,msm-dai-cdc-dma"; | |
| sb_7_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-tx"; | |
| sdhc_1 = "/soc/sdhci@7C4000"; | |
| xbl_ramdump_mem = "/reserved-memory/xbl_ramdump_region@80640000"; | |
| hostless = "/soc/qcom,msm-pcm-hostless"; | |
| hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = "/soc/qcom,gdsc@18d06c"; | |
| L7E = "/soc/rsc@17a00000/rpmh-regulator-ldoe7/regulator-pm8010-l7"; | |
| tpdm_apss0_out_tpda_apss_3 = "/soc/tpdm@12860000/out-ports/port/endpoint"; | |
| msm_audio_ion_cma = "/soc/spf_core_platform/qcom,msm-audio-ion-cma"; | |
| wsa_cdc_dma_1_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-1-rx"; | |
| swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@33F0000/va_swr_master"; | |
| qupv3_se3_spi = "/soc/spi@98c000"; | |
| wcd_reset_active = "/soc/pinctrl@f000000/wcd_reset_active"; | |
| L18B = "/soc/rsc@17a00000/rpmh-regulator-ldob18/regulator-pm6450-l18"; | |
| qupv3_se1_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sleep"; | |
| dai_mi2s2 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-tert"; | |
| trans_loopback = "/soc/qcom,msm-transcode-loopback"; | |
| debugcc = "/soc/debug-clock-controller@0"; | |
| tpdm_dl_lpass_out_tpda_dl_lpass_10 = "/soc/tpdm@10c38000/out-ports/port/endpoint"; | |
| qupv3_se6_i2c_pins = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins"; | |
| mdss_rotator = "/soc/qcom,mdss_rotator"; | |
| qupv3_se7_2uart_pins = "/soc/pinctrl@f000000/qupv3_se7_2uart_pins"; | |
| CPU3 = "/cpus/cpu@300"; | |
| tpda_dl_center2_7_in_funnel_dl_south = "/soc/tpda@10ac3000/in-ports/port@7/endpoint"; | |
| wsa_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-2-tx"; | |
| swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@31E0000/wsa2_swr_master"; | |
| cpu6_emerg0 = "/soc/thermal-zones/cpu-1-0/trips/cpu6-emerg0-cfg"; | |
| stm = "/soc/stm@10002000"; | |
| qseecom_ta_mem = "/reserved-memory/qseecom_ta_region"; | |
| sb_8_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-tx"; | |
| qupv3_se1_i2c = "/soc/i2c@984000"; | |
| tpda_dl_center_19_in_tpdm_prng = "/soc/tpda@10c2b000/in-ports/port@13/endpoint"; | |
| ipa_smmu_uc = "/soc/qcom,ipa@3e00000/ipa_smmu_uc"; | |
| funnel_modem_q6_dup = "/soc/funnel@1080d000"; | |
| funnel_apss_out_funnel_dl_center = "/soc/funnel@12810000/out-ports/port/endpoint"; | |
| funnel_modem_q6_out_funnel_modem = "/soc/funnel@1080c000/out-ports/port/endpoint"; | |
| fan_det_default = "/soc/pinctrl@f000000/fan_det_default/fan_det_default"; | |
| qupv3_se0_i2c = "/soc/i2c@980000"; | |
| rx_cdc_dma_5_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-5-rx"; | |
| ramoops_mem = "/reserved-memory/ramoops_region"; | |
| gcc_usb3_phy_gdsc = "/soc/qcom,gdsc@160018"; | |
| tpdm_ddr_ch01 = "/soc/tpdm@10d20000"; | |
| ddr_ch01_dl_cti_0 = "/soc/cti@10d21000"; | |
| sf_0_tbu = "/soc/apps-smmu@15000000/sf_0_tbu@151fd000"; | |
| funnel_modem_in_tpda_modem = "/soc/funnel@10804000/in-ports/port@0/endpoint"; | |
| sdhc1_opp_table = "/soc/sdhc1-opp-table"; | |
| trigout_a = "/soc/pinctrl@f000000/trigout_a"; | |
| gpu_speed_bin = "/soc/qfprom@221c8000/gpu_speed_bin@119"; | |
| qupv3_se3_spi_pins = "/soc/pinctrl@f000000/qupv3_se3_spi_pins"; | |
| replicator_etr = "/soc/replicator@1004e000"; | |
| L25B = "/soc/rsc@17a00000/rpmh-regulator-ldob25/regulator-pm6450-l25"; | |
| tpdm_dlct = "/soc/tpdm@10c28000"; | |
| ete7_out_funnel_ete = "/soc/etm7/out-ports/port/endpoint"; | |
| S9B = "/soc/rsc@17a00000/rpmh-regulator-smpb9/regulator-pm6450-s9"; | |
| gcc_vcodec0_gdsc = "/soc/qcom,gdsc@1b6044"; | |
| cpu4_hotplug = "/soc/qcom,cpu-hotplug/cpu4-hotplug"; | |
| lsm = "/soc/qcom,msm-lsm-client"; | |
| battery_charger = "/soc/qcom,pmic_glink/qcom,battery_charger"; | |
| pcie0_msi = "/soc/qcom,pcie0_msi@0x17210040"; | |
| rx_macro = "/soc/spf_core_platform/lpass-cdc/rx-macro@3200000"; | |
| funnel_ddr_out_tpda_dl_center_9 = "/soc/funnel@10d03000/out-ports/port@0/endpoint"; | |
| wlan = "/soc/qcom,cnss-qca6490@b0000000"; | |
| hyp_mem = "/reserved-memory/hyp_region@80000000"; | |
| funnel_modem_q6_in_funnel_modem_q6_dup = "/soc/funnel@1080c000/in-ports/port@1/endpoint"; | |
| tmess_cti_1 = "/soc/cti@10cc3000"; | |
| audio_cma_mem = "/reserved-memory/audio_cma_region"; | |
| tpdm_swao_prio_2_out_tpda_aoss_2 = "/soc/tpdm@10b0b000/out-ports/port/endpoint"; | |
| tpdm_wpss1 = "/soc/tpdm@10c71000"; | |
| apsscc = "/soc/syscon@17aa0000"; | |
| tdm_tert_rx = "/soc/qcom,msm-dai-tdm-tert-rx"; | |
| gcc_ufs_phy_gdsc = "/soc/qcom,gdsc@187004"; | |
| GOLD_CPU_OFF = "/idle-states/gold-c3"; | |
| trust_ui_vm = "/soc/qcom,trust_ui_vm@e55fc000"; | |
| tpdm_ddr = "/soc/tpdm@10d00000"; | |
| nfc_int_active = "/soc/pinctrl@f000000/nfc/nfc_int_active"; | |
| disp_cc_mdss_core_gdsc = "/soc/qcom,gdsc@af09000"; | |
| swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@3240000/wsa_swr_master"; | |
| dai_sec_auxpcm = "/soc/qcom,msm-sec-auxpcm"; | |
| tx_macro = "/soc/spf_core_platform/lpass-cdc/tx-macro@3220000"; | |
| dai_dp = "/soc/qcom,msm-dai-q6-dp"; | |
| pm6450_s1_level = "/soc/rsc@17a00000/rpmh-regulator-msslvl/regulator-pm6450-s1-level"; | |
| apps_rsc = "/soc/rsc@17a00000"; | |
| tpdm_swao_prio_2 = "/soc/tpdm@10b0b000"; | |
| smem = "/soc/qcom,smem"; | |
| qupv3_se9_i2c = "/soc/i2c@a90000"; | |
| CLUSTER_OFF = "/idle-states/cluster-d4"; | |
| tpdm_rdpm = "/soc/tpdm@10c00000"; | |
| qupv3_se9_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sda_active"; | |
| afe_loopback_tx = "/soc/qcom,msm-dai-q6-afe-loopback-tx"; | |
| tpdm_ipa_out_tpda_dl_center_24 = "/soc/tpdm@10c22000/out-ports/port/endpoint"; | |
| }; | |
| hypervisor { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| compatible = "qcom,gunyah-hypervisor-1.0\0qcom,gunyah-hypervisor\0simple-bus"; | |
| qcom,resource-manager-rpc@f06b2ac981d971fe { | |
| qcom,tx-queue-depth = <0x08>; | |
| qcom,is-full-duplex; | |
| qcom,rx-message-size = <0xf0>; | |
| qcom,rx-queue-depth = <0x08>; | |
| qcom,tx-message-size = <0xf0>; | |
| reg = <0xf06b2ac9 0x81d971fe 0xf06b2ac9 0x81d95bee>; | |
| interrupts = <0x00 0x3a0 0x01 0x00 0x3a1 0x01>; | |
| qcom,free-irq-start = <0x3c0>; | |
| compatible = "qcom,resource-manager-1-0\0qcom,resource-manager\0qcom,gunyah-message-queue\0qcom,gunyah-capability"; | |
| }; | |
| qcom,gunyah-vm { | |
| qcom,vendor = "Qualcomm"; | |
| compatible = "qcom,gunyah-vm-id-1.0\0qcom,gunyah-vm-id"; | |
| qcom,vmid = <0x03>; | |
| }; | |
| qcom,gh-watchdog { | |
| interrupts = <0x00 0x00 0x01>; | |
| compatible = "qcom,gh-watchdog"; | |
| }; | |
| }; | |
| aliases { | |
| hsuart1 = "/soc/qcom,qup_uart@98c000"; | |
| ufshc1 = "/soc/ufshc@1d84000"; | |
| mmc1 = "/soc/sdhci@8804000"; | |
| swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@3200000/rx_swr_master"; | |
| hsuart0 = "/soc/qcom,qup_uart@988000"; | |
| serial0 = "/soc/qcom,qup_uart@a88000"; | |
| serial1 = "/soc/qcom,qup_uart@980000"; | |
| mmc0 = "/soc/sdhci@7C4000"; | |
| phandle = <0x212>; | |
| swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@33F0000/va_swr_master"; | |
| swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@31E0000/wsa2_swr_master"; | |
| swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@3240000/wsa_swr_master"; | |
| }; | |
| firmware { | |
| phandle = <0x214>; | |
| qcom_smcinvoke { | |
| compatible = "qcom,smcinvoke"; | |
| }; | |
| qtee_shmbridge { | |
| compatible = "qcom,tee-shared-memory-bridge"; | |
| }; | |
| android { | |
| compatible = "android,firmware"; | |
| vbmeta { | |
| parts = "vbmeta,boot,system,vendor,dtbo,recovery"; | |
| compatible = "android,vbmeta"; | |
| }; | |
| }; | |
| qcom_scm { | |
| qcom,dload-mode = <0x03 0x13000>; | |
| interrupts = <0x00 0x3a2 0x01>; | |
| compatible = "qcom,scm-v1.1\0qcom,scm"; | |
| qcom,max-queues = <0x02>; | |
| }; | |
| }; | |
| soc { | |
| #size-cells = <0x01>; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| #address-cells = <0x01>; | |
| compatible = "simple-bus"; | |
| phandle = <0x215>; | |
| subsystem-sleep-stats@c3f0000 { | |
| ddr-freq-update; | |
| reg = <0xc3f0000 0x400>; | |
| compatible = "qcom,subsystem-sleep-stats"; | |
| }; | |
| qcom,msm-dai-tdm-tert-rx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9120>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9020>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3d2>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-tert-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9020>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3d3>; | |
| }; | |
| }; | |
| funnel@109c3000 { | |
| coresight-name = "coresight-funnel-dl_south"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x109c3000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x25b>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xd0>; | |
| phandle = <0xda>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xcc>; | |
| source = <0xcd>; | |
| phandle = <0xd1>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xce>; | |
| source = <0xcf>; | |
| phandle = <0xd2>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0xca>; | |
| phandle = <0x6a>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xc9>; | |
| phandle = <0x69>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xcb>; | |
| phandle = <0x75>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10b13000 { | |
| coresight-name = "coresight-cti-cortex_m3"; | |
| clocks = <0x31>; | |
| reg = <0x10b13000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x27d>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,gdsc@aaf8244 { | |
| regulator-name = "video_cc_mvs1_gdsc"; | |
| reg = <0xaaf8244 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x32c>; | |
| qcom,retain-regs; | |
| }; | |
| tmc@10048000 { | |
| qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; | |
| coresight-name = "coresight-tmc-etr"; | |
| clocks = <0x31>; | |
| csr-atid-offset = <0xf8>; | |
| csr-irqctrl-offset = <0x6c>; | |
| reg-names = "tmc-base\0bam-base"; | |
| byte-cntr-name = "byte-cntr"; | |
| coresight-csr = <0x10d>; | |
| reg = <0x10048000 0x1000 0x10064000 0x16000>; | |
| interrupts = <0x00 0x10e 0x01>; | |
| interrupt-names = "byte-cntr-irq"; | |
| qcom,sw-usb; | |
| dma-coherent; | |
| compatible = "arm,primecell"; | |
| byte-cntr-class-name = "coresight-tmc-etr-stream"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x26d>; | |
| qcom,iommu-dma = "bypass"; | |
| arm,scatter-gather; | |
| iommus = <0x2f 0x4e0 0x00 0x2f 0x520 0x00>; | |
| arm,primecell-periphid = <0xbb961>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10e>; | |
| phandle = <0x10b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,ddr-cdev { | |
| qcom,bus-width = <0x04>; | |
| interconnects = <0x29 0x03 0x29 0x200>; | |
| compatible = "qcom,ddr-cooling-device"; | |
| phandle = <0x17c>; | |
| #cooling-cells = <0x02>; | |
| qcom,freq-table = <0x1f8>; | |
| }; | |
| dsi_panel_pwr_supply_sim { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| phandle = <0x44a>; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| qcom,supply-disable-load = <0x50>; | |
| reg = <0x00>; | |
| qcom,supply-name = "dummy"; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-enable-load = <0x30d40>; | |
| }; | |
| }; | |
| tmc@10b05000 { | |
| coresight-name = "coresight-tmc-etf"; | |
| clocks = <0x31>; | |
| reg-names = "tmc-base"; | |
| reg = <0x10b05000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x269>; | |
| arm,primecell-periphid = <0xbb961>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x104>; | |
| phandle = <0x105>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x103>; | |
| phandle = <0x101>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| mini_dump_node { | |
| status = "ok"; | |
| compatible = "qcom,minidump"; | |
| }; | |
| qcom,disp1-gdsc@1570b000 { | |
| regulator-name = "disp1_cc_mdss_core_int2_gdsc"; | |
| reg = <0x1570b000 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x318>; | |
| qcom,retain-regs; | |
| }; | |
| i2c@a84000 { | |
| dmas = <0x1c4 0x00 0x01 0x03 0x40 0x00 0x1c4 0x01 0x01 0x03 0x40 0x00>; | |
| qcom,wrapper-core = <0x1c0>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x4c 0x24 0x56 0x24 0x57>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0xa84000 0x4000>; | |
| interrupts = <0x00 0x162 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1cc>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x33f>; | |
| pinctrl-0 = <0x1ca 0x1cb>; | |
| }; | |
| tpdm@10d20000 { | |
| coresight-name = "coresight-tpdm-ddr-ch01"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10d20000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x93>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x54>; | |
| phandle = <0x8d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10cc9000 { | |
| coresight-name = "coresight-tpdm-tmess-prng"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10cc9000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x55>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x247>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x76>; | |
| phandle = <0x9e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@109C2000 { | |
| coresight-name = "coresight-cti-dl_south_cti0"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x109c2000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x272>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| disp_rdump_region@e1000000 { | |
| reg = <0xb8000000 0x800000>; | |
| phandle = <0x46e>; | |
| label = "disp_rdump_region"; | |
| }; | |
| cti@10d02000 { | |
| coresight-name = "coresight-cti-ddr_dl_0_cti_0"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10d02000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x273>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| funnel@10041000 { | |
| coresight-name = "coresight-funnel-in0"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10041000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x263>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xef>; | |
| phandle = <0xf6>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0xee>; | |
| phandle = <0x65>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xed>; | |
| phandle = <0xea>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xeb>; | |
| phandle = <0x63>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xec>; | |
| phandle = <0xa3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,dma-heaps { | |
| compatible = "qcom,dma-heaps"; | |
| qcom,audio_ml { | |
| qcom,dma-heap-type = <0x02>; | |
| memory-region = <0x38>; | |
| qcom,dma-heap-name = "qcom,audio-ml"; | |
| }; | |
| qcom,user_contig { | |
| qcom,dma-heap-type = <0x02>; | |
| memory-region = <0x35>; | |
| qcom,dma-heap-name = "qcom,user-contig"; | |
| }; | |
| qcom,qseecom_ta { | |
| qcom,dma-heap-type = <0x02>; | |
| memory-region = <0x37>; | |
| qcom,dma-heap-name = "qcom,qseecom-ta"; | |
| }; | |
| qcom,display { | |
| qcom,max-align = <0x09>; | |
| qcom,dma-heap-type = <0x02>; | |
| memory-region = <0x39>; | |
| qcom,dma-heap-name = "qcom,display"; | |
| phandle = <0x222>; | |
| }; | |
| qcom,qseecom { | |
| qcom,dma-heap-type = <0x02>; | |
| memory-region = <0x36>; | |
| qcom,dma-heap-name = "qcom,qseecom"; | |
| }; | |
| }; | |
| thermal-sensor@c265000 { | |
| #qcom,sensors = <0x10>; | |
| reg = <0xc265000 0x1ff 0xc223000 0x1ff>; | |
| interrupts = <0x00 0x1fb 0x04 0x00 0x1fd 0x04 0x00 0x1f5 0x01>; | |
| interrupt-names = "uplow\0critical\0cold"; | |
| compatible = "qcom,tsens-v2"; | |
| phandle = <0x17a>; | |
| #thermal-sensor-cells = <0x01>; | |
| }; | |
| tpdm@109c0000 { | |
| coresight-name = "coresight-tpdm-dl-south-dsb"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x109c0000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4f>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0xcd>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x69>; | |
| phandle = <0xc9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-voip-dsp { | |
| compatible = "qcom,msm-voip-dsp"; | |
| phandle = <0x382>; | |
| }; | |
| i2c@a8c000 { | |
| dmas = <0x1c4 0x00 0x03 0x03 0x40 0x00 0x1c4 0x01 0x03 0x03 0x40 0x00>; | |
| qcom,wrapper-core = <0x1c0>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x50 0x24 0x56 0x24 0x57>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0xa8c000 0x4000>; | |
| interrupts = <0x00 0x164 0x04>; | |
| status = "ok"; | |
| pinctrl-1 = <0x1d4>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x341>; | |
| pinctrl-0 = <0x1d2 0x1d3>; | |
| qcom,shared; | |
| aw883xx_smartpa@34 { | |
| irq-gpio = <0x126 0x2a 0x2008>; | |
| sync-load = <0x01>; | |
| re-min = <0x3e8>; | |
| sound-channel = <0x01>; | |
| reg = <0x34>; | |
| re-max = <0x9c40>; | |
| status = "okay"; | |
| compatible = "awinic,aw883xx_smartpa"; | |
| reset-gpio = <0x126 0x02 0x00>; | |
| rename-flag = <0x01>; | |
| }; | |
| pm8010n@c { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x0c>; | |
| compatible = "qcom,i2c-pmic"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x407>; | |
| pm8010-chip@900 { | |
| reg = <0x900>; | |
| compatible = "qcom,pm8008-chip"; | |
| qcom,pm8008-chip-en { | |
| regulator-name = "pm8010n-chip-en"; | |
| phandle = <0x408>; | |
| }; | |
| }; | |
| qcom,revid@100 { | |
| reg = <0x100>; | |
| compatible = "qcom,qpnp-revid"; | |
| }; | |
| }; | |
| pm8010n@d { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x0d>; | |
| compatible = "qcom,i2c-pmic"; | |
| qcom,pm8010n-regulator { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| vdd_l1_l2-supply = <0x1ee>; | |
| compatible = "qcom,pm8010-regulator"; | |
| pm8008_en-supply = <0x408>; | |
| regulator@4300 { | |
| regulator-max-microvolt = <0x1cfde0>; | |
| regulator-name = "pm8010N_l4"; | |
| qcom,hpm-min-load = <0x00>; | |
| reg = <0x4300>; | |
| qcom,min-dropout-voltage = <0x251c0>; | |
| regulator-min-microvolt = <0x1a0040>; | |
| phandle = <0x439>; | |
| }; | |
| regulator@4000 { | |
| regulator-max-microvolt = <0x118c30>; | |
| regulator-name = "pm8010n_l1"; | |
| qcom,hpm-min-load = <0x7530>; | |
| reg = <0x4000>; | |
| qcom,min-dropout-voltage = <0x11940>; | |
| regulator-min-microvolt = <0xe7ef0>; | |
| phandle = <0x437>; | |
| }; | |
| regulator@4500 { | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "pm8010n_l6"; | |
| qcom,hpm-min-load = <0x00>; | |
| reg = <0x4500>; | |
| regulator-min-microvolt = <0x2932e0>; | |
| phandle = <0x43a>; | |
| }; | |
| regulator@4200 { | |
| regulator-max-microvolt = <0x328980>; | |
| regulator-name = "pm8010n_l3"; | |
| qcom,hpm-min-load = <0x00>; | |
| reg = <0x4200>; | |
| qcom,min-dropout-voltage = <0x1d4c0>; | |
| regulator-min-microvolt = <0x1a7d40>; | |
| phandle = <0x438>; | |
| }; | |
| }; | |
| }; | |
| fsa4480@42 { | |
| reg = <0x42>; | |
| compatible = "qcom,fsa4480-i2c"; | |
| phandle = <0x342>; | |
| }; | |
| pm8010m@9 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x09>; | |
| compatible = "qcom,i2c-pmic"; | |
| qcom,pm8010m-regulator { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| vdd_l1_l2-supply = <0x1ee>; | |
| compatible = "qcom,pm8010-regulator"; | |
| pm8008_en-supply = <0x406>; | |
| regulator@4100 { | |
| regulator-max-microvolt = <0x118c30>; | |
| regulator-name = "pm8010m_l2"; | |
| qcom,hpm-min-load = <0x7530>; | |
| reg = <0x4100>; | |
| qcom,min-dropout-voltage = <0x13880>; | |
| regulator-min-microvolt = <0xe7ef0>; | |
| phandle = <0x432>; | |
| }; | |
| regulator@4300 { | |
| regulator-max-microvolt = <0x2c4020>; | |
| regulator-name = "pm8010m_l4"; | |
| qcom,hpm-min-load = <0x00>; | |
| reg = <0x4300>; | |
| regulator-min-microvolt = <0x2932e0>; | |
| phandle = <0x434>; | |
| }; | |
| regulator@4000 { | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "pm8010m_l1"; | |
| qcom,hpm-min-load = <0x7530>; | |
| reg = <0x4000>; | |
| qcom,min-dropout-voltage = <0x157c0>; | |
| regulator-min-microvolt = <0xf4240>; | |
| phandle = <0x431>; | |
| }; | |
| regulator@4600 { | |
| regulator-max-microvolt = <0x2d0370>; | |
| regulator-name = "pm8010m_l7"; | |
| qcom,hpm-min-load = <0x00>; | |
| reg = <0x4600>; | |
| regulator-min-microvolt = <0x286f90>; | |
| phandle = <0x436>; | |
| }; | |
| regulator@4500 { | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "pm8010m_l6"; | |
| qcom,hpm-min-load = <0x00>; | |
| reg = <0x4500>; | |
| regulator-min-microvolt = <0x2932e0>; | |
| phandle = <0x435>; | |
| }; | |
| regulator@4200 { | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "pm8010m_l3"; | |
| qcom,hpm-min-load = <0x00>; | |
| reg = <0x4200>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| phandle = <0x433>; | |
| }; | |
| }; | |
| }; | |
| awinic@64 { | |
| reg = <0x64>; | |
| compatible = "awinic,aw2016_led"; | |
| awinic,blue { | |
| awinic,id = <0x02>; | |
| awinic,max-brightness = <0xff>; | |
| awinic,rise-time-ms = <0x06>; | |
| awinic,led-current = <0x03>; | |
| awinic,name = "blue"; | |
| awinic,imax = <0x02>; | |
| awinic,off-time-ms = <0x04>; | |
| awinic,fall-time-ms = <0x06>; | |
| awinic,hold-time-ms = <0x00>; | |
| }; | |
| awinic,green { | |
| awinic,id = <0x01>; | |
| awinic,max-brightness = <0xff>; | |
| awinic,rise-time-ms = <0x06>; | |
| awinic,led-current = <0x03>; | |
| awinic,name = "green"; | |
| awinic,imax = <0x02>; | |
| awinic,off-time-ms = <0x04>; | |
| awinic,fall-time-ms = <0x06>; | |
| awinic,hold-time-ms = <0x00>; | |
| }; | |
| awinic,red { | |
| awinic,id = <0x00>; | |
| awinic,max-brightness = <0xff>; | |
| awinic,rise-time-ms = <0x06>; | |
| awinic,led-current = <0x03>; | |
| awinic,name = "red"; | |
| awinic,imax = <0x02>; | |
| awinic,off-time-ms = <0x04>; | |
| awinic,fall-time-ms = <0x06>; | |
| awinic,hold-time-ms = <0x00>; | |
| }; | |
| }; | |
| aw883xx_smartpa@35 { | |
| irq-gpio = <0x126 0x2f 0x2008>; | |
| sync-load = <0x01>; | |
| re-min = <0x3e8>; | |
| sound-channel = <0x00>; | |
| reg = <0x35>; | |
| re-max = <0x9c40>; | |
| status = "okay"; | |
| compatible = "awinic,aw883xx_smartpa"; | |
| reset-gpio = <0x126 0x03 0x00>; | |
| rename-flag = <0x01>; | |
| }; | |
| pm8010m@8 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x08>; | |
| compatible = "qcom,i2c-pmic"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x405>; | |
| pm8010-chip@900 { | |
| reg = <0x900>; | |
| compatible = "qcom,pm8008-chip"; | |
| qcom,pm8008-chip-en { | |
| regulator-name = "pm8010m-chip-en"; | |
| phandle = <0x406>; | |
| }; | |
| }; | |
| qcom,revid@100 { | |
| reg = <0x100>; | |
| compatible = "qcom,qpnp-revid"; | |
| }; | |
| }; | |
| }; | |
| cti@10c2a000 { | |
| coresight-name = "coresight-cti-cti0"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10c2a000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x271>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| display_gpio_regulator@1 { | |
| enable-active-high; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-boot-on; | |
| regulator-name = "display_panel_vddio"; | |
| regulator-enable-ramp-delay = <0xe9>; | |
| compatible = "qti-regulator-fixed"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| pinctrl-names = "default"; | |
| gpio = <0x414 0x0b 0x00>; | |
| phandle = <0x451>; | |
| qcom,proxy-consumer-enable; | |
| pinctrl-0 = <0x457>; | |
| proxy-supply = <0x451>; | |
| }; | |
| qcom,gdsc@18d06c { | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc"; | |
| reg = <0x18d06c 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x325>; | |
| }; | |
| bamdma@3304000 { | |
| qcom,ee = <0x01>; | |
| num-channels = <0x1f>; | |
| qcom,num-ees = <0x02>; | |
| reg-names = "bam\0bam_remote_mem"; | |
| #dma-cells = <0x01>; | |
| reg = <0x3304000 0x20000 0x326b000 0x1000>; | |
| interrupts = <0x00 0xa4 0x04>; | |
| qcom,controlled-remotely; | |
| compatible = "qcom,bam-v1.7.0"; | |
| phandle = <0x12d>; | |
| }; | |
| qcom,rmtfs_sharedmem@0 { | |
| qcom,client-id = <0x01>; | |
| reg-names = "rmtfs"; | |
| reg = <0x00 0x280000>; | |
| compatible = "qcom,sharedmem-uio"; | |
| }; | |
| tpda@10004000 { | |
| coresight-name = "coresight-tpda-qdss"; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x10004000 0x1000>; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x00 0x20 0x01 0x20>; | |
| qcom,tpda-atid = <0x41>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x262>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xea>; | |
| phandle = <0xed>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe8>; | |
| phandle = <0x66>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xe9>; | |
| phandle = <0x64>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| timer { | |
| interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0c 0xff08>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv8-timer"; | |
| always-on; | |
| phandle = <0x295>; | |
| }; | |
| qcom,msm-dai-q6-dp { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| phandle = <0x387>; | |
| qcom,msm-dai-q6-dev-id = <0x00>; | |
| }; | |
| syscon@162204 { | |
| reg = <0x162204 0x04>; | |
| compatible = "syscon"; | |
| phandle = <0x319>; | |
| }; | |
| usb_nop_phy { | |
| compatible = "usb-nop-xceiv"; | |
| phandle = <0x224>; | |
| }; | |
| qcom,gdsc@aaf5004 { | |
| regulator-name = "video_cc_mvsc_gdsc"; | |
| reg = <0xaaf5004 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x32e>; | |
| qcom,retain-regs; | |
| }; | |
| i2c@a90000 { | |
| dmas = <0x1c4 0x00 0x04 0x03 0x40 0x00 0x1c4 0x01 0x04 0x03 0x40 0x00>; | |
| qcom,wrapper-core = <0x1c0>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x52 0x24 0x56 0x24 0x57>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0xa90000 0x4000>; | |
| interrupts = <0x00 0x165 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1dc>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x344>; | |
| pinctrl-0 = <0x1da 0x1db>; | |
| }; | |
| tpdm@109d0000 { | |
| coresight-name = "coresight-tpdm-qm"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x109d0000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x230>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x59>; | |
| phandle = <0xbd>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,wcn6750 { | |
| qcom,vdd-1.3-rfa-config = <0x1312d0 0x14a140 0x00 0x00 0x00>; | |
| qcom,vdd-cx-mx-config = <0xf6950 0x111700 0x00 0x00 0x01>; | |
| tsens = "quiet-therm"; | |
| qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; | |
| qcom,smem-states = <0x1f3 0x00 0x1f4 0x00 0x1f5 0x00>; | |
| qcom,smem-state-names = "wlan-smp2p-out\0wlan-soc-wake-smp2p-out\0wlan-ep-powersave-smp2p-out"; | |
| qcom,wlan; | |
| reg-names = "msi_addr\0smmu_iova_ipa"; | |
| qcom,vdd-1.8-xo-config = <0x1c5200 0x1f20c0 0x00 0x00 0x00>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; | |
| reg = <0x17210040 0x00 0xb0000000 0x10000>; | |
| interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>; | |
| status = "disabled"; | |
| vdd-cx-mx-supply = <0x1ed>; | |
| vdd-1.3-rfa-supply = <0x1ee>; | |
| dma-coherent; | |
| compatible = "qcom,wcn6750"; | |
| qcom,rproc-handle = <0x1f1>; | |
| qcom,wlan-msa-fixed-region = <0x1f2>; | |
| phandle = <0x34a>; | |
| qcom,iommu-dma = "fastmap"; | |
| iommus = <0x2f 0x1400 0x01>; | |
| qcom,iommu-geometry = <0xa0000000 0x10010000>; | |
| qcom,fw-prefix; | |
| qcom,icnss_cdev2 { | |
| phandle = <0x34c>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| qcom,icnss_cdev1 { | |
| phandle = <0x34b>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| qcom,smp2p_map_wlan_1_in { | |
| interrupts-extended = <0x1f6 0x00 0x00 0x1f6 0x01 0x00>; | |
| interrupt-names = "qcom,smp2p-force-fatal-error\0qcom,smp2p-early-crash-ind"; | |
| }; | |
| qcom,smp2p_map_wlan_2_in { | |
| interrupts-extended = <0x1f7 0x00 0x00>; | |
| interrupt-names = "qcom,smp2p-soc-wake-ack"; | |
| }; | |
| }; | |
| tpdm@10cc1000 { | |
| coresight-name = "coresight-tpdm-tmess-1"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10cc1000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x55>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x249>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x78>; | |
| phandle = <0xa0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| rpmh-sleep-stats@c3f0000 { | |
| ddr-freq-update; | |
| ss-name = "modem\0adsp\0adsp_island\0apss\0wpss"; | |
| reg = <0xc3f0000 0x400>; | |
| compatible = "qcom,rpmh-sleep-stats"; | |
| mboxes = <0x02 0x00>; | |
| }; | |
| qcom,msm-compress-dsp { | |
| compatible = "qcom,msm-compress-dsp"; | |
| phandle = <0x381>; | |
| }; | |
| qcom,msm-adsp-loader { | |
| qcom,adsp-state = <0x00>; | |
| status = "ok"; | |
| compatible = "qcom,adsp-loader"; | |
| qcom,rproc-handle = <0x2d4>; | |
| phandle = <0x3c8>; | |
| }; | |
| qcom,msm-transcode-loopback { | |
| compatible = "qcom,msm-transcode-loopback"; | |
| phandle = <0x380>; | |
| }; | |
| qcom,msm-dai-tdm-pri-rx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9100>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3ca>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-pri-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9000>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3cb>; | |
| }; | |
| }; | |
| cti@10cd1000 { | |
| coresight-name = "coresight-cti-tmess_cpu"; | |
| clocks = <0x31>; | |
| reg = <0x10cd1000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x288>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| rsc@17a00000 { | |
| qcom,drv-id = <0x02>; | |
| power-domains = <0x123>; | |
| reg-names = "drv-0\0drv-1\0drv-2"; | |
| reg = <0x17a00000 0x10000 0x17a10000 0x10000 0x17a20000 0x10000>; | |
| interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>; | |
| qcom,tcs-offset = <0xd00>; | |
| compatible = "qcom,rpmh-rsc"; | |
| phandle = <0x296>; | |
| label = "apps_rsc"; | |
| qcom,tcs-config = <0x02 0x02 0x00 0x03 0x01 0x03 0x03 0x00 0x04 0x00>; | |
| rpmh-regulator-cxlvl { | |
| qcom,resource-name = "cx.lvl"; | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| proxy-supply = <0x124>; | |
| regulator-pm6450-s5-level { | |
| qcom,proxy-consumer-voltage = <0x180 0xffff>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xffff>; | |
| qcom,init-voltage-level = <0x180>; | |
| regulator-name = "pm6450_s5_level"; | |
| regulator-min-microvolt = <0x10>; | |
| phandle = <0x124>; | |
| qcom,proxy-consumer-enable; | |
| }; | |
| regulator-cdev { | |
| compatible = "qcom,rpmh-reg-cdev"; | |
| phandle = <0x17e>; | |
| #cooling-cells = <0x02>; | |
| mboxes = <0x02 0x00>; | |
| qcom,reg-resource-name = "cx"; | |
| }; | |
| regulator-pm6450-s5-level-ao { | |
| qcom,set = <0x01>; | |
| regulator-max-microvolt = <0xffff>; | |
| qcom,init-voltage-level = <0x10>; | |
| regulator-name = "pm6450_s5_level_ao"; | |
| regulator-min-microvolt = <0x10>; | |
| phandle = <0x297>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob9 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob9"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l9 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xc92c0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l9"; | |
| qcom,init-voltage = <0xb7980>; | |
| regulator-min-microvolt = <0x7b0c0>; | |
| phandle = <0x29e>; | |
| }; | |
| }; | |
| rpmh-regulator-lcxlvl { | |
| qcom,resource-name = "lcx.lvl"; | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| regulator-pm6450-l2-level { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xffff>; | |
| qcom,init-voltage-level = <0x10>; | |
| regulator-name = "pm6450_l2_level"; | |
| regulator-min-microvolt = <0x10>; | |
| phandle = <0x153>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob28 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob28"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l28 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l28"; | |
| qcom,init-voltage = <0x2932e0>; | |
| regulator-min-microvolt = <0x18b820>; | |
| phandle = <0x2ab>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob11 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob11"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l11 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xb7980>; | |
| regulator-name = "pm6450_l11"; | |
| qcom,init-voltage = <0x54f60>; | |
| regulator-min-microvolt = <0x4c2c0>; | |
| phandle = <0x2a0>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoe4 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldoe4"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| regulator-pm8010-l4 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x328980>; | |
| regulator-name = "pm8010_l4"; | |
| qcom,init-voltage = <0x2932e0>; | |
| regulator-min-microvolt = <0x27ac40>; | |
| phandle = <0x2ad>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob3 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob3"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l3 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xecd10>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l3"; | |
| qcom,init-voltage = <0xdcb40>; | |
| regulator-min-microvolt = <0xd4670>; | |
| phandle = <0x29b>; | |
| }; | |
| }; | |
| rpmh-regulator-msslvl { | |
| qcom,resource-name = "mss.lvl"; | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| regulator-pm6450-s1-level { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xffff>; | |
| qcom,init-voltage-level = <0x10>; | |
| regulator-name = "pm6450_s1_level"; | |
| regulator-min-microvolt = <0x10>; | |
| phandle = <0x158>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob18 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob18"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l18 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1e8480>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l18"; | |
| qcom,init-voltage = <0x16f300>; | |
| regulator-min-microvolt = <0x16f300>; | |
| phandle = <0x2a4>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob1 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob1"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l1 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x9eb10>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l1"; | |
| qcom,init-voltage = <0x7b0c0>; | |
| regulator-min-microvolt = <0x4c2c0>; | |
| phandle = <0x29a>; | |
| }; | |
| }; | |
| rpmh-regulator-ebilvl { | |
| qcom,resource-name = "ebi.lvl"; | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| regulator-pm6450-s6-level { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xffff>; | |
| qcom,init-voltage-level = <0x10>; | |
| regulator-name = "pm6450_s6_level"; | |
| regulator-min-microvolt = <0x10>; | |
| phandle = <0x298>; | |
| }; | |
| }; | |
| rpmh-regulator-sf1-vreg-mode { | |
| qcom,resource-name = "gpioi10"; | |
| status = "disabled"; | |
| compatible = "qcom,rpmh-xob-regulator"; | |
| regulator-sf1-vreg-mode { | |
| qcom,set = <0x03>; | |
| regulator-name = "sf1_vreg_mode"; | |
| phandle = <0x2b1>; | |
| }; | |
| }; | |
| rpmh-regulator-mxlvl { | |
| qcom,resource-name = "mx.lvl"; | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| proxy-supply = <0x125>; | |
| regulator-pmg1110-s1-level { | |
| qcom,proxy-consumer-voltage = <0x180 0xffff>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xffff>; | |
| qcom,init-voltage-level = <0x180>; | |
| regulator-name = "pmg1110_s1_level"; | |
| regulator-min-microvolt = <0x10>; | |
| phandle = <0x125>; | |
| qcom,proxy-consumer-enable; | |
| }; | |
| }; | |
| rpmh-regulator-ldob22 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob22"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l22 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1e8480>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l22"; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x16f300>; | |
| phandle = <0x2a7>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob16 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob16"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l16 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1339e0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l16"; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x4c2c0>; | |
| phandle = <0x47>; | |
| }; | |
| }; | |
| rpmh-regulator-smpb8 { | |
| qcom,resource-name = "smpb8"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| regulator-pm6450-s8 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1a9c80>; | |
| regulator-name = "pm6450_s8"; | |
| qcom,init-voltage = <0x14a140>; | |
| regulator-min-microvolt = <0x5d430>; | |
| phandle = <0x1ee>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob23 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob23"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l23 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1e3660>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l23"; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x18b820>; | |
| phandle = <0x43>; | |
| }; | |
| }; | |
| rpmh-regulator-vrmpx2 { | |
| qcom,resource-name = "vrm.px2"; | |
| compatible = "qcom,rpmh-pbs-regulator"; | |
| regulator-pm6450-l28-pbs { | |
| qcom,set = <0x03>; | |
| regulator-name = "pm6450_l28_pbs"; | |
| phandle = <0x2b3>; | |
| }; | |
| }; | |
| rpmh-regulator-smpb7 { | |
| qcom,resource-name = "smpb7"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| regulator-pm6450-s7 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x11da50>; | |
| regulator-name = "pm6450_s7"; | |
| qcom,init-voltage = <0x111700>; | |
| regulator-min-microvolt = <0xf6950>; | |
| phandle = <0x1ed>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoe1 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldoe1"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8010-l1 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = "\0\r/"; | |
| regulator-name = "pm8010_l1"; | |
| qcom,init-voltage = <0x81650>; | |
| regulator-min-microvolt = <0x81650>; | |
| phandle = <0x2ac>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoe3 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldoe3"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| regulator-pm8010-l3 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "pm8010_l3"; | |
| qcom,init-voltage = <0x2932e0>; | |
| regulator-min-microvolt = <0x2932e0>; | |
| phandle = <0x1ef>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob26 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob26"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l26 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l26"; | |
| qcom,init-voltage = <0x18b820>; | |
| regulator-min-microvolt = <0x18b820>; | |
| phandle = <0x2a9>; | |
| }; | |
| }; | |
| bcm_voter { | |
| compatible = "qcom,bcm-voter"; | |
| phandle = <0x14e>; | |
| }; | |
| rpmh-regulator-ldob24 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob24"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l24 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x3613c0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l24"; | |
| qcom,init-voltage = <0x2932e0>; | |
| regulator-min-microvolt = <0x2932e0>; | |
| phandle = <0x2a8>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob4 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob4"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l4 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xd1f60>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l4"; | |
| qcom,init-voltage = <0xc5440>; | |
| regulator-min-microvolt = <0x81650>; | |
| phandle = <0x29c>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoe5 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldoe5"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| regulator-pm8010-l5 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "pm8010_l5"; | |
| qcom,init-voltage = <0x325aa0>; | |
| regulator-min-microvolt = <0x325aa0>; | |
| phandle = <0x2ae>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob27 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob27"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l27 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l27"; | |
| qcom,init-voltage = <0x18b820>; | |
| regulator-min-microvolt = <0x18b820>; | |
| phandle = <0x2aa>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob10 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob10"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l10 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xdbf88>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l10"; | |
| qcom,init-voltage = <0xc92c0>; | |
| regulator-min-microvolt = <0xc92c0>; | |
| phandle = <0x29f>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob12 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob12"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l12 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x13e5c0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l12"; | |
| qcom,init-voltage = <0x107ac0>; | |
| regulator-min-microvolt = <0x107ac0>; | |
| phandle = <0x2a1>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob13 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob13"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l13 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x13e5c0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l13"; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x107ac0>; | |
| phandle = <0x2a2>; | |
| }; | |
| }; | |
| rpmh-regulator-vrmsd { | |
| qcom,resource-name = "vrm.sd"; | |
| compatible = "qcom,rpmh-pbs-regulator"; | |
| regulator-pm6450-l24-pbs { | |
| qcom,set = <0x03>; | |
| regulator-name = "pm6450_l24_pbs"; | |
| phandle = <0x2b2>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob25 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob25"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l25 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x3613c0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l25"; | |
| qcom,init-voltage = <0x2ee000>; | |
| regulator-min-microvolt = <0x2932e0>; | |
| phandle = <0x44>; | |
| }; | |
| }; | |
| qcom,rpmhclk { | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,ravelin-rpmh-clk"; | |
| phandle = <0x45>; | |
| }; | |
| rpmh-regulator-ldob5 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob5"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l5 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x100d60>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l4"; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0x4c2c0>; | |
| phandle = <0x42>; | |
| }; | |
| }; | |
| rpmh-regulator-smpb9 { | |
| qcom,resource-name = "smpb9"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| regulator-pm6450-s9 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1f20c0>; | |
| regulator-name = "pm6450_s9"; | |
| regulator-always-on; | |
| qcom,init-voltage = <0x1c9080>; | |
| regulator-min-microvolt = <0x1c5200>; | |
| phandle = <0x299>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob19 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob19"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l19 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1dc130>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l19"; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x19f0a0>; | |
| phandle = <0x2a5>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob6 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob6"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l6 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xc92c0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l6"; | |
| qcom,init-voltage = <0xc92c0>; | |
| regulator-min-microvolt = <0xb7598>; | |
| phandle = <0x29d>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoe6 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldoe6"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| regulator-pm8010-l6 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x328980>; | |
| regulator-name = "pm8010_l6"; | |
| qcom,init-voltage = <0x2dc6c0>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| phandle = <0x2af>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob20 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob20"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l20 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1cfde0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l20"; | |
| qcom,init-voltage = <0x19f0a0>; | |
| regulator-min-microvolt = <0x19f0a0>; | |
| phandle = <0x2a6>; | |
| }; | |
| }; | |
| rpmh-regulator-sf1-vreg-enable { | |
| qcom,resource-name = "gpioi7"; | |
| status = "disabled"; | |
| compatible = "qcom,rpmh-xob-regulator"; | |
| regulator-sf1-vreg-enable { | |
| qcom,set = <0x03>; | |
| regulator-name = "sf1_vreg_enable"; | |
| phandle = <0x2b0>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob7 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob7"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l7 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xe09c0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l7"; | |
| qcom,init-voltage = <0xdea80>; | |
| regulator-min-microvolt = <0xcaa30>; | |
| phandle = <0x46>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob17 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob17"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l17 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l17"; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| phandle = <0x2a3>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoe7 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldoe7"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| regulator-pm8010-l7 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x3613c0>; | |
| regulator-name = "pm8010_l7"; | |
| regulator-always-on; | |
| qcom,init-voltage = <0x2dc6c0>; | |
| regulator-min-microvolt = <0x2625a0>; | |
| phandle = <0x129>; | |
| }; | |
| }; | |
| rpmh-regulator-lmxlvl { | |
| qcom,resource-name = "lmx.lvl"; | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| regulator-pm6450-l8-level { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xffff>; | |
| qcom,init-voltage-level = <0x10>; | |
| regulator-name = "pm6450_l8_level"; | |
| regulator-min-microvolt = <0x10>; | |
| phandle = <0x154>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob21 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob21"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l21 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1e8480>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l21"; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x16f300>; | |
| phandle = <0x127>; | |
| }; | |
| }; | |
| rpmh-regulator-ldob14 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| qcom,resource-name = "ldob14"; | |
| qcom,disable-mode = <0x02>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm6450-l14 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x13e5c0>; | |
| qcom,init-mode = <0x04>; | |
| regulator-name = "pm6450_l14"; | |
| qcom,init-voltage = <0x118c30>; | |
| regulator-min-microvolt = <0x12ff48>; | |
| phandle = <0x128>; | |
| }; | |
| }; | |
| }; | |
| syscon@162128 { | |
| reg = <0x162128 0x04>; | |
| compatible = "syscon"; | |
| phandle = <0x18b>; | |
| }; | |
| cti@1080b000 { | |
| coresight-name = "coresight-cti-mss_q6_cti"; | |
| clocks = <0x31>; | |
| reg = <0x1080b000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x284>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,logbuf-vendor-hooks { | |
| compatible = "qcom,logbuf-vendor-hooks"; | |
| phandle = <0x2cf>; | |
| }; | |
| qcom,smem { | |
| hwlocks = <0x13a 0x03>; | |
| compatible = "qcom,smem"; | |
| memory-region = <0x139>; | |
| phandle = <0x2c4>; | |
| }; | |
| rx_core_clk { | |
| qcom,codec-ext-clk-src = <0x05>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x30e>; | |
| qcom,codec-lpass-ext-clk-freq = <0x1588800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x471>; | |
| }; | |
| remoteproc-mss@04080000 { | |
| qcom,smem-states = <0x15b 0x00>; | |
| qcom,smem-state-names = "stop"; | |
| qcom,qmp = <0x31>; | |
| interrupts-extended = <0x01 0x00 0x108 0x01 0x15a 0x00 0x00 0x15a 0x02 0x00 0x15a 0x01 0x00 0x15a 0x03 0x00 0x15a 0x07 0x00>; | |
| clocks = <0x45 0x00>; | |
| reg-names = "cx\0mx"; | |
| reg = <0x4080000 0x10000>; | |
| mx-supply = <0x158>; | |
| interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack"; | |
| interconnect-names = "rproc_ddr\0crypto_ddr"; | |
| status = "ok"; | |
| interconnects = <0x29 0x03 0x29 0x200 0x3c 0x26 0x29 0x200>; | |
| compatible = "qcom,ravelin-modem-pas"; | |
| cx-supply = <0x124>; | |
| memory-region = <0x159 0x2e>; | |
| clock-names = "xo"; | |
| phandle = <0x2d6>; | |
| cx-uV-uA = <0x180 0x186a0>; | |
| mx-uV-uA = <0x180 0x186a0>; | |
| glink-edge { | |
| qcom,remote-pid = <0x01>; | |
| interrupts = <0x02 0x00 0x01>; | |
| interrupt-parent = <0x13b>; | |
| mbox-names = "mpss_smem"; | |
| transport = "smem"; | |
| label = "modem"; | |
| mboxes = <0x13b 0x02 0x00>; | |
| qcom,glink-label = "mpss"; | |
| qcom,modem_ds { | |
| qcom,intents = <0x4000 0x02>; | |
| qcom,glink-channels = "DS"; | |
| }; | |
| qcom,modem_qrtr { | |
| qcom,low-latency; | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| }; | |
| }; | |
| clock-controller@3d90000 { | |
| vdd_mx-supply = <0x125>; | |
| #clock-cells = <0x01>; | |
| clocks = <0x45 0x00 0x24 0x21 0x24 0x22 0x24 0x24>; | |
| reg-name = "cc_base"; | |
| reg = <0x3d90000 0xa000>; | |
| compatible = "qcom,ravelin-gpucc\0syscon"; | |
| clock-names = "bi_tcxo\0gpll0_out_main\0gpll0_out_main_div\0gcc_gpu_snoc_dvm_gfx_clk"; | |
| phandle = <0x23>; | |
| vdd_cx-supply = <0x124>; | |
| #reset-cells = <0x01>; | |
| }; | |
| va_core_clk { | |
| qcom,codec-ext-clk-src = <0x02>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x307>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x473>; | |
| }; | |
| tpdm@10844000 { | |
| coresight-name = "coresight-tpdm-lpass"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10844000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4a>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x226>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4c>; | |
| phandle = <0x8b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-q6-spdif-sec-tx { | |
| compatible = "qcom,msm-dai-q6-spdif"; | |
| phandle = <0x3e5>; | |
| qcom,msm-dai-q6-dev-id = <0x5003>; | |
| }; | |
| qcom,msm-dai-q6 { | |
| compatible = "qcom,msm-dai-q6"; | |
| qcom,msm-dai-q6-afe-proxy-tx-1 { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3ba>; | |
| qcom,msm-dai-q6-dev-id = <0xf2>; | |
| }; | |
| qcom,msm-dai-q6-proxy-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3bb>; | |
| qcom,msm-dai-q6-dev-id = <0x2002>; | |
| }; | |
| qcom,msm-dai-q6-sb-7-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3ac>; | |
| qcom,msm-dai-q6-dev-id = <0x400f>; | |
| qcom,msm-dai-q6-slim-dev-id = <0x00>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b7>; | |
| qcom,msm-dai-q6-dev-id = <0x8004>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b6>; | |
| qcom,msm-dai-q6-dev-id = <0x8003>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b4>; | |
| qcom,msm-dai-q6-dev-id = <0xf1>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b8>; | |
| qcom,msm-dai-q6-dev-id = <0x8005>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3af>; | |
| qcom,msm-dai-q6-dev-id = <0x3001>; | |
| }; | |
| qcom,msm-dai-q6-usb-audio-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3bd>; | |
| qcom,msm-dai-q6-dev-id = <0x7000>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b5>; | |
| qcom,msm-dai-q6-dev-id = <0xf0>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-2-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b9>; | |
| qcom,msm-dai-q6-dev-id = <0x8002>; | |
| }; | |
| qcom,msm-dai-q6-usb-audio-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3be>; | |
| qcom,msm-dai-q6-dev-id = <0x7001>; | |
| }; | |
| qcom,msm-dai-q6-sb-7-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3ab>; | |
| qcom,msm-dai-q6-dev-id = <0x400e>; | |
| qcom,msm-dai-q6-slim-dev-id = <0x00>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b0>; | |
| qcom,msm-dai-q6-dev-id = <0x3004>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b1>; | |
| qcom,msm-dai-q6-dev-id = <0x3005>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3ae>; | |
| qcom,msm-dai-q6-dev-id = <0x3000>; | |
| }; | |
| qcom,msm-dai-q6-sb-8-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3ad>; | |
| qcom,msm-dai-q6-dev-id = <0x4011>; | |
| qcom,msm-dai-q6-slim-dev-id = <0x00>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b2>; | |
| qcom,msm-dai-q6-dev-id = <0xe0>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3b3>; | |
| qcom,msm-dai-q6-dev-id = <0xe1>; | |
| }; | |
| qcom,msm-dai-q6-proxy-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3bc>; | |
| qcom,msm-dai-q6-dev-id = <0x2003>; | |
| }; | |
| }; | |
| funnel@10d03000 { | |
| coresight-name = "coresight-funnel-ddr_dl0"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10d03000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x24f>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x96>; | |
| source = <0x97>; | |
| phandle = <0xbb>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x92>; | |
| source = <0x93>; | |
| phandle = <0xb9>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x94>; | |
| source = <0x95>; | |
| phandle = <0xba>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x91>; | |
| phandle = <0x56>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x90>; | |
| phandle = <0x55>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x8f>; | |
| phandle = <0x8e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| modem_etm0 { | |
| qcom,inst-id = <0x02>; | |
| coresight-name = "coresight-modem-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| atid = <0x24 0x25>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x72>; | |
| phandle = <0xa7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-quat-rx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9130>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9030>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3d6>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-quat-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9030>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3d7>; | |
| }; | |
| }; | |
| qcom,pmu { | |
| reg-names = "pmu-base"; | |
| reg = <0x17d09300 0x300>; | |
| compatible = "qcom,pmu"; | |
| phandle = <0x2c7>; | |
| qcom,pmu-events-tbl = <0x08 0xff 0xff 0x02 0x11 0xff 0xff 0x00 0x17 0xff 0xff 0xff 0x2a 0xff 0xff 0xff 0x4005 0xc0 0xff 0xff>; | |
| }; | |
| tmc@1004f000 { | |
| qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; | |
| coresight-name = "coresight-tmc-etr1"; | |
| clocks = <0x31>; | |
| csr-atid-offset = <0x108>; | |
| csr-irqctrl-offset = <0x70>; | |
| reg-names = "tmc-base"; | |
| byte-cntr-name = "byte-cntr1"; | |
| coresight-csr = <0x10d>; | |
| reg = <0x1004f000 0x1000>; | |
| interrupts = <0x00 0x10d 0x01>; | |
| interrupt-names = "byte-cntr-irq"; | |
| dma-coherent; | |
| compatible = "arm,primecell"; | |
| byte-cntr-class-name = "coresight-tmc-etr1-stream"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x26e>; | |
| arm,scatter-gather; | |
| iommus = <0x2f 0x500 0x00>; | |
| arm,primecell-periphid = <0xbb961>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10f>; | |
| phandle = <0x10c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gpio5_pwm { | |
| qcom,fan-fg-gpio = <0x126 0x34 0x00>; | |
| gpio5-pwm-state = <0x01>; | |
| qcom,fan-en-gpio = <0x126 0x12 0x00>; | |
| pwms = <0x418 0x00 0x186a0>; | |
| compatible = "gpio5-pwm"; | |
| gpio5-pwm-duty-ns = <0x2710>; | |
| pinctrl-names = "default"; | |
| gpio5-pwm-period-ns = <0xc350>; | |
| pinctrl-0 = <0x419 0x2f6>; | |
| }; | |
| power-controller@c300000 { | |
| #clock-cells = <0x00>; | |
| #power-domain-cells = <0x01>; | |
| reg = <0xc300000 0x400>; | |
| interrupts = <0x00 0x00 0x01>; | |
| interrupt-parent = <0x13b>; | |
| compatible = "qcom,ravelin-aoss-qmp"; | |
| phandle = <0x31>; | |
| mboxes = <0x13b 0x00 0x00>; | |
| }; | |
| bt_wcn6750 { | |
| qcom,bt-vdd-rfa2-supply = <0x1ee>; | |
| qcom,bt-vdd-aon-supply = <0x1ed>; | |
| qcom,bt-vdd-rfa2-config = <0x1312d0 0x14a140 0x00 0x01>; | |
| qcom,bt-sw-ctrl-gpio = <0x126 0x38 0x00>; | |
| qcom,wl-reset-gpio = <0x126 0x2b 0x00>; | |
| qcom,bt-vdd-aon-config = <0xcf850 0x111700 0x00 0x01>; | |
| qcom,bt-vdd-rfa1-config = <0x1c5200 0x1f20c0 0x00 0x01>; | |
| qcom,bt-reset-gpio = <0x126 0x27 0x00>; | |
| status = "disabled"; | |
| qcom,bt-vdd-io-supply = <0x127>; | |
| compatible = "qcom,wcn6750-bt"; | |
| pinctrl-names = "default"; | |
| qcom,bt-vdd-dig-config = <0xc3500 0x111700 0x00 0x01>; | |
| qcom,bt-vdd-io-config = <0x1b7740 0x1b7740 0x00 0x01>; | |
| phandle = <0x34d>; | |
| pinctrl-0 = <0x1f0>; | |
| qcom,bt-vdd-dig-supply = <0x1ed>; | |
| }; | |
| slim@3340000 { | |
| dmas = <0x12d 0x03 0x12d 0x04>; | |
| dma-names = "rx\0tx"; | |
| #size-cells = <0x00>; | |
| reg-names = "ctrl\0slimbus_remote_mem"; | |
| #address-cells = <0x01>; | |
| reg = <0x3340000 0x2c000 0x326a000 0x1000>; | |
| interrupts = <0x00 0xa3 0x04>; | |
| status = "ok"; | |
| compatible = "qcom,slim-ngd-v1.5.0"; | |
| phandle = <0x2b6>; | |
| qcom,apps-ch-pipes = <0x00>; | |
| qcom,ea-pc = <0x440>; | |
| ngd@1 { | |
| #size-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| reg = <0x01>; | |
| btfmslim-driver { | |
| reg = <0x01 0x00>; | |
| compatible = "slim217,221"; | |
| phandle = <0x2b7>; | |
| }; | |
| }; | |
| }; | |
| tpdm@12861000 { | |
| coresight-name = "coresight-tpdm-apss"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x12861000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x42>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x242>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x6f>; | |
| phandle = <0xb2>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10813000 { | |
| coresight-name = "coresight-cti-mss_vq6_cti"; | |
| clocks = <0x31>; | |
| reg = <0x10813000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x285>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| tpdm@10800000 { | |
| coresight-name = "coresight-tpdm-modem-0"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10800000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x43>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x243>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x70>; | |
| phandle = <0xa4>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cpufreq-hw-debug { | |
| compatible = "qcom,cpufreq-hw-epss-debug"; | |
| qcom,freq-hw-domain = <0x07 0x00 0x07 0x01>; | |
| }; | |
| qcom,gdsc@1b6020 { | |
| regulator-name = "gcc_venus_gdsc"; | |
| reg = <0x1b6020 0x04>; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x31f>; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| }; | |
| tpdm@109c1000 { | |
| coresight-name = "coresight-tpdm-dl-south-cmb"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x109c1000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4f>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0xcf>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x6a>; | |
| phandle = <0xca>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10C48000 { | |
| coresight-name = "coresight-tpdm-dl-west"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10c48000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x65>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x239>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x62>; | |
| phandle = <0xde>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-pcm-loopback-low-latency { | |
| qcom,msm-pcm-loopback-low-latency; | |
| compatible = "qcom,msm-pcm-loopback"; | |
| phandle = <0x38a>; | |
| }; | |
| qcom,gdsc@3d99108 { | |
| qcom,clk-dis-wait-val = <0x08>; | |
| clocks = <0x24 0x20>; | |
| regulator-name = "gpu_cc_cx_gdsc"; | |
| reg = <0x3d99108 0x04>; | |
| status = "ok"; | |
| hw-ctrl-addr = <0x18d>; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| clock-names = "ahb_clk"; | |
| phandle = <0x22>; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| }; | |
| funnel@1080c000 { | |
| coresight-name = "coresight-funnel-modem_q6"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x1080c000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x255>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xab>; | |
| phandle = <0xae>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xaa>; | |
| phandle = <0x74>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xa9>; | |
| phandle = <0xa8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-imem@146aa000 { | |
| #size-cells = <0x01>; | |
| ranges = <0x00 0x146aa000 0x1000>; | |
| #address-cells = <0x01>; | |
| compatible = "qcom,msm-imem"; | |
| kaslr_offset@6d0 { | |
| reg = <0x6d0 0x0c>; | |
| compatible = "qcom,msm-imem-kaslr_offset"; | |
| }; | |
| boot_stats@6b0 { | |
| reg = <0x6b0 0x20>; | |
| compatible = "qcom,msm-imem-boot_stats"; | |
| }; | |
| restart_reason@65c { | |
| reg = <0x65c 0x04>; | |
| compatible = "qcom,msm-imem-restart_reason"; | |
| }; | |
| diag_dload@c8 { | |
| reg = <0xc8 0xc8>; | |
| compatible = "qcom,msm-imem-diag-dload"; | |
| }; | |
| pil@94c { | |
| reg = <0x94c 0xc8>; | |
| compatible = "qcom,pil-reloc-info"; | |
| }; | |
| dload_type@1c { | |
| reg = <0x1c 0x04>; | |
| compatible = "qcom,msm-imem-dload-type"; | |
| }; | |
| pil@6dc { | |
| reg = <0x6dc 0x04>; | |
| compatible = "qcom,msm-imem-pil-disable-timeout"; | |
| }; | |
| mem_dump_table@10 { | |
| reg = <0x10 0x08>; | |
| compatible = "qcom,msm-imem-mem_dump_table"; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-pri-tx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9101>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9001>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3cc>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-pri-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9001>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3cd>; | |
| }; | |
| }; | |
| ssusb@a600000 { | |
| extcon = <0x3e>; | |
| interrupts-extended = <0x3b 0x0e 0x01 0x01 0x00 0x82 0x04 0x3b 0x11 0x04 0x3b 0x0f 0x01>; | |
| qcom,core-clk-rate = <0x7f28155>; | |
| resets = <0x24 0x12>; | |
| clocks = <0x24 0x71 0x24 0x13 0x24 0x0b 0x24 0x73 0x24 0x76>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| reg-names = "core_base"; | |
| usb-role-switch; | |
| #address-cells = <0x01>; | |
| qcom,core-clk-rate-hs = <0x3f940ab>; | |
| reg = <0xa600000 0x100000>; | |
| reset-names = "core_reset"; | |
| interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq"; | |
| USB3_GDSC-supply = <0x3a>; | |
| qcom,use-pdc-interrupts; | |
| interconnect-names = "usb-ddr\0usb-ipa\0ddr-usb"; | |
| interconnects = <0x3c 0x36 0x29 0x200 0x3c 0x36 0x3d 0x20f 0x25 0x02 0x3d 0x226>; | |
| compatible = "qcom,dwc-usb3-msm"; | |
| clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk"; | |
| qcom,num-gsi-evt-buffs = <0x03>; | |
| phandle = <0x223>; | |
| qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>; | |
| qcom,pm-qos-latency = <0x02>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x41>; | |
| phandle = <0x163>; | |
| }; | |
| }; | |
| dwc3@a600000 { | |
| dr_mode = "otg"; | |
| usb-phy = <0x3f 0x40>; | |
| maximum-speed = "super-speed"; | |
| snps,dis_u3_susphy_quirk; | |
| qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; | |
| snps,dis-u1-entry-quirk; | |
| snps,dis_u2_susphy_quirk; | |
| snps,has-lpm-erratum; | |
| snps,is-utmi-l1-suspend; | |
| snps,hird-threshold = [00]; | |
| usb-role-switch; | |
| reg = <0xa600000 0xd800>; | |
| interrupts = <0x00 0x85 0x04>; | |
| tx-fifo-resize; | |
| dma-coherent; | |
| compatible = "snps,dwc3"; | |
| snps,dis-u2-entry-quirk; | |
| qcom,iommu-dma = "atomic"; | |
| iommus = <0x2f 0x540 0x00>; | |
| }; | |
| }; | |
| qcom,chd { | |
| qcom,chd-percpu-info = <0x1a 0x17800058 0x17800060 0x1b 0x17810058 0x17810060 0x1c 0x17820058 0x17820060 0x1d 0x17830058 0x17830060 0x1e 0x17840058 0x17840060 0x1f 0x17850058 0x17850060 0x20 0x17860058 0x17860060 0x21 0x17870058 0x17870060>; | |
| compatible = "qcom,core-hang-detect"; | |
| label = "core"; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_2_out { | |
| qcom,smem-states = <0x1f9 0x00>; | |
| qcom,smem-state-names = "rdbg-smp2p-out"; | |
| compatible = "qcom,smp2p-interrupt-rdbg-2-out"; | |
| }; | |
| qcom,spmi-debug@10b14000 { | |
| qcom,fuse-enable-bit = <0x12>; | |
| clocks = <0x31>; | |
| #size-cells = <0x00>; | |
| reg-names = "core\0fuse"; | |
| #address-cells = <0x02>; | |
| reg = <0x10b14000 0x60 0x221c8784 0x04>; | |
| depends-on-supply = <0x162>; | |
| compatible = "qcom,spmi-pmic-arb-debug"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2dc>; | |
| qcom,pm8010-debug@4 { | |
| qcom,can-sleep; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| reg = <0x04 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| }; | |
| qcom,pm6450-debug@1 { | |
| qcom,can-sleep; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| reg = <0x01 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| }; | |
| qcom,pm7250b-debug@9 { | |
| qcom,can-sleep; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| reg = <0x09 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| }; | |
| qcom,pmk8350-debug@0 { | |
| qcom,can-sleep; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| reg = <0x00 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| }; | |
| qcom,pm7250b-debug@8 { | |
| qcom,can-sleep; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| reg = <0x08 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| }; | |
| qcom,pmg1110-debug@6 { | |
| qcom,can-sleep; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| reg = <0x06 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| }; | |
| }; | |
| qcom,smp2p-wpss { | |
| qcom,smem = <0x269 0x268>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x0d>; | |
| interrupts = <0x18 0x02 0x01>; | |
| interrupt-parent = <0x13b>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x13b 0x18 0x02>; | |
| qcom,smp2p-wlan-2-in { | |
| qcom,entry-name = "wlan_soc_wake"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1f7>; | |
| }; | |
| qcom,smp2p-wlan-2-out { | |
| qcom,entry-name = "wlan_soc_wake"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x1f4>; | |
| }; | |
| qcom,smp2p-wlan-1-out { | |
| qcom,entry-name = "wlan"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x1f3>; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x15e>; | |
| }; | |
| qcom,smp2p-wlan-1-in { | |
| qcom,entry-name = "wlan"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1f6>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x15d>; | |
| }; | |
| qcom,smp2p-wlan-3-out { | |
| qcom,entry-name = "wlan_ep_power_save"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x1f5>; | |
| }; | |
| }; | |
| qcom,gdsc@18d054 { | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"; | |
| reg = <0x18d054 0x04>; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x2d>; | |
| parent-supply = <0x124>; | |
| }; | |
| qcom,gdsc@1b6044 { | |
| regulator-name = "gcc_vcodec0_gdsc"; | |
| reg = <0x1b6044 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x320>; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| }; | |
| tpdm@1082c000 { | |
| coresight-name = "coresight-tpdm-gcc"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x1082c000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x231>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5a>; | |
| phandle = <0xbe>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tz-log@146AA720 { | |
| tmecrashdump-address-offset = <0x808a0000>; | |
| reg = <0x146aa720 0x3000>; | |
| qcom,hyplog-enabled; | |
| status = "ok"; | |
| hyplog-address-offset = <0x410>; | |
| compatible = "qcom,tz-log"; | |
| rmlog-size = <0x2000>; | |
| hyplog-size-offset = <0x414>; | |
| phandle = <0x2bf>; | |
| rmlog-address = <0x804d8000>; | |
| }; | |
| qcom,gdsc@ad10004 { | |
| regulator-name = "cam_cc_bps_gdsc"; | |
| reg = <0xad10004 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x30f>; | |
| qcom,retain-regs; | |
| }; | |
| qcom,scmi { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| shmem = <0x12f>; | |
| mbox-names = "tx"; | |
| compatible = "arm,scmi"; | |
| phandle = <0x2b9>; | |
| mboxes = <0x12e 0x00>; | |
| protocol@86 { | |
| #clock-cells = <0x01>; | |
| reg = <0x86>; | |
| phandle = <0x2ba>; | |
| }; | |
| protocol@81 { | |
| #clock-cells = <0x01>; | |
| reg = <0x81>; | |
| phandle = <0x2bb>; | |
| }; | |
| protocol@88 { | |
| #clock-cells = <0x01>; | |
| reg = <0x88>; | |
| phandle = <0x2bd>; | |
| }; | |
| protocol@84 { | |
| #clock-cells = <0x01>; | |
| reg = <0x84>; | |
| phandle = <0x2bc>; | |
| }; | |
| }; | |
| qcom,kgsl-3d0@3d00000 { | |
| qcom,gpu-qdss-stm = <0x161c0000 0x40000>; | |
| qcom,enable-ca-jump; | |
| qcom,ubwc-mode = <0x02>; | |
| qcom,min-access-length = <0x20>; | |
| vdd-supply = <0x32>; | |
| qcom,ca-busy-penalty = <0x2ee0>; | |
| resets = <0x23 0x09>; | |
| qcom,bus-table-ddr7 = <0x00 0xbebc2 0x209a8e 0x2dc6c0 0x3c9e30 0x50a524 0x5caf6a 0x65ce03 0x7f22ff>; | |
| qcom,no-nap; | |
| regulator-names = "vddcx\0vdd"; | |
| clocks = <0x23 0x13 0x23 0x08 0x24 0x14 0x24 0x23 0x23 0x1c 0x23 0x18 0x31 0x23 0x08 0x23 0x1c 0x23 0x18 0x24 0x23 0x24 0x24 0x23 0x02>; | |
| reg-names = "kgsl_3d0_reg_memory\0cx_dbgc\0gmu_wrapper\0cx_misc\0qdss_gfx"; | |
| qcom,tzone-names = "gpuss"; | |
| nvmem-cells = <0x33>; | |
| reg = <0x3d00000 0x40000 0x3d61000 0x800 0x3d7d000 0x1d000 0x3d9e000 0x1000 0x10900000 0x80000>; | |
| reset-names = "freq_limiter_irq_clear"; | |
| interrupts = <0x00 0x12c 0x04 0x00 0x11e 0x04>; | |
| interrupt-names = "kgsl_3d0_irq\0freq_limiter_irq"; | |
| interconnect-names = "gpu_icc_path"; | |
| status = "ok"; | |
| interconnects = <0x25 0x15 0x29 0x200>; | |
| vddcx-supply = <0x22>; | |
| compatible = "qcom,kgsl-3d0\0qcom,adreno-gpu-gen6-3-26-0"; | |
| qcom,gpu-model = "AdrenoA12v1"; | |
| qcom,bus-table-ddr8 = <0x00 0xbebc2 0x1ae1b6 0x209a8e 0x28973c 0x2dc6c0 0x5caf6a 0x65ce03 0x7cb163 0xa3140c 0xbe7f17>; | |
| clock-names = "core_clk\0gmu_clk\0mem_clk\0mem_iface_clk\0hub_cx_int_clk\0smmu_vote\0apb_pclk\0gpu_cc_cx_gmu\0gpu_cc_hub_cx_int\0gpu_cc_hlos1_vote_gpu_smmu\0gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb"; | |
| phandle = <0x179>; | |
| #cooling-cells = <0x02>; | |
| qcom,chipid = <0x6010300>; | |
| nvmem-cell-names = "speed_bin"; | |
| zap-shader { | |
| memory-region = <0x34>; | |
| }; | |
| qcom,gpu-pwrlevel-bins { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| compatible = "qcom,gpu-pwrlevel-bins"; | |
| qcom,gpu-pwrlevels-3 { | |
| qcom,initial-pwrlevel = <0x03>; | |
| qcom,speed-bin = <0xa2>; | |
| qcom,ca-target-pwrlevel = <0x02>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x80>; | |
| qcom,gpu-freq = <0x1dcd6500>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,bus-max-ddr7 = <0x05>; | |
| qcom,bus-freq-ddr8 = <0x06>; | |
| qcom,bus-min-ddr8 = <0x05>; | |
| reg = <0x02>; | |
| qcom,bus-max-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr7 = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x100>; | |
| qcom,gpu-freq = <0x2d98f940>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x0a>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| reg = <0x00>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x40>; | |
| qcom,gpu-freq = <0x1443fd00>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,bus-max-ddr7 = <0x04>; | |
| qcom,bus-freq-ddr8 = <0x03>; | |
| qcom,bus-min-ddr8 = <0x03>; | |
| reg = <0x03>; | |
| qcom,bus-max-ddr8 = <0x06>; | |
| qcom,bus-freq-ddr7 = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0xc0>; | |
| qcom,gpu-freq = <0x240f9140>; | |
| qcom,bus-min-ddr7 = <0x04>; | |
| qcom,bus-max-ddr7 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x07>; | |
| qcom,bus-min-ddr8 = <0x06>; | |
| reg = <0x01>; | |
| qcom,bus-max-ddr8 = <0x08>; | |
| qcom,bus-freq-ddr7 = <0x05>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-1 { | |
| qcom,initial-pwrlevel = <0x06>; | |
| qcom,speed-bin = <0xd5>; | |
| qcom,ca-target-pwrlevel = <0x05>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x140>; | |
| qcom,gpu-freq = <0x32a9f880>; | |
| qcom,bus-min-ddr7 = <0x07>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x08>; | |
| reg = <0x02>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x1a0>; | |
| qcom,gpu-freq = <0x3c336080>; | |
| qcom,bus-min-ddr7 = <0x08>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x0a>; | |
| qcom,bus-min-ddr8 = <0x0a>; | |
| reg = <0x00>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x100>; | |
| qcom,gpu-freq = <0x2d98f940>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| reg = <0x03>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-freq-ddr7 = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x180>; | |
| qcom,gpu-freq = <0x38ec24c0>; | |
| qcom,bus-min-ddr7 = <0x08>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x09>; | |
| reg = <0x01>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,level = <0x40>; | |
| qcom,gpu-freq = <0x1443fd00>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,bus-max-ddr7 = <0x04>; | |
| qcom,bus-freq-ddr8 = <0x03>; | |
| qcom,bus-min-ddr8 = <0x03>; | |
| reg = <0x06>; | |
| qcom,bus-max-ddr8 = <0x06>; | |
| qcom,bus-freq-ddr7 = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,level = <0x80>; | |
| qcom,gpu-freq = <0x1dcd6500>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,bus-max-ddr7 = <0x05>; | |
| qcom,bus-freq-ddr8 = <0x06>; | |
| qcom,bus-min-ddr8 = <0x05>; | |
| reg = <0x05>; | |
| qcom,bus-max-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr7 = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0xc0>; | |
| qcom,gpu-freq = <0x240f9140>; | |
| qcom,bus-min-ddr7 = <0x04>; | |
| qcom,bus-max-ddr7 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x07>; | |
| qcom,bus-min-ddr8 = <0x06>; | |
| reg = <0x04>; | |
| qcom,bus-max-ddr8 = <0x08>; | |
| qcom,bus-freq-ddr7 = <0x05>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-0 { | |
| qcom,initial-pwrlevel = <0x06>; | |
| qcom,speed-bin = <0x00>; | |
| qcom,ca-target-pwrlevel = <0x05>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x140>; | |
| qcom,gpu-freq = <0x32a9f880>; | |
| qcom,bus-min-ddr7 = <0x07>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x08>; | |
| reg = <0x02>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x1a0>; | |
| qcom,gpu-freq = <0x3c336080>; | |
| qcom,bus-min-ddr7 = <0x08>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x0a>; | |
| qcom,bus-min-ddr8 = <0x0a>; | |
| reg = <0x00>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0x100>; | |
| qcom,gpu-freq = <0x2d98f940>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| reg = <0x03>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-freq-ddr7 = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x180>; | |
| qcom,gpu-freq = <0x38ec24c0>; | |
| qcom,bus-min-ddr7 = <0x08>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x09>; | |
| reg = <0x01>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,level = <0x40>; | |
| qcom,gpu-freq = <0x1443fd00>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,bus-max-ddr7 = <0x04>; | |
| qcom,bus-freq-ddr8 = <0x03>; | |
| qcom,bus-min-ddr8 = <0x03>; | |
| reg = <0x06>; | |
| qcom,bus-max-ddr8 = <0x06>; | |
| qcom,bus-freq-ddr7 = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,level = <0x80>; | |
| qcom,gpu-freq = <0x1dcd6500>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,bus-max-ddr7 = <0x05>; | |
| qcom,bus-freq-ddr8 = <0x06>; | |
| qcom,bus-min-ddr8 = <0x05>; | |
| reg = <0x05>; | |
| qcom,bus-max-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr7 = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0xc0>; | |
| qcom,gpu-freq = <0x240f9140>; | |
| qcom,bus-min-ddr7 = <0x04>; | |
| qcom,bus-max-ddr7 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x07>; | |
| qcom,bus-min-ddr8 = <0x06>; | |
| reg = <0x04>; | |
| qcom,bus-max-ddr8 = <0x08>; | |
| qcom,bus-freq-ddr7 = <0x05>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-2 { | |
| qcom,initial-pwrlevel = <0x05>; | |
| qcom,speed-bin = <0xc9>; | |
| qcom,ca-target-pwrlevel = <0x04>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,level = <0x100>; | |
| qcom,gpu-freq = <0x2d98f940>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| reg = <0x02>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-freq-ddr7 = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,level = <0x180>; | |
| qcom,gpu-freq = <0x38ec24c0>; | |
| qcom,bus-min-ddr7 = <0x08>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x0a>; | |
| qcom,bus-min-ddr8 = <0x09>; | |
| reg = <0x00>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,level = <0xc0>; | |
| qcom,gpu-freq = <0x240f9140>; | |
| qcom,bus-min-ddr7 = <0x04>; | |
| qcom,bus-max-ddr7 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x07>; | |
| qcom,bus-min-ddr8 = <0x06>; | |
| reg = <0x03>; | |
| qcom,bus-max-ddr8 = <0x08>; | |
| qcom,bus-freq-ddr7 = <0x05>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,level = <0x140>; | |
| qcom,gpu-freq = <0x32a9f880>; | |
| qcom,bus-min-ddr7 = <0x07>; | |
| qcom,bus-max-ddr7 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x08>; | |
| reg = <0x01>; | |
| qcom,bus-max-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr7 = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,level = <0x40>; | |
| qcom,gpu-freq = <0x1443fd00>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,bus-max-ddr7 = <0x04>; | |
| qcom,bus-freq-ddr8 = <0x03>; | |
| qcom,bus-min-ddr8 = <0x03>; | |
| reg = <0x05>; | |
| qcom,bus-max-ddr8 = <0x06>; | |
| qcom,bus-freq-ddr7 = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,level = <0x80>; | |
| qcom,gpu-freq = <0x1dcd6500>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,bus-max-ddr7 = <0x05>; | |
| qcom,bus-freq-ddr8 = <0x06>; | |
| qcom,bus-min-ddr8 = <0x05>; | |
| reg = <0x04>; | |
| qcom,bus-max-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr7 = <0x04>; | |
| }; | |
| }; | |
| }; | |
| qcom,gpu-mempools { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| compatible = "qcom,gpu-mempools"; | |
| qcom,gpu-mempool@1 { | |
| qcom,mempool-page-size = <0x2000>; | |
| qcom,mempool-reserved = <0x400>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-mempool@4 { | |
| qcom,mempool-page-size = <0x40000>; | |
| qcom,mempool-reserved = <0x50>; | |
| reg = <0x04>; | |
| }; | |
| qcom,gpu-mempool@5 { | |
| qcom,mempool-page-size = <0x100000>; | |
| qcom,mempool-reserved = <0x20>; | |
| reg = <0x05>; | |
| }; | |
| qcom,gpu-mempool@2 { | |
| qcom,mempool-page-size = <0x10000>; | |
| qcom,mempool-reserved = <0x100>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-mempool@3 { | |
| qcom,mempool-page-size = <0x20000>; | |
| qcom,mempool-reserved = <0x80>; | |
| reg = <0x03>; | |
| }; | |
| qcom,gpu-mempool@0 { | |
| qcom,mempool-page-size = <0x1000>; | |
| qcom,mempool-reserved = <0x800>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,qupv3_1_geni_se@ac0000 { | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| reg = <0xac0000 0x2000>; | |
| interconnect-names = "qup-core\0snoc-llcc\0qup-ddr"; | |
| status = "ok"; | |
| interconnects = <0x190 0x25 0x190 0x241 0x191 0x0c 0x25 0x234 0x3c 0x08 0x29 0x200>; | |
| dma-coherent; | |
| compatible = "qcom,qupv3-geni-se"; | |
| phandle = <0x1c0>; | |
| qcom,iommu-dma = "fastmap"; | |
| iommus = <0x2f 0x403 0x00>; | |
| qcom,msm-bus,num-paths = <0x03>; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| }; | |
| funnel@10b04000 { | |
| coresight-name = "coresight-funnel-aoss"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10b04000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x267>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x101>; | |
| phandle = <0x103>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x100>; | |
| phandle = <0xf7>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0xfe>; | |
| phandle = <0x88>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xff>; | |
| phandle = <0xfd>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@128f0000 { | |
| coresight-name = "coresight-cti-apss_cti1"; | |
| clocks = <0x31>; | |
| reg = <0x128f0000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x281>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,msm-pcm { | |
| qcom,msm-pcm-dsp-id = <0x00>; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| phandle = <0x37a>; | |
| }; | |
| clock-controller@100000 { | |
| vdd_mx-supply = <0x125>; | |
| #clock-cells = <0x01>; | |
| clocks = <0x45 0x00 0x130 0x131 0x132 0x133 0x134 0x48>; | |
| reg-name = "cc_base"; | |
| reg = <0x100000 0x1f4200>; | |
| compatible = "qcom,ravelin-gcc\0syscon"; | |
| clock-names = "bi_tcxo\0sleep_clk\0pcie_0_pipe_clk\0ufs_phy_rx_symbol_0_clk\0ufs_phy_rx_symbol_1_clk\0ufs_phy_tx_symbol_0_clk\0usb3_phy_wrapper_gcc_usb30_pipe_clk"; | |
| phandle = <0x24>; | |
| vdd_cx-supply = <0x124>; | |
| qcom,critical-devices = <0x341>; | |
| #reset-cells = <0x01>; | |
| }; | |
| hwversion { | |
| vendor,hwver-low-gpio = <0x126 0x5f 0x00>; | |
| status = "okay"; | |
| vendor,hwver-low0-gpio = <0x126 0x5a 0x00>; | |
| compatible = "vendor-hwver"; | |
| pinctrl-names = "default"; | |
| vendor,hwver-hig-gpio = <0x126 0x53 0x00>; | |
| pinctrl-0 = <0x2f7>; | |
| vendor,hwver-mid-gpio = <0x126 0x66 0x00>; | |
| }; | |
| qcom,msm-quin-auxpcm { | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| qcom,msm-auxpcm-interface = "quinary"; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| phandle = <0x3c5>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| }; | |
| funnel@12810000 { | |
| coresight-name = "coresight-funnel-apss"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x12810000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x258>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xb6>; | |
| phandle = <0xc7>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0xb5>; | |
| phandle = <0xb3>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb4>; | |
| phandle = <0x119>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@10803000 { | |
| coresight-name = "coresight-tpda-modem"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x10803000 0x1000>; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x00 0x40>; | |
| qcom,tpda-atid = <0x43>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x253>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa6>; | |
| phandle = <0xad>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xa4>; | |
| phandle = <0x70>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xa5>; | |
| phandle = <0x71>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cnss-qca6490@b0000000 { | |
| wlan-ant-switch-supply = <0x1ef>; | |
| vdd-wlan-rfa2-supply = <0x1ee>; | |
| qcom,bt-en-gpio = <0x126 0x27 0x00>; | |
| qcom,vreg_ipa = "g7i"; | |
| qcom,vdd-wlan-dig-config = <0xc3500 0x111700 0x00 0x00 0x01>; | |
| vdd-wlan-io-supply = <0x127>; | |
| qcom,wlan-ramdump-dynamic = <0x420000>; | |
| qcom,wlan; | |
| vdd-wlan-aon-supply = <0x1ed>; | |
| use-pm-domain; | |
| reg-names = "smmu_iova_ipa"; | |
| qcom,vdd-wlan-rfa2-config = <0x1312d0 0x14a140 0x00 0x00 0x01>; | |
| wlan-en-gpio = <0x126 0x2b 0x00>; | |
| qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x1b8a00 0x1d4c 0x1b8a00 0x7530 0x1b8a00 0x186a0 0x1b8a00 0x2ab98 0x5eec00 0x1d4c 0x216600>; | |
| reg = <0xb0000000 0x10000>; | |
| cnss-enable-self-recovery; | |
| qcom,vdd-wlan-rfa1-config = <0x1b7740 0x1f20c0 0x00 0x00 0x01>; | |
| qcom,vdd-wlan-aon-config = <0xcf850 0x111700 0x00 0x00 0x01>; | |
| interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; | |
| qcom,wlan-rc-num = <0x00>; | |
| status = "disabled"; | |
| interconnects = <0x2c 0x2f 0x2c 0x23a 0x25 0x1c 0x29 0x200>; | |
| pinctrl-1 = <0x1ec>; | |
| qcom,bus-bw-cfg-count = <0x07>; | |
| compatible = "qcom,cnss-qca6490"; | |
| pinctrl-names = "wlan_en_active\0wlan_en_sleep"; | |
| qcom,icc-path-count = <0x02>; | |
| qcom,vdd-wlan-io-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; | |
| phandle = <0x348>; | |
| pinctrl-0 = <0x1eb>; | |
| qcom,wlan-cbc-enabled; | |
| mboxes = <0x02 0x00>; | |
| qcom,wlan-ant-switch-config = <0x2ab980 0x2ab980 0x00 0x00 0x01>; | |
| qcom,same-dt-multi-dev; | |
| vdd-wlan-dig-supply = <0x1ed>; | |
| qcom,xo-clk-gpio = <0x126 0x6c 0x00>; | |
| }; | |
| cti@1098b000 { | |
| coresight-name = "coresight-cti-turing_q6_cti"; | |
| clocks = <0x31>; | |
| reg = <0x1098b000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x27a>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,msm-lsm-client { | |
| compatible = "qcom,msm-lsm-client"; | |
| phandle = <0x3aa>; | |
| }; | |
| tpda@10cc4000 { | |
| coresight-name = "coresight-tpda-tmess"; | |
| qcom,dsb-elem-size = <0x01 0x20>; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x10cc4000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x00 0x40 0x01 0x40 0x02 0x20>; | |
| qcom,tpda-atid = <0x55>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x251>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa1>; | |
| phandle = <0xa2>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xa0>; | |
| phandle = <0x78>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x9e>; | |
| phandle = <0x76>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x9f>; | |
| phandle = <0x77>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,ipcc@ed18000 { | |
| #mbox-cells = <0x02>; | |
| reg = <0xed18000 0x1000>; | |
| interrupts = <0x00 0xe5 0x04>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x03>; | |
| compatible = "qcom,ipcc"; | |
| phandle = <0x13b>; | |
| }; | |
| dsi_panel_pwr_supply_lcd { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| phandle = <0x44b>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| qcom,supply-disable-load = <0x64>; | |
| reg = <0x01>; | |
| qcom,supply-name = "avdd"; | |
| qcom,supply-post-off-sleep = <0x0a>; | |
| qcom,supply-pre-off-sleep = <0x0a>; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| qcom,supply-post-on-sleep = <0x0a>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-max-voltage = <0x1e8480>; | |
| qcom,supply-disable-load = <0x50>; | |
| reg = <0x00>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-post-on-sleep = <0x0a>; | |
| qcom,supply-enable-load = <0x30d40>; | |
| }; | |
| }; | |
| sdhci@7C4000 { | |
| qcom,ice-clk-rates = <0x11e1a300 0x5f5e100>; | |
| vdd-io-supply = <0x2a5>; | |
| mmc-hs400-enhanced-strobe; | |
| vdd-supply = <0x2ae>; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| qcom,dll-hsr-list = <0xf642c 0x00 0x01 0x2c010800 0x80040868>; | |
| resets = <0x24 0x0f>; | |
| cap-mmc-hw-reset; | |
| clocks = <0x24 0x58 0x24 0x59 0x24 0x5b>; | |
| mmc-hs400-1_8v; | |
| qcom,vdd-current-level = <0x00 0x8b290>; | |
| reg-names = "hc\0cqhci\0cqhci_ice\0cqhci_ice_hwkm"; | |
| no-sdio; | |
| supports-cqe; | |
| reg = <0x7c4000 0x1000 0x7c5000 0x1000 0x7c8000 0x8000 0x7d0000 0x9000>; | |
| reset-names = "core_reset"; | |
| interrupts = <0x00 0x87 0x04 0x00 0x89 0x04>; | |
| qcom,vdd-io-lpm-sup; | |
| non-removable; | |
| interrupt-names = "hc_irq\0pwr_irq"; | |
| bus-width = <0x08>; | |
| interconnect-names = "sdhc-ddr\0cpu-sdhc"; | |
| status = "ok"; | |
| interconnects = <0x3c 0x33 0x29 0x200 0x25 0x02 0x3d 0x220>; | |
| pinctrl-1 = <0x2ff>; | |
| qcom,scaling-lower-bus-speed-mode = "DDR52"; | |
| dma-coherent; | |
| compatible = "qcom,sdhci-msm-v5"; | |
| pinctrl-names = "default\0sleep"; | |
| qcom,vdd-io-current-level = <0x00 0x4f588>; | |
| operating-points-v2 = <0x149>; | |
| no-sd; | |
| clock-names = "iface\0core\0ice_core"; | |
| phandle = <0x2cc>; | |
| qcom,devfreq,freq-table = <0x2faf080 0xbebc200>; | |
| qcom,iommu-dma = "fastmap"; | |
| pinctrl-0 = <0x2fe>; | |
| mmc-ddr-1_8v; | |
| iommus = <0x2f 0x560 0x00>; | |
| qcom,vdd-io-always-on; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| mmc-hs200-1_8v; | |
| qos1 { | |
| mask = <0x3f>; | |
| vote = <0x2c>; | |
| }; | |
| qos0 { | |
| mask = <0x03>; | |
| vote = <0x2c>; | |
| }; | |
| }; | |
| thermal-sensor@c263000 { | |
| #qcom,sensors = <0x10>; | |
| reg = <0xc263000 0x1ff 0xc222000 0x1ff>; | |
| interrupts = <0x00 0x1fa 0x04 0x00 0x1fc 0x04 0x00 0x1f4 0x01>; | |
| interrupt-names = "uplow\0critical\0cold"; | |
| compatible = "qcom,tsens-v2"; | |
| phandle = <0x165>; | |
| #thermal-sensor-cells = <0x01>; | |
| }; | |
| qcom,gdsc@ad11004 { | |
| regulator-name = "cam_cc_ipe_0_gdsc"; | |
| reg = <0xad11004 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x313>; | |
| qcom,retain-regs; | |
| }; | |
| funnel@12800000 { | |
| coresight-name = "coresight-funnel-etm"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x12800000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x292>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x119>; | |
| phandle = <0xb4>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x11d>; | |
| phandle = <0x114>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x11c>; | |
| phandle = <0x113>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x121>; | |
| phandle = <0x118>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x11f>; | |
| phandle = <0x116>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x120>; | |
| phandle = <0x117>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x11a>; | |
| phandle = <0x111>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x11e>; | |
| phandle = <0x115>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x11b>; | |
| phandle = <0x112>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qrng@10c3000 { | |
| reg = <0x10c3000 0x1000>; | |
| compatible = "qcom,msm-rng"; | |
| qcom,no-clock-support; | |
| qcom,no-qrng-config; | |
| phandle = <0x2c6>; | |
| }; | |
| qcom,gdsc@18d05c { | |
| regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; | |
| reg = <0x18d05c 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x326>; | |
| }; | |
| qcom,gdsc@19e000 { | |
| regulator-name = "gcc_pcie_1_phy_gdsc"; | |
| reg = <0x19e000 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x31c>; | |
| qcom,retain-regs; | |
| qcom,collapse-vote = <0x18b 0x04>; | |
| }; | |
| qcom,kgsl-iommu@3da0000 { | |
| reg = <0x3da0000 0x40000>; | |
| vddcx-supply = <0x22>; | |
| compatible = "qcom,kgsl-smmu-v2"; | |
| phandle = <0x21f>; | |
| gfx3d_user { | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x220>; | |
| qcom,iommu-dma = "disabled"; | |
| iommus = <0x30 0x00 0x400>; | |
| }; | |
| gfx3d_secure { | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x221>; | |
| qcom,iommu-dma = "disabled"; | |
| iommus = <0x30 0x02 0x400>; | |
| }; | |
| }; | |
| thermal-ddr-freq-table { | |
| qcom,freq-tbl = <0x1fef00>; | |
| phandle = <0x1f8>; | |
| }; | |
| qcom,mem-buf-msgq { | |
| compatible = "qcom,mem-buf-msgq"; | |
| }; | |
| qcom,msm-sec-auxpcm { | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| qcom,msm-auxpcm-interface = "secondary"; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| phandle = <0x3c2>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| }; | |
| qcom,msm-dai-q6-spdif-pri-rx { | |
| compatible = "qcom,msm-dai-q6-spdif"; | |
| phandle = <0x3e2>; | |
| qcom,msm-dai-q6-dev-id = <0x5000>; | |
| }; | |
| tpdm@10b0d000 { | |
| coresight-name = "coresight-tpdm-swao-1"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10b0d000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x22d>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x53>; | |
| phandle = <0xfc>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@b220000 { | |
| reg-names = "pdc-interrupt-base\0apps-shared-spi-cfg"; | |
| reg = <0xb220000 0x30000 0x174000f0 0x64>; | |
| interrupt-parent = <0x01>; | |
| qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x1f 0x7d 0x3f 0x01 0x7e 0x2cc 0x0c>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| compatible = "qcom,ravelin-pdc\0qcom,pdc"; | |
| phandle = <0x3b>; | |
| }; | |
| i2c@980000 { | |
| dmas = <0x1a1 0x00 0x00 0x03 0x40 0x00 0x1a1 0x01 0x00 0x03 0x40 0x00>; | |
| qcom,wrapper-core = <0x19a>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x3e 0x24 0x54 0x24 0x55>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x980000 0x4000>; | |
| interrupts = <0x00 0x259 0x04>; | |
| status = "ok"; | |
| pinctrl-1 = <0x1a0>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x334>; | |
| pinctrl-0 = <0x19e 0x19f>; | |
| htrl@3c { | |
| reg = <0x3c>; | |
| htr3212l,dv-en1 = <0x126 0x06 0x00>; | |
| compatible = "kona,htr3212l"; | |
| }; | |
| }; | |
| ipcc-self-ping-cdsp { | |
| interrupts-extended = <0x13b 0x06 0x03 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x330>; | |
| mboxes = <0x13b 0x06 0x03>; | |
| }; | |
| ddrqos-freq-table { | |
| qcom,freq-tbl = <0x00 0x01>; | |
| phandle = <0x142>; | |
| }; | |
| qcom,msm-eud@88e0000 { | |
| clocks = <0x24 0x19>; | |
| reg-names = "eud_base\0eud_mode_mgr2"; | |
| reg = <0x88e0000 0x2000 0x88e2000 0x1000>; | |
| interrupts = <0x0b 0x04>; | |
| interrupt-parent = <0x3b>; | |
| interrupt-names = "eud_irq"; | |
| status = "ok"; | |
| compatible = "qcom,msm-eud"; | |
| clock-names = "eud_clkref_clk"; | |
| phandle = <0x3e>; | |
| qcom,secure-eud-en; | |
| }; | |
| qcom,wdt@17410000 { | |
| qcom,bark-time = <0x2af8>; | |
| qcom,ipi-ping; | |
| qcom,wakeup-enable; | |
| reg-names = "wdt-base"; | |
| reg = <0x17410000 0x1000>; | |
| interrupts = <0x00 0x00 0x04 0x00 0x01 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,msm-watchdog"; | |
| qcom,pet-time = <0x2490>; | |
| phandle = <0x294>; | |
| }; | |
| cti@128e0000 { | |
| coresight-name = "coresight-cti-apss_cti0"; | |
| clocks = <0x31>; | |
| reg = <0x128e0000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x280>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| interconnect@16e0000 { | |
| qcom,bcm-voter-names = "hlos"; | |
| clocks = <0x24 0x5d>; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x16e0000 0x13080>; | |
| compatible = "qcom,ravelin-aggre1_noc"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x14a>; | |
| }; | |
| clocks { | |
| sleep_clk { | |
| #clock-cells = <0x00>; | |
| clock-output-names = "sleep_clk"; | |
| clock-frequency = <0x7d00>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x130>; | |
| }; | |
| ufs_phy_rx_symbol_0_clk { | |
| #clock-cells = <0x00>; | |
| clock-output-names = "ufs_phy_rx_symbol_0_clk"; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x132>; | |
| }; | |
| xo_board { | |
| #clock-cells = <0x00>; | |
| clock-output-names = "xo_board"; | |
| clock-frequency = <0x493e000>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x2c2>; | |
| }; | |
| usb3_phy_wrapper_gcc_usb30_pipe_clk { | |
| #clock-cells = <0x00>; | |
| clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x48>; | |
| }; | |
| pcie_0_pipe_clk { | |
| #clock-cells = <0x00>; | |
| clock-output-names = "pcie_0_pipe_clk"; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x131>; | |
| }; | |
| ufs_phy_tx_symbol_0_clk { | |
| #clock-cells = <0x00>; | |
| clock-output-names = "ufs_phy_tx_symbol_0_clk"; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x134>; | |
| }; | |
| ufs_phy_rx_symbol_1_clk { | |
| #clock-cells = <0x00>; | |
| clock-output-names = "ufs_phy_rx_symbol_1_clk"; | |
| clock-frequency = <0x3e8>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x133>; | |
| }; | |
| }; | |
| qcom,gdsc@aaf8084 { | |
| regulator-name = "video_cc_mvs0c_gdsc"; | |
| reg = <0xaaf8084 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x32b>; | |
| qcom,retain-regs; | |
| }; | |
| clock-controller@ade0000 { | |
| vdd_mx-supply = <0x125>; | |
| #clock-cells = <0x01>; | |
| clocks = <0x45 0x00 0x24 0x0d>; | |
| reg-name = "cc_base"; | |
| reg = <0xade0000 0x20000>; | |
| compatible = "qcom,ravelin-camcc\0syscon"; | |
| clock-names = "bi_tcxo\0iface"; | |
| phandle = <0x135>; | |
| vdd_cx-supply = <0x124>; | |
| #reset-cells = <0x01>; | |
| }; | |
| i2c@98c000 { | |
| dmas = <0x1a1 0x00 0x03 0x03 0x40 0x00 0x1a1 0x01 0x03 0x03 0x40 0x00>; | |
| qcom,wrapper-core = <0x19a>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x44 0x24 0x54 0x24 0x55>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x98c000 0x4000>; | |
| interrupts = <0x00 0x25c 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1ac>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x337>; | |
| pinctrl-0 = <0x1aa 0x1ab>; | |
| }; | |
| tpdm@10900000 { | |
| coresight-name = "coresight-tpdm-gpu"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10900000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4f>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x22e>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x57>; | |
| phandle = <0x89>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| wsa2_spkr_en1_pinctrl { | |
| status = "disabled"; | |
| pinctrl-1 = <0x2f8>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x47f>; | |
| pinctrl-0 = <0x2f9>; | |
| }; | |
| tpdm@10ac1000 { | |
| coresight-name = "coresight-tpdm-dlct2-cmb"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x10ac1000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4f>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x23f>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x68>; | |
| phandle = <0xd7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interconnect@0 { | |
| qcom,bcm-voter-names = "hlos"; | |
| #interconnect-cells = <0x01>; | |
| compatible = "qcom,ravelin-clk_virt"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x190>; | |
| }; | |
| display_gpio_regulator@2 { | |
| enable-active-high; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-boot-on; | |
| regulator-name = "display_panel_extvdd"; | |
| regulator-enable-ramp-delay = <0xe9>; | |
| compatible = "qti-regulator-fixed"; | |
| regulator-min-microvolt = <0x124f80>; | |
| pinctrl-names = "default"; | |
| gpio = <0x414 0x0c 0x00>; | |
| phandle = <0x415>; | |
| qcom,proxy-consumer-enable; | |
| pinctrl-0 = <0x416>; | |
| proxy-supply = <0x415>; | |
| }; | |
| snoc { | |
| coresight-name = "coresight-snoc"; | |
| compatible = "qcom,coresight-dummy"; | |
| qcom,dummy-source; | |
| atid = <0x7d>; | |
| phandle = <0x23a>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x63>; | |
| phandle = <0xeb>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,spmi@c42d000 { | |
| qcom,ee = <0x00>; | |
| interrupts-extended = <0x3b 0x01 0x04>; | |
| cell-index = <0x00>; | |
| qcom,bus-id = <0x00>; | |
| #size-cells = <0x00>; | |
| reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; | |
| #address-cells = <0x02>; | |
| reg = <0xc42d000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4c0000 0x10000>; | |
| interrupt-names = "periph_irq"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x04>; | |
| compatible = "qcom,spmi-pmic-arb"; | |
| qcom,channel = <0x00>; | |
| phandle = <0x162>; | |
| qcom,pm8010@4 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x04 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| phandle = <0x430>; | |
| pm8010-e-temp-alarm@2400 { | |
| reg = <0x2400>; | |
| interrupts = <0x04 0x24 0x00 0x03>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| phandle = <0x402>; | |
| #thermal-sensor-cells = <0x00>; | |
| }; | |
| }; | |
| qcom,pm7250b@2 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x08 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| phandle = <0x43b>; | |
| vadc@3100 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| #io-channel-cells = <0x01>; | |
| io-channel-ranges; | |
| reg = <0x3100>; | |
| interrupts = <0x08 0x31 0x00 0x01>; | |
| interrupt-names = "eoc-int-en-set"; | |
| compatible = "qcom,spmi-adc5"; | |
| phandle = <0x409>; | |
| usb_in_v_div_16@8 { | |
| reg = <0x08>; | |
| qcom,pre-scaling = <0x01 0x10>; | |
| label = "usb_in_v_div_16"; | |
| }; | |
| bat_therm@4a { | |
| reg = <0x4a>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "bat_therm"; | |
| }; | |
| vph_pwr@83 { | |
| reg = <0x83>; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| label = "vph_pwr"; | |
| }; | |
| bat_therm_30k@2a { | |
| reg = <0x2a>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "bat_therm_30k"; | |
| }; | |
| bat_id@4b { | |
| reg = <0x4b>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "bat_id"; | |
| }; | |
| usb_in_i_uv@7 { | |
| reg = <0x07>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "usb_in_i_uv"; | |
| }; | |
| die_temp@2 { | |
| reg = <0x06>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "die_temp"; | |
| }; | |
| chg_temp@9 { | |
| reg = <0x09>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "chg_temp"; | |
| }; | |
| pm7250b_usb_conn_therm { | |
| reg = <0x4f>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pm7250b_usb_conn_therm"; | |
| }; | |
| bat_therm_400k@6a { | |
| reg = <0x6a>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "bat_therm_400k"; | |
| }; | |
| smb1390_therm@e { | |
| reg = <0x0e>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "smb1390_therm"; | |
| }; | |
| vref_1p25@1 { | |
| reg = <0x01>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "vref_1p25"; | |
| }; | |
| ref_gnd@0 { | |
| reg = <0x00>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "ref_gnd"; | |
| }; | |
| pm7250b_charger_skin_therm { | |
| reg = <0x4d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pm7250b_charger_skin_therm"; | |
| }; | |
| vbat_sns@84 { | |
| reg = <0x84>; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| label = "vbat_sns"; | |
| }; | |
| chg_sbux@99 { | |
| reg = <0x99>; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| label = "chg_sbux"; | |
| }; | |
| mid_chg_div6@1e { | |
| reg = <0x1e>; | |
| qcom,pre-scaling = <0x01 0x06>; | |
| label = "chg_mid"; | |
| }; | |
| }; | |
| qcom,power-on@800 { | |
| reg = <0x800>; | |
| compatible = "qcom,qpnp-power-on"; | |
| }; | |
| pinctrl@c000 { | |
| reg = <0xc000>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| compatible = "qcom,pm7250b-gpio"; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| phandle = <0x414>; | |
| display_panel_supply_ctrl { | |
| display_panel_vddio_default { | |
| drive-push-pull; | |
| power-source = <0x00>; | |
| input-disable; | |
| bias-disable; | |
| pins = "gpio11"; | |
| qcom,drive-strength = <0x02>; | |
| output-enable; | |
| function = "normal"; | |
| phandle = <0x457>; | |
| }; | |
| display_panel_extvdd_default { | |
| power-source = <0x00>; | |
| input-disable; | |
| bias-disable; | |
| pins = "gpio12"; | |
| qcom,drive-strength = <0x02>; | |
| output-enable; | |
| function = "normal"; | |
| phandle = <0x416>; | |
| }; | |
| }; | |
| }; | |
| bcl@1d00 { | |
| reg = <0x1d00>; | |
| interrupts = <0x08 0x1d 0x00 0x01 0x08 0x1d 0x01 0x01 0x08 0x1d 0x02 0x01>; | |
| interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; | |
| compatible = "qcom,bcl-v5"; | |
| phandle = <0x40b>; | |
| #thermal-sensor-cells = <0x01>; | |
| }; | |
| qcom,qpnp-smb5 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,thermal-mitigation = <0x5265c0 0x44aa20 0x3d0900 0x3567e0 0x2dc6c0 0x2625a0 0x1e8480 0x16e360 0xf4240 0x7a120>; | |
| status = "disabled"; | |
| depends-on-supply = <0x409>; | |
| compatible = "qcom,pm7250b-smb5"; | |
| phandle = <0x43c>; | |
| #cooling-cells = <0x02>; | |
| qcom,dc@1400 { | |
| reg = <0x1400>; | |
| interrupts = <0x02 0x14 0x01 0x03 0x02 0x14 0x02 0x03 0x02 0x14 0x03 0x03 0x02 0x14 0x04 0x03 0x02 0x14 0x05 0x03 0x02 0x14 0x06 0x01 0x02 0x14 0x07 0x01>; | |
| interrupt-names = "dcin-vashdn\0dcin-uv\0dcin-ov\0dcin-plugin\0dcin-revi\0dcin-pon\0dcin-en"; | |
| }; | |
| qcom,misc@1600 { | |
| reg = <0x1600>; | |
| interrupts = <0x02 0x16 0x00 0x01 0x02 0x16 0x01 0x01 0x02 0x16 0x02 0x01 0x02 0x16 0x03 0x01 0x02 0x16 0x04 0x03 0x02 0x16 0x05 0x01 0x02 0x16 0x06 0x01 0x02 0x16 0x07 0x01>; | |
| interrupt-names = "wdog-snarl\0wdog-bark\0aicl-fail\0aicl-done\0smb-en\0imp-trigger\0temp-change\0temp-change-smb"; | |
| }; | |
| qcom,chgr@1000 { | |
| reg = <0x1000>; | |
| interrupts = <0x02 0x10 0x00 0x01 0x02 0x10 0x01 0x01 0x02 0x10 0x02 0x01 0x02 0x10 0x03 0x01 0x02 0x10 0x04 0x01 0x02 0x10 0x05 0x01 0x02 0x10 0x06 0x01 0x02 0x10 0x07 0x01>; | |
| interrupt-names = "chgr-error\0chg-state-change\0step-chg-state-change\0step-chg-soc-update-fail\0step-chg-soc-update-req\0fg-fvcal-qualified\0vph-alarm\0vph-drop-prechg"; | |
| }; | |
| qcom,chg-sdam@b000 { | |
| reg = <0xb000>; | |
| }; | |
| qcom,batif@1200 { | |
| reg = <0x1200>; | |
| interrupts = <0x02 0x12 0x00 0x01 0x02 0x12 0x02 0x03 0x02 0x12 0x03 0x03 0x02 0x12 0x04 0x03 0x02 0x12 0x05 0x03 0x02 0x12 0x06 0x03 0x02 0x12 0x07 0x03>; | |
| interrupt-names = "bat-temp\0bat-ov\0bat-low\0bat-therm-or-id-missing\0bat-terminal-missing\0buck-oc\0vph-ov"; | |
| }; | |
| qcom,usb@1300 { | |
| reg = <0x1300>; | |
| interrupts = <0x02 0x13 0x00 0x03 0x02 0x13 0x01 0x03 0x02 0x13 0x02 0x03 0x02 0x13 0x03 0x03 0x02 0x13 0x04 0x03 0x02 0x13 0x05 0x03 0x02 0x13 0x06 0x01 0x02 0x13 0x07 0x01>; | |
| interrupt-names = "usbin-collapse\0usbin-vashdn\0usbin-uv\0usbin-ov\0usbin-plugin\0usbin-revi-change\0usbin-src-change\0usbin-icl-change"; | |
| }; | |
| qcom,typec@1500 { | |
| reg = <0x1500>; | |
| interrupts = <0x02 0x15 0x00 0x01 0x02 0x15 0x01 0x01 0x02 0x15 0x02 0x01 0x02 0x15 0x03 0x01 0x02 0x15 0x04 0x01 0x02 0x15 0x05 0x01 0x02 0x15 0x06 0x01 0x02 0x15 0x07 0x01>; | |
| interrupt-names = "typec-or-rid-detect-change\0typec-vpd-detect\0typec-cc-state-change\0typec-vconn-oc\0typec-vbus-change\0typec-attach-detach\0typec-legacy-cable-detect\0typec-try-snk-src-detect"; | |
| }; | |
| qcom,dcdc@1100 { | |
| reg = <0x1100>; | |
| interrupts = <0x02 0x11 0x00 0x01 0x02 0x11 0x01 0x01 0x02 0x11 0x02 0x01 0x02 0x11 0x03 0x03 0x02 0x11 0x04 0x03 0x02 0x11 0x05 0x03 0x02 0x11 0x06 0x01 0x02 0x11 0x07 0x03>; | |
| interrupt-names = "otg-fail\0otg-oc-disable-sw\0otg-oc-hiccup\0bsm-active\0high-duty-cycle\0input-current-limiting\0concurrent-mode-disable\0switcher-power-ok"; | |
| }; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| qcom,temperature-threshold-set = <0x01>; | |
| io-channel-names = "thermal"; | |
| reg = <0x2400>; | |
| interrupts = <0x08 0x24 0x00 0x03>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| phandle = <0x40a>; | |
| io-channels = <0x409 0x06>; | |
| #thermal-sensor-cells = <0x00>; | |
| }; | |
| adc_tm@3500 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x3500>; | |
| interrupts = <0x08 0x35 0x00 0x01>; | |
| interrupt-names = "threshold"; | |
| compatible = "qcom,adc-tm5"; | |
| phandle = <0x411>; | |
| io-channels = <0x409 0x4f 0x409 0x4d>; | |
| #thermal-sensor-cells = <0x01>; | |
| pm7250b_usb_conn_therm { | |
| reg = <0x4f>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| }; | |
| pm7250b_charger_skin_therm { | |
| reg = <0x4d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| }; | |
| }; | |
| qcom,usb-pdphy@1700 { | |
| reg = <0x1700 0x100>; | |
| interrupts = <0x02 0x17 0x00 0x01 0x02 0x17 0x01 0x01 0x02 0x17 0x02 0x01 0x02 0x17 0x03 0x01 0x02 0x17 0x04 0x01 0x02 0x17 0x05 0x01 0x02 0x17 0x06 0x01 0x02 0x17 0x07 0x01>; | |
| interrupt-names = "sig-tx\0sig-rx\0msg-tx\0msg-rx\0msg-tx-failed\0msg-tx-discarded\0msg-rx-discarded\0fr-swap"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-pdphy"; | |
| phandle = <0x43f>; | |
| qcom,default-sink-caps = <0x1388 0xbb8 0x2328 0xbb8 0x2ee0 0x8ca>; | |
| }; | |
| qpnp,qg { | |
| qcom,vbatt-empty-cold-mv = <0xbb8>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,vbatt-cutoff-mv = <0xc80>; | |
| status = "disabled"; | |
| compatible = "qcom,pm7250b-qg"; | |
| qcom,s3-entry-fifo-length = <0x02>; | |
| qcom,vbatt-low-cold-mv = <0xe74>; | |
| phandle = <0x43d>; | |
| qcom,vbatt-low-mv = <0xce4>; | |
| qcom,vbatt-empty-mv = <0xbb8>; | |
| qcom,qgauge@4800 { | |
| reg = <0x4800>; | |
| interrupts = <0x02 0x48 0x00 0x03 0x02 0x48 0x01 0x03 0x02 0x48 0x02 0x01 0x02 0x48 0x03 0x01 0x02 0x48 0x04 0x01>; | |
| interrupt-names = "qg-batt-missing\0qg-vbat-low\0qg-vbat-empty\0qg-fifo-done\0qg-good-ocv"; | |
| status = "okay"; | |
| }; | |
| qcom,qg-sdam@b100 { | |
| reg = <0xb100>; | |
| status = "okay"; | |
| }; | |
| }; | |
| clock-controller@5b00 { | |
| #clock-cells = <0x01>; | |
| clocks = <0x45 0x00>; | |
| reg = <0x5b00>; | |
| clock-output-names = "pm7250b_div_clk1"; | |
| status = "disabled"; | |
| compatible = "qcom,spmi-clkdiv"; | |
| qcom,num-clkdivs = <0x01>; | |
| clock-names = "xo"; | |
| phandle = <0x43e>; | |
| }; | |
| bcl-soc { | |
| compatible = "qcom,msm-bcl-soc"; | |
| phandle = <0x40c>; | |
| #thermal-sensor-cells = <0x00>; | |
| }; | |
| }; | |
| qcom,pm6450@1 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x01 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| pinctrl@8800 { | |
| reg = <0x8800>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| compatible = "qcom,pm6450-gpio"; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| phandle = <0x42b>; | |
| fan_pwm_default { | |
| power-source = <0x00>; | |
| input-disable; | |
| bias-disable; | |
| pins = "gpio7"; | |
| qcom,drive-strength = <0x02>; | |
| output-enable; | |
| function = "func1"; | |
| phandle = <0x419>; | |
| }; | |
| lcd_backlight_ctrl { | |
| lcd_backlight_en_default { | |
| power-source = <0x00>; | |
| input-disable; | |
| bias-disable; | |
| pins = "gpio6"; | |
| qcom,drive-strength = <0x02>; | |
| output-enable; | |
| function = "normal"; | |
| phandle = <0x42d>; | |
| }; | |
| lcd_backlight_pwm_default { | |
| power-source = <0x01>; | |
| input-disable; | |
| bias-disable; | |
| qcom,drive-strength = <0x02>; | |
| output-enable; | |
| function = "func1"; | |
| phandle = <0x42c>; | |
| }; | |
| }; | |
| pa_therm2 { | |
| pa_therm2_default { | |
| pins = "gpio4"; | |
| bias-high-impedance; | |
| phandle = <0x3fc>; | |
| }; | |
| }; | |
| quiet_therm { | |
| quiet_therm_default { | |
| pins = "gpio2"; | |
| bias-high-impedance; | |
| phandle = <0x3f9>; | |
| }; | |
| }; | |
| rear_cam_flash_therm { | |
| rear_cam_flash_therm_default { | |
| pins = "gpio5"; | |
| bias-high-impedance; | |
| phandle = <0x3fb>; | |
| }; | |
| }; | |
| }; | |
| qcom,temp-alarm@a00 { | |
| reg = <0xa00>; | |
| interrupts = <0x01 0x0a 0x00 0x03>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| phandle = <0x3ff>; | |
| #thermal-sensor-cells = <0x00>; | |
| }; | |
| qcom,pwms@e800 { | |
| reg-names = "lpg-base"; | |
| reg = <0xe800>; | |
| status = "ok"; | |
| compatible = "qcom,pwm-lpg"; | |
| #pwm-cells = <0x02>; | |
| phandle = <0x418>; | |
| qcom,num-lpg-channels = <0x01>; | |
| }; | |
| }; | |
| qcom,pm7250b@3 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x09 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| phandle = <0x440>; | |
| qcom,vibrator@5300 { | |
| qcom,vib-ldo-volt-uv = <0x2dc6c0>; | |
| reg = <0x5300>; | |
| compatible = "qcom,qpnp-vibrator-ldo"; | |
| qcom,disable-overdrive; | |
| phandle = <0x441>; | |
| }; | |
| }; | |
| qcom,pmk8350@0 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| phandle = <0x41d>; | |
| adc_tm@3400 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x3400>; | |
| interrupts = <0x00 0x34 0x00 0x01>; | |
| interrupt-names = "threshold"; | |
| compatible = "qcom,adc-tm7"; | |
| phandle = <0x403>; | |
| io-channels = <0x3fe 0x44 0x3fe 0x14a 0x3fe 0x45 0x3fe 0x14d 0x3fe 0x14c 0x3fe 0x46>; | |
| #thermal-sensor-cells = <0x01>; | |
| pmk8350_xo_therm { | |
| reg = <0x44>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| }; | |
| pm6450_pa2_therm { | |
| reg = <0x14c>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| }; | |
| pm6450_quiet_therm { | |
| reg = <0x14a>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| }; | |
| pm6450_rear_cam_flash_therm { | |
| reg = <0x14d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| }; | |
| pmk8350_pa1_therm { | |
| reg = <0x46>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| }; | |
| pmk8350_wide_rfc_therm { | |
| reg = <0x45>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| }; | |
| }; | |
| vadc@3100 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| #io-channel-cells = <0x01>; | |
| io-channel-ranges; | |
| reg = <0x3100>; | |
| interrupts = <0x00 0x31 0x00 0x01>; | |
| interrupt-names = "eoc-int-en-set"; | |
| compatible = "qcom,spmi-adc7"; | |
| pinctrl-names = "default"; | |
| phandle = <0x3fe>; | |
| pinctrl-0 = <0x3f9 0x3fa 0x3fb 0x3fc 0x3fd>; | |
| pmk8350_ref_gnd { | |
| reg = <0x00>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pmk8350_ref_gnd"; | |
| }; | |
| pmk8350_xo_therm { | |
| reg = <0x44>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pmk8350_xo_therm"; | |
| }; | |
| pmk8350_pa_therm1 { | |
| reg = <0x46>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pmk8350_pa_therm1"; | |
| }; | |
| pmk8350_vref_1p25 { | |
| reg = <0x01>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pmk8350_vref_1p25"; | |
| }; | |
| pm6450_quiet_therm { | |
| reg = <0x14a>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pm6450_quiet_therm"; | |
| }; | |
| pm6450_ref_gnd { | |
| reg = <0x100>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pm6450_ref_gnd"; | |
| }; | |
| pm6450_pa_therm2 { | |
| reg = <0x14c>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pm6450_pa_therm2"; | |
| }; | |
| pm6450_rear_cam_flash_therm { | |
| reg = <0x14d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pm6450_rear_cam_flash_therm"; | |
| }; | |
| pmk8350_die_temp { | |
| reg = <0x03>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pmk8350_die_temp"; | |
| }; | |
| pm6450_vref_1p25 { | |
| reg = <0x101>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pm6450_vref_1p25"; | |
| }; | |
| pm6450_die_temp { | |
| reg = <0x103>; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pm6450_die_temp"; | |
| }; | |
| pmk8350_wide_rfc_therm { | |
| reg = <0x45>; | |
| qcom,hw-settle-time = <0xc8>; | |
| qcom,ratiometric; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| label = "pmk8350_wide_rfc_therm"; | |
| }; | |
| }; | |
| sdam@7400 { | |
| reg = <0x7400>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x401>; | |
| }; | |
| pinctrl@b000 { | |
| reg = <0xb000>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| compatible = "qcom,pmk8350-gpio"; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| phandle = <0x429>; | |
| wide_rfc_therm { | |
| wide_rfc_therm_default { | |
| pins = "gpio1"; | |
| bias-high-impedance; | |
| phandle = <0x3fa>; | |
| }; | |
| }; | |
| pa_therm1 { | |
| pa_therm1_default { | |
| pins = "gpio2"; | |
| bias-high-impedance; | |
| phandle = <0x3fd>; | |
| }; | |
| }; | |
| }; | |
| sdam@8600 { | |
| #size-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| reg = <0x8600>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x425>; | |
| scaling@bf { | |
| bits = <0x00 0x02>; | |
| reg = <0xbf 0x01>; | |
| phandle = <0x426>; | |
| }; | |
| }; | |
| sdam@8400 { | |
| reg = <0x8400>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x423>; | |
| }; | |
| pon_hlos@1300 { | |
| qcom,log-kpd-event; | |
| reg-names = "pon_hlos\0pon_pbs"; | |
| reg = <0x1300 0x800>; | |
| compatible = "qcom,pm8998-pon"; | |
| phandle = <0x41e>; | |
| pwrkey { | |
| interrupts = <0x00 0x13 0x07 0x03>; | |
| linux,code = <0x74>; | |
| compatible = "qcom,pmk8350-pwrkey"; | |
| }; | |
| resin { | |
| interrupts = <0x00 0x13 0x06 0x03>; | |
| linux,code = <0x72>; | |
| compatible = "qcom,pmk8350-resin"; | |
| }; | |
| }; | |
| sdam@7000 { | |
| #size-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| reg = <0x7000>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x41f>; | |
| ufs_dev@94 { | |
| bits = <0x00 0x00>; | |
| reg = <0x94 0x01>; | |
| phandle = <0x41a>; | |
| }; | |
| }; | |
| sdam@9800 { | |
| reg = <0x9800>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x427>; | |
| }; | |
| rtc@6100 { | |
| reg-names = "rtc\0alarm"; | |
| reg = <0x6100 0x6200>; | |
| interrupts = <0x00 0x62 0x01 0x01>; | |
| compatible = "qcom,pmk8350-rtc"; | |
| phandle = <0x42a>; | |
| }; | |
| sdam@7c00 { | |
| reg = <0x7c00>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x421>; | |
| }; | |
| sdam@9d00 { | |
| reg = <0x9d00>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x428>; | |
| }; | |
| sdam@7100 { | |
| #size-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| reg = <0x7100>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x420>; | |
| restart@48 { | |
| bits = <0x01 0x07>; | |
| reg = <0x48 0x01>; | |
| phandle = <0x400>; | |
| }; | |
| }; | |
| sdam@7d00 { | |
| reg = <0x7d00>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x422>; | |
| }; | |
| sdam@8500 { | |
| reg = <0x8500>; | |
| compatible = "qcom,spmi-sdam"; | |
| phandle = <0x424>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-pcm-low-latency { | |
| qcom,latency-level = "regular"; | |
| qcom,msm-pcm-dsp-id = <0x01>; | |
| qcom,msm-pcm-low-latency; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| phandle = <0x37d>; | |
| }; | |
| etm5 { | |
| coresight-name = "coresight-etm5"; | |
| clocks = <0x31>; | |
| cpu = <0x1f>; | |
| qcom,skip-power-up; | |
| reg = <0x12540000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x06>; | |
| clock-names = "apb_pclk"; | |
| arm,primecell-periphid = <0xbb95d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x116>; | |
| phandle = <0x11f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,qmp-tme { | |
| priority = <0x00>; | |
| mbox-desc-offset = <0x00>; | |
| qcom,early-boot; | |
| qcom,remote-pid = <0x0e>; | |
| #mbox-cells = <0x01>; | |
| interrupts = <0x17 0x00 0x01>; | |
| interrupt-parent = <0x13b>; | |
| mbox-names = "tme_qmp"; | |
| compatible = "qcom,qmp-mbox"; | |
| phandle = <0x13e>; | |
| label = "tme"; | |
| mboxes = <0x13b 0x17 0x00>; | |
| }; | |
| tpdm@10d00000 { | |
| coresight-name = "coresight-tpdm-ddr"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10d00000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x95>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x55>; | |
| phandle = <0x90>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| audio_etm0 { | |
| qcom,inst-id = <0x05>; | |
| coresight-name = "coresight-audio-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| atid = <0x28>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4a>; | |
| phandle = <0x85>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@109ad000 { | |
| coresight-name = "coresight-cti-wcss1"; | |
| clocks = <0x31>; | |
| reg = <0x109ad000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x28d>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,ipa@3e00000 { | |
| qcom,smmu-fast-map; | |
| qcom,ipa-holb-monitor-max-cnt-11ad = <0x0a>; | |
| qcom,ee = <0x00>; | |
| qcom,interconnect,num-paths = <0x03>; | |
| qcom,use-ipa-tethering-bridge; | |
| qcom,svs = <0x124f80 0x00 0x124f80 0x2ab980 0x00 0x249f0>; | |
| qcom,rmnet-ctl-enable; | |
| clocks = <0x45 0x16>; | |
| qcom,ipa-hw-mode = <0x00>; | |
| reg-names = "ipa-base\0gsi-base"; | |
| pas-ids = <0x0f>; | |
| qcom,ulso-ip-id-max-linux-val = <0xffff>; | |
| qcom,nominal = <0x249f00 0x00 0x249f00 0x53ec60 0x00 0x61a80>; | |
| qcom,tx-napi; | |
| qcom,entire-ipa-block-size = <0x200000>; | |
| qcom,ipa-wdi3-over-gsi; | |
| qcom,wan-use-skb-page; | |
| qcom,max_num_smmu_cb = <0x04>; | |
| reg = <0x3e00000 0x84000 0x3e04000 0xfc000>; | |
| firmware-names = "ipa_fws"; | |
| interrupts = <0x00 0x28e 0x04 0x00 0x1b0 0x04>; | |
| qcom,ipa-cfg-offset = <0x140000>; | |
| qcom,platform-type = <0x01>; | |
| interrupt-names = "ipa-irq\0gsi-irq"; | |
| qcom,ipa-holb-monitor-max-cnt-usb = <0x0a>; | |
| qcom,ipa-hw-ver = <0x17>; | |
| interconnect-names = "ipa_to_llcc\0llcc_to_ebi1\0appss_to_ipa"; | |
| qcom,non-tn-collection-on-crash; | |
| qcom,mhi-event-ring-id-limits = <0x09 0x0b>; | |
| interconnects = <0x3c 0x27 0x25 0x234 0x29 0x03 0x29 0x200 0x25 0x02 0x3d 0x20f>; | |
| qcom,ulso-ip-id-min-linux-val = <0x00>; | |
| qcom,arm-smmu; | |
| compatible = "qcom,ipa"; | |
| qcom,lan-rx-napi; | |
| qcom,scaling-exceptions; | |
| qcom,svs2 = <0x00 0x00 0x00 0x1cfde0 0x00 0x12c00>; | |
| qcom,ipa-gpi-event-rp-ddr; | |
| qcom,ulso-supported; | |
| qcom,throughput-threshold = <0x258 0x9c4 0x1388>; | |
| memory-regions = <0x15f>; | |
| qcom,ulso-ip-id-min-windows-val = <0x00>; | |
| qcom,no-vote = <0x00 0x00 0x00 0x00 0x00 0x00>; | |
| clock-names = "core_clk"; | |
| qcom,ipa-gen-rx-cmn-temp-pool-sz-factor = <0x01>; | |
| phandle = <0x2d7>; | |
| qcom,ipa-ulso-wa; | |
| qcom,testbus-collection-on-crash; | |
| qcom,ulso-ip-id-max-windows-val = <0x7fff>; | |
| qcom,interconnect,num-cases = <0x05>; | |
| qcom,tx-poll; | |
| qcom,modem-cfg-emb-pipe-flt; | |
| qcom,ipa-gen-rx-cmn-page-pool-sz-factor = <0x02>; | |
| qcom,turbo = <0x36ee80 0x00 0x36ee80 0x53ec60 0x00 0x61a80>; | |
| qcom,ipa-holb-monitor-max-cnt-wlan = <0x0a>; | |
| qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO"; | |
| qcom,tx-wrapper-cache-max-size = <0x190>; | |
| qcom,use-64-bit-dma-mask; | |
| qcom,gfp-no-retry; | |
| qcom,register-collection-on-crash; | |
| qcom,ipa-holb-monitor-poll-period = <0x05>; | |
| qcom,ipa-endp-delay-wa-v2; | |
| ipa_smmu_11ad { | |
| qcom,shared-cb; | |
| qcom,iommu-group; | |
| dma-coherent; | |
| compatible = "qcom,ipa-smmu-11ad-cb"; | |
| phandle = <0x2db>; | |
| iommus = <0x2f 0x4a3 0x00>; | |
| }; | |
| qcom,smp2p_map_ipa_1_in { | |
| interrupts-extended = <0x161 0x00 0x00>; | |
| interrupt-names = "ipa-smp2p-in"; | |
| compatible = "qcom,smp2p-map-ipa-1-in"; | |
| }; | |
| qcom,smp2p_map_ipa_1_out { | |
| qcom,smem-states = <0x160 0x00>; | |
| qcom,smem-state-names = "ipa-smp2p-out"; | |
| compatible = "qcom,smp2p-map-ipa-1-out"; | |
| }; | |
| ipa_smmu_wlan { | |
| compatible = "qcom,ipa-smmu-wlan-cb"; | |
| phandle = <0x2d9>; | |
| qcom,iommu-dma = "atomic"; | |
| iommus = <0x2f 0x4a1 0x00>; | |
| }; | |
| ipa_smmu_ap { | |
| qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; | |
| qcom,ipa-q6-smem-size = <0xb000>; | |
| qcom,additional-mapping = <0x146a8000 0x146a8000 0x2000>; | |
| dma-coherent; | |
| compatible = "qcom,ipa-smmu-ap-cb"; | |
| phandle = <0x2d8>; | |
| qcom,iommu-dma = "atomic"; | |
| iommus = <0x2f 0x4a0 0x00>; | |
| }; | |
| ipa_smmu_uc { | |
| qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; | |
| compatible = "qcom,ipa-smmu-uc-cb"; | |
| phandle = <0x2da>; | |
| qcom,iommu-dma = "atomic"; | |
| iommus = <0x2f 0x4a2 0x00>; | |
| }; | |
| }; | |
| qcom,disp0-gdsc@af09000 { | |
| regulator-name = "disp0_cc_mdss_core_gdsc"; | |
| reg = <0xaf09000 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x189>; | |
| qcom,proxy-consumer-enable; | |
| qcom,retain-regs; | |
| proxy-supply = <0x189>; | |
| }; | |
| qseecom@c1700000 { | |
| qcom,appsbl-qseecom-support; | |
| qcom,disk-encrypt-pipe-pair = <0x02>; | |
| qcom,qsee-ce-hw-instance = <0x00>; | |
| qseecom_mem = <0x36>; | |
| user_contig_mem = <0x35>; | |
| qcom,commonlib64-loaded-by-uefi; | |
| qcom,qsee-reentrancy-support = <0x02>; | |
| qcom,hlos-ce-hw-instance = <0x00>; | |
| compatible = "qcom,qseecom"; | |
| memory-region = <0x36>; | |
| qcom,no-clock-support; | |
| phandle = <0x2c0>; | |
| qseecom_ta_mem = <0x37>; | |
| qcom,hlos-num-ce-hw-instances = <0x01>; | |
| }; | |
| qcom,gdsc@149004 { | |
| regulator-name = "gcc_usb30_prim_gdsc"; | |
| reg = <0x149004 0x04>; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x3a>; | |
| qcom,proxy-consumer-enable; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| proxy-supply = <0x3a>; | |
| }; | |
| funnel@10ac4000 { | |
| coresight-name = "coresight-funnel-dlct2"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10ac4000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x25d>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xdc>; | |
| phandle = <0xf3>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xdb>; | |
| phandle = <0xe7>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xd9>; | |
| phandle = <0xd8>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xda>; | |
| phandle = <0xd0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10cc0000 { | |
| coresight-name = "coresight-tpdm-tmess-0"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10cc0000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x55>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x248>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x77>; | |
| phandle = <0x9f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| stm@10002000 { | |
| coresight-name = "coresight-stm"; | |
| clocks = <0x31>; | |
| reg-names = "stm-base\0stm-stimulus-base"; | |
| reg = <0x10002000 0x1000 0x16280000 0x180000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x10>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x23c>; | |
| arm,primecell-periphid = <0xbb962>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x65>; | |
| phandle = <0xee>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| spi@990000 { | |
| dmas = <0x1a1 0x00 0x04 0x01 0x40 0x00 0x1a1 0x01 0x04 0x01 0x40 0x00>; | |
| qcom,wrapper-core = <0x19a>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x46 0x24 0x54 0x24 0x55>; | |
| #size-cells = <0x00>; | |
| reg-names = "se_phys"; | |
| #address-cells = <0x01>; | |
| spi-max-frequency = <0x2faf080>; | |
| reg = <0x990000 0x4000>; | |
| interrupts = <0x00 0x25d 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1bc>; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x33b>; | |
| pinctrl-0 = <0x1b8 0x1b9 0x1ba 0x1bb>; | |
| }; | |
| qcom,msm-dai-tdm-quin-rx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9140>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9040>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3da>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-quin-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9040>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3db>; | |
| }; | |
| }; | |
| ssphy@88e8000 { | |
| qcom,qmp-phy-reg-offset = <0x1c14 0x1f08 0x1f14 0x1c40 0x1c00 0x1c44 0xffff 0x08 0x04 0x1c 0x00 0x10 0x1c8c>; | |
| vdd-supply = <0x46>; | |
| qcom,vdd-max-load-uA = <0xb798>; | |
| resets = <0x24 0x13 0x24 0x15>; | |
| core-supply = <0x47>; | |
| clocks = <0x24 0x78 0x24 0x7b 0x24 0x7c 0x48 0x45 0x00 0x24 0x7a 0x24 0x77>; | |
| reg-names = "qmp_phy_base"; | |
| reg = <0x88e8000 0x3000>; | |
| reset-names = "global_phy_reset\0phy_reset"; | |
| qcom,vdd-voltage-level = <0x00 0xdea80 0xdea80>; | |
| compatible = "qcom,usb-ssphy-qmp-dp-combo"; | |
| pinctrl-names = "default"; | |
| clock-names = "aux_clk\0pipe_clk\0pipe_clk_mux\0pipe_clk_ext_src\0ref_clk_src\0com_aux_clk\0ref_clk"; | |
| phandle = <0x40>; | |
| pinctrl-0 = <0x49>; | |
| qcom,qmp-phy-init-seq = <0x1010 0x01 0x101c 0x31 0x1020 0x01 0x1024 0xde 0x1028 0x07 0x1030 0xde 0x1034 0x07 0x1050 0x0a 0x1060 0x20 0x1074 0x06 0x1078 0x06 0x107c 0x16 0x1080 0x16 0x1084 0x36 0x1088 0x36 0x1094 0x1a 0x10a4 0x04 0x10ac 0x14 0x10b0 0x34 0x10b4 0x34 0x10b8 0x82 0x10bc 0x82 0x10c4 0x82 0x10cc 0xab 0x10d0 0xea 0x10d4 0x02 0x10d8 0xab 0x10dc 0xea 0x10e0 0x02 0x110c 0x02 0x1110 0x24 0x1118 0x24 0x111c 0x02 0x1158 0x01 0x116c 0x08 0x11ac 0xca 0x11b0 0x1e 0x11b4 0xca 0x11b8 0x1e 0x11bc 0x11 0x1234 0x00 0x1238 0x00 0x123c 0x16 0x1240 0x0e 0x1284 0x35 0x128c 0x3f 0x1290 0x7f 0x1294 0x3f 0x12a4 0x12 0x12e4 0x21 0x1408 0x09 0x1414 0x04 0x1430 0x2f 0x1434 0x7f 0x143c 0xff 0x1440 0x0f 0x1444 0x99 0x144c 0x08 0x1450 0x08 0x1454 0x00 0x1458 0x04 0x14d4 0x54 0x14d8 0x0f 0x14ec 0x0f 0x14f0 0x4a 0x14f4 0x0a 0x14f8 0xc0 0x14fc 0x00 0x1510 0x47 0x151c 0x04 0x1524 0x0e 0x155c 0xbb 0x1560 0x7b 0x1564 0xbb 0x1568 0x3d 0x156c 0xdb 0x1570 0x64 0x1574 0x24 0x1578 0xd2 0x157c 0x13 0x1580 0xa9 0x15a0 0x04 0x15a4 0x38 0x1460 0xa0 0x15a8 0x0c 0x14dc 0x00 0x15b0 0x10 0x1634 0x00 0x1638 0x00 0x163c 0x16 0x1640 0x0e 0x1684 0x35 0x168c 0x3f 0x1690 0x7f 0x1694 0x3f 0x16a4 0x12 0x16e4 0x21 0x1808 0x09 0x1814 0x04 0x1830 0x2f 0x1834 0x7f 0x183c 0xff 0x1840 0x0f 0x1844 0x99 0x184c 0x08 0x1850 0x08 0x1854 0x00 0x1858 0x04 0x18d4 0x54 0x18d8 0x0f 0x18ec 0x0f 0x18f0 0x4a 0x18f4 0x0a 0x18f8 0xc0 0x18fc 0x00 0x1910 0x47 0x191c 0x04 0x1924 0x0e 0x195c 0xbb 0x1960 0x7b 0x1964 0xbb 0x1968 0x3c 0x196c 0xdb 0x1970 0x64 0x1974 0x24 0x1978 0xd2 0x197c 0x13 0x1980 0xa9 0x19a0 0x04 0x19a4 0x38 0x1860 0xa0 0x19a8 0x0c 0x18dc 0x00 0x1f40 0x40 0x1f44 0x00 0x1d90 0xe7 0x1d94 0x03 0x19b0 0x10 0x1cc4 0xc4 0x1cc8 0x89 0x1ccc 0x20 0x1cd8 0x13 0x1cdc 0x21 0x1d88 0xaa 0x1db0 0x0a 0x1dc0 0x88 0x1dc4 0x13 0x1dd0 0x0c 0x1ddc 0x4b 0x1dec 0x10 0x1f18 0xf8 0x1f3c 0x07>; | |
| }; | |
| qcom,msm-adsprpc-mem { | |
| restrict-access; | |
| compatible = "qcom,msm-adsprpc-mem-region"; | |
| memory-region = <0x14d>; | |
| }; | |
| qcedev@1de0000 { | |
| qcom,bam-pipe-pair = <0x02>; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| qcom,smmu-s1-enable; | |
| qcom,ce-hw-shared; | |
| reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
| interrupts = <0x00 0x110 0x04>; | |
| qcom,ce-device = <0x00>; | |
| interconnect-names = "data_path"; | |
| interconnects = <0x3c 0x26 0x29 0x200>; | |
| dma-coherent; | |
| compatible = "qcom,qcedev"; | |
| qcom,no-clock-support; | |
| phandle = <0x2c5>; | |
| qcom,iommu-dma = "atomic"; | |
| iommus = <0x2f 0x480 0x00 0x2f 0x481 0x00>; | |
| qcom,bam-ee = <0x00>; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom_cedev_s_cb { | |
| qcom,secure-context-bank; | |
| dma-coherent; | |
| compatible = "qcom,qcedev,context-bank"; | |
| qcom,iommu-vmid = <0x09>; | |
| label = "secure_context"; | |
| iommus = <0x2f 0x483 0x00>; | |
| }; | |
| qcom_cedev_ns_cb { | |
| dma-coherent; | |
| compatible = "qcom,qcedev,context-bank"; | |
| label = "ns_context"; | |
| iommus = <0x2f 0x481 0x00>; | |
| }; | |
| }; | |
| qcom,cpufreq-hw { | |
| #freq-domain-cells = <0x02>; | |
| clocks = <0x45 0x00 0x24 0x00>; | |
| reg-names = "freq-domain0\0freq-domain1"; | |
| reg = <0x17d91000 0x1000 0x17d92000 0x1000>; | |
| interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04>; | |
| interrupt-names = "dcvsh0_int\0dcvsh1_int"; | |
| compatible = "qcom,cpufreq-hw-epss"; | |
| clock-names = "xo\0alternate"; | |
| phandle = <0x07>; | |
| qcom,lut-row-size = <0x04>; | |
| qcom,skip-enable-check; | |
| }; | |
| qcom,gdsc@af0b000 { | |
| clocks = <0x24 0x16>; | |
| regulator-name = "disp_cc_mdss_core_int2_gdsc"; | |
| reg = <0xaf0b000 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "ahb_clk"; | |
| phandle = <0x316>; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| }; | |
| gpios_control { | |
| mcu-3v3-enable-gpio = <0x126 0x2e 0x00>; | |
| mcu-rst-gpio = <0x126 0x01 0x00>; | |
| status = "ok"; | |
| compatible = "gpios-control"; | |
| }; | |
| qcom,gdsc@ad14078 { | |
| regulator-name = "cam_cc_ife_2_gdsc"; | |
| reg = <0xad14078 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x312>; | |
| qcom,retain-regs; | |
| }; | |
| qfprom@221c8000 { | |
| #size-cells = <0x01>; | |
| ranges; | |
| #address-cells = <0x01>; | |
| reg = <0x221c8000 0x1000>; | |
| compatible = "qcom,ravelin-qfprom\0qcom,qfprom"; | |
| phandle = <0x2d2>; | |
| read-only; | |
| boot_config@600 { | |
| reg = <0x600 0x01>; | |
| phandle = <0x152>; | |
| }; | |
| gpu_speed_bin@119 { | |
| bits = <0x05 0x08>; | |
| reg = <0x119 0x02>; | |
| phandle = <0x33>; | |
| }; | |
| feat_conf12@0130 { | |
| reg = <0x130 0x04>; | |
| phandle = <0x150>; | |
| }; | |
| feat_conf13@0134 { | |
| reg = <0x134 0x04>; | |
| phandle = <0x151>; | |
| }; | |
| }; | |
| cti@1282b000 { | |
| coresight-name = "coresight-cti-riscv_cti"; | |
| clocks = <0x31>; | |
| reg = <0x1282b000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x283>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| dma_dev@0x0 { | |
| compatible = "qcom,iommu-dma"; | |
| memory-region = <0x2e>; | |
| }; | |
| qcom,qup_uart@98c000 { | |
| qcom,wrapper-core = <0x19a>; | |
| interrupts-extended = <0x01 0x00 0x25c 0x04 0x126 0x15 0x04>; | |
| clocks = <0x24 0x44 0x24 0x54 0x24 0x55>; | |
| reg-names = "se_phys"; | |
| reg = <0x98c000 0x4000>; | |
| status = "ok"; | |
| pinctrl-1 = <0x1b4>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x339>; | |
| pinctrl-0 = <0x1b2 0x1b3>; | |
| qcom,auto-suspend-disable; | |
| }; | |
| funnel@10c3b000 { | |
| coresight-name = "coresight-funnel-dl-lpass"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10c3b000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x261>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xe7>; | |
| phandle = <0xdb>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xe6>; | |
| phandle = <0xe5>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10841000 { | |
| coresight-name = "coresight-tpdm-prng"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10841000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x22f>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x58>; | |
| phandle = <0xbc>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interconnect@1700000 { | |
| qcom,bcm-voter-names = "hlos"; | |
| clocks = <0x45 0x16 0x24 0x0b>; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x1700000 0x1b080>; | |
| compatible = "qcom,ravelin-aggre2_noc"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x3c>; | |
| }; | |
| qcom,smmu_sde_unsec_cb { | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-earlymap; | |
| dma-coherent; | |
| compatible = "qcom,smmu_sde_unsec"; | |
| phandle = <0x376>; | |
| iommus = <0x2f 0x800 0x402>; | |
| }; | |
| spi@a8c000 { | |
| dmas = <0x1c4 0x00 0x03 0x01 0x40 0x00 0x1c4 0x01 0x03 0x01 0x40 0x00>; | |
| qcom,wrapper-core = <0x1c0>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x50 0x24 0x56 0x24 0x57>; | |
| #size-cells = <0x00>; | |
| reg-names = "se_phys"; | |
| #address-cells = <0x01>; | |
| spi-max-frequency = <0x2faf080>; | |
| reg = <0xa8c000 0x4000>; | |
| interrupts = <0x00 0x164 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1d9>; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x343>; | |
| pinctrl-0 = <0x1d5 0x1d6 0x1d7 0x1d8>; | |
| }; | |
| qcom,secure-buffer { | |
| qcom,vmid-cp-camera-preview-ro; | |
| compatible = "qcom,secure-buffer"; | |
| }; | |
| tpda@10c3a000 { | |
| coresight-name = "coresight-tpda-dl-lpass"; | |
| qcom,dsb-elem-size = <0x02 0x20 0x0a 0x20>; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x10c3a000 0x1000>; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| qcom,tpda-atid = <0x4a>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x260>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xe5>; | |
| phandle = <0xe6>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xe3>; | |
| phandle = <0x8c>; | |
| }; | |
| }; | |
| port@10 { | |
| reg = <0x0a>; | |
| endpoint { | |
| remote-endpoint = <0xe4>; | |
| phandle = <0x4d>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xe2>; | |
| phandle = <0x5c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tgu@10b10000 { | |
| tgu-conditions = <0x04>; | |
| tgu-steps = <0x03>; | |
| coresight-name = "coresight-tgu-spmi1"; | |
| clocks = <0x31>; | |
| reg-names = "tgu-base"; | |
| reg = <0x10b10000 0x1000>; | |
| compatible = "arm,primecell"; | |
| tgu-regs = <0x09>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x291>; | |
| arm,primecell-periphid = <0xbb999>; | |
| tgu-timer-counters = <0x08>; | |
| }; | |
| qcom,gdsc@18d088 { | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc"; | |
| reg = <0x18d088 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x323>; | |
| }; | |
| qcom,qupv3_0_geni_se@9c0000 { | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| reg = <0x9c0000 0x2000>; | |
| interconnect-names = "qup-core\0snoc-llcc\0qup-ddr"; | |
| status = "ok"; | |
| interconnects = <0x190 0x24 0x190 0x240 0x191 0x0c 0x25 0x234 0x14a 0x07 0x29 0x200>; | |
| dma-coherent; | |
| compatible = "qcom,qupv3-geni-se"; | |
| phandle = <0x19a>; | |
| qcom,iommu-dma = "fastmap"; | |
| iommus = <0x2f 0x163 0x00>; | |
| qcom,msm-bus,num-paths = <0x03>; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| }; | |
| qcom,sde_rscc@af20000 { | |
| vdd-supply = <0x188>; | |
| qcom,sde-dram-channels = <0x02>; | |
| cell-index = <0x00>; | |
| clocks = <0x12a 0x17 0x12a 0x10 0x12a 0x16>; | |
| reg-names = "drv\0wrapper"; | |
| qcom,msm-bus,active-only; | |
| reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; | |
| interconnect-names = "qcom,sde-data-bus0"; | |
| interconnects = <0x28 0x3e9 0x29 0x5e8>; | |
| compatible = "qcom,sde-rsc"; | |
| clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; | |
| phandle = <0x372>; | |
| qcom,sde-rsc-version = <0x04>; | |
| }; | |
| syscon@190ba000 { | |
| reg = <0x190ba000 0x54>; | |
| compatible = "syscon"; | |
| phandle = <0x137>; | |
| }; | |
| i2c@a80000 { | |
| dmas = <0x1c4 0x00 0x00 0x03 0x40 0x00 0x1c4 0x01 0x00 0x03 0x40 0x00>; | |
| qcom,wrapper-core = <0x1c0>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x4a 0x24 0x56 0x24 0x57>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0xa80000 0x4000>; | |
| interrupts = <0x00 0x161 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1c3>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x33d>; | |
| pinctrl-0 = <0x1c1 0x1c2>; | |
| }; | |
| wpss_etm0 { | |
| qcom,inst-id = <0x03>; | |
| coresight-name = "coresight-wpss-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| atid = <0x2c>; | |
| phandle = <0x84>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x7b>; | |
| phandle = <0x7e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-ultra-low-latency { | |
| qcom,latency-level = "ultra"; | |
| qcom,msm-pcm-dsp-id = <0x02>; | |
| qcom,msm-pcm-low-latency; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| phandle = <0x37e>; | |
| }; | |
| qcom,pmic_glink { | |
| qcom,protection-domain = "tms/servreg\0msm/adsp/charger_pd"; | |
| qcom,subsys-name = "lpass"; | |
| qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; | |
| status = "okay"; | |
| depends-on-supply = <0x13b>; | |
| compatible = "qcom,pmic-glink"; | |
| qcom,battery_charger { | |
| qcom,wireless-charging-not-supported; | |
| status = "okay"; | |
| compatible = "qcom,battery-charger"; | |
| qcom,thermal-mitigation-step = <0x7a120>; | |
| phandle = <0x2dd>; | |
| }; | |
| qcom,altmode { | |
| #altmode-cells = <0x01>; | |
| status = "okay"; | |
| compatible = "qcom,altmode-glink"; | |
| phandle = <0x2df>; | |
| }; | |
| qcom,ucsi { | |
| status = "okay"; | |
| compatible = "qcom,ucsi-glink"; | |
| phandle = <0x2de>; | |
| connector { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x163>; | |
| phandle = <0x41>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_pll_codes { | |
| reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x36f>; | |
| label = "dsi_pll_codes"; | |
| }; | |
| etm2 { | |
| coresight-name = "coresight-etm2"; | |
| clocks = <0x31>; | |
| cpu = <0x1c>; | |
| qcom,skip-power-up; | |
| reg = <0x12240000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x03>; | |
| clock-names = "apb_pclk"; | |
| arm,primecell-periphid = <0xbb95d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x113>; | |
| phandle = <0x11c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interconnect@1500000 { | |
| qcom,bcm-voter-names = "hlos"; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x1500000 0x6200>; | |
| compatible = "qcom,ravelin-cnoc2"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x3d>; | |
| }; | |
| qcom,msm-dai-mi2s { | |
| compatible = "qcom,msm-dai-mi2s"; | |
| phandle = <0x38c>; | |
| qcom,msm-dai-q6-mi2s-senary { | |
| qcom,msm-mi2s-rx-lines = <0x00>; | |
| qcom,msm-mi2s-tx-lines = <0x03>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x05>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x392>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-sec { | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| qcom,msm-mi2s-tx-lines = <0x00>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x01>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x38e>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quat { | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x03>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x390>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quin { | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x04>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x391>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-tert { | |
| qcom,msm-mi2s-rx-lines = <0x00>; | |
| qcom,msm-mi2s-tx-lines = <0x03>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x02>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x38f>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-prim { | |
| qcom,msm-mi2s-rx-lines = <0x03>; | |
| qcom,msm-mi2s-tx-lines = <0x00>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x00>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x38d>; | |
| }; | |
| }; | |
| funnel@10c02000 { | |
| coresight-name = "coresight-funnel-dlct1"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10c02000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x250>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x9a>; | |
| source = <0x9b>; | |
| phandle = <0xd3>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x9c>; | |
| source = <0x9d>; | |
| phandle = <0xd4>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x99>; | |
| phandle = <0x6c>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x98>; | |
| phandle = <0x6b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10c38000 { | |
| coresight-name = "coresight-tpdm-dl-lpass"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10c38000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4a>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x227>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4d>; | |
| phandle = <0xe4>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ctrl0@ae94000 { | |
| cell-index = <0x00>; | |
| clocks = <0x12a 0x05 0x12a 0x06 0x12a 0x08 0x12a 0x11 0x12a 0x12 0x12a 0x09 0x45 0x00>; | |
| reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; | |
| reg = <0xae94000 0x400 0xaf0f000 0x04 0xae36000 0x300>; | |
| interrupts = <0x04 0x00>; | |
| interrupt-parent = <0x36e>; | |
| vdda-1p2-supply = <0x47>; | |
| compatible = "qcom,dsi-ctrl-hw-v2.6"; | |
| clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; | |
| phandle = <0x370>; | |
| frame-threshold-time-us = <0x320>; | |
| label = "dsi-ctrl-0"; | |
| qcom,split-link-supported; | |
| qcom,ctrl-supply-entries { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-max-voltage = <0x1339e0>; | |
| qcom,supply-disable-load = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| qcom,supply-enable-load = <0x40d8>; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@18d058 { | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; | |
| reg = <0x18d058 0x04>; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x2a>; | |
| parent-supply = <0x124>; | |
| }; | |
| qcom,qup_uart@988000 { | |
| qcom,wrapper-core = <0x19a>; | |
| interrupts-extended = <0x01 0x00 0x25b 0x04 0x126 0x11 0x04>; | |
| pinctrl-2 = <0x196 0x197 0x198 0x195>; | |
| clocks = <0x24 0x42 0x24 0x54 0x24 0x55>; | |
| reg-names = "se_phys"; | |
| pinctrl-3 = <0x192 0x193 0x194 0x195>; | |
| reg = <0x988000 0x4000>; | |
| qcom,wakeup-byte = <0xfd>; | |
| status = "ok"; | |
| pinctrl-1 = <0x196 0x197 0x198 0x199>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-names = "default\0active\0sleep\0shutdown"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x332>; | |
| pinctrl-0 = <0x192 0x193 0x194 0x195>; | |
| }; | |
| qcom,memlat { | |
| qcom,be-stall-ev = <0x4005>; | |
| compatible = "qcom,memlat"; | |
| phandle = <0x2c9>; | |
| l3 { | |
| qcom,miss-ev = <0x17>; | |
| qcom,target-dev = <0x145>; | |
| compatible = "qcom,memlat-grp"; | |
| qcom,sampling-path = <0x146>; | |
| gold-compute { | |
| qcom,sampling-enabled; | |
| qcom,compute-mon; | |
| qcom,cpulist = <0x20 0x21>; | |
| qcom,cpufreq-memfreq-tbl = <0x1f5900 0x4b000 0x240900 0x156300>; | |
| compatible = "qcom,memlat-mon"; | |
| }; | |
| gold { | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x20 0x21>; | |
| qcom,cpufreq-memfreq-tbl = <0xa8c00 0x4b000 0xea600 0x87f00 0x122a00 0xc9900 0x148200 0xe5b00 0x193200 0x127500 0x1d0100 0x13ec00 0x1f5900 0x156300 0x21b100 0x15f900>; | |
| compatible = "qcom,memlat-mon"; | |
| }; | |
| silver { | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; | |
| qcom,cpufreq-memfreq-tbl = <0x79e00 0x4b000 0xa4100 0x87f00 0xc4e00 0x9f600 0xe1000 0xc9900 0x10b300 0xe5b00 0x13a100 0x106800 0x168f00 0x127500 0x18e700 0x13ec00 0x1b8a00 0x15f900>; | |
| compatible = "qcom,memlat-mon"; | |
| }; | |
| }; | |
| ddrqos { | |
| qcom,miss-ev = <0x2a>; | |
| qcom,target-dev = <0x147>; | |
| compatible = "qcom,memlat-grp"; | |
| qcom,sampling-path = <0x148>; | |
| gold { | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x20 0x21>; | |
| qcom,cpufreq-memfreq-tbl = <0x231860 0x00 0x2dc6c0 0x01>; | |
| compatible = "qcom,memlat-mon"; | |
| phandle = <0x2ca>; | |
| }; | |
| }; | |
| ddr { | |
| qcom,miss-ev = <0x2a>; | |
| qcom,target-dev = <0x143>; | |
| compatible = "qcom,memlat-grp"; | |
| qcom,sampling-path = <0x144>; | |
| gold-compute { | |
| qcom,sampling-enabled; | |
| qcom,compute-mon; | |
| qcom,cpulist = <0x20 0x21>; | |
| compatible = "qcom,memlat-mon"; | |
| ddr4-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x122a00 0x858b8 0x16da00 0xbb800 0x193200 0xf84a8 0x1d0100 0x17ba38 0x208500 0x1a0fe0 0x249f00 0x1febe0>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr5-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x122a00 0x858b8 0x16da00 0xbb800 0x193200 0xf84a8 0x1f5900 0x17ba38 0x208500 0x1a0fe0 0x249f00 0x1febe0>; | |
| qcom,ddr-type = <0x08>; | |
| }; | |
| }; | |
| gold { | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x20 0x21>; | |
| compatible = "qcom,memlat-mon"; | |
| ddr4-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0xea600 0x858b8 0x122a00 0xf84a8 0x16da00 0x14a780 0x193200 0x17ba38 0x208500 0x1a0fe0 0x249f00 0x1febe0>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr5-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0xea600 0x858b8 0x193200 0x17ba38 0x1d0100 0x1a0fe0 0x208500 0x1febe0 0x249f00 0x30c460>; | |
| qcom,ddr-type = <0x08>; | |
| }; | |
| }; | |
| silver { | |
| qcom,sampling-enabled; | |
| qcom,cpulist = <0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; | |
| compatible = "qcom,memlat-mon"; | |
| ddr4-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x10b300 0x858b8 0x168f00 0xbb800 0x1b8a00 0xf84a8>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr5-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x10b300 0x858b8 0x168f00 0xbb800 0x1b8a00 0x17ba38>; | |
| qcom,ddr-type = <0x08>; | |
| }; | |
| }; | |
| silver-compute { | |
| qcom,sampling-enabled; | |
| qcom,compute-mon; | |
| qcom,cpulist = <0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; | |
| compatible = "qcom,memlat-mon"; | |
| ddr4-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x168f00 0x858b8 0x1b8a00 0xbb800>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr5-tbl { | |
| qcom,cpufreq-memfreq-tbl = <0x168f00 0x858b8 0x1b8a00 0xbb800>; | |
| qcom,ddr-type = <0x08>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| iommu_test_device { | |
| compatible = "qcom,iommu-debug-test"; | |
| usecase3_apps_dma { | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-dma = "atomic"; | |
| iommus = <0x2f 0x7e0 0x00>; | |
| }; | |
| usecase7_apps_secure { | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-vmid = <0x0a>; | |
| qcom,iommu-dma = "atomic"; | |
| iommus = <0x2f 0x7e0 0x00>; | |
| }; | |
| usecase5_kgsl_dma { | |
| compatible = "qcom,iommu-debug-usecase"; | |
| iommus = <0x30 0x07 0x400>; | |
| }; | |
| usecase0_apps { | |
| compatible = "qcom,iommu-debug-usecase"; | |
| iommus = <0x2f 0x7e0 0x00>; | |
| }; | |
| usecase4_apps_coherent { | |
| dma-coherent; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| iommus = <0x2f 0x7e1 0x00>; | |
| }; | |
| usecase6_kgsl_coherent { | |
| dma-coherent; | |
| compatible = "qcom,iommu-debug-usecase"; | |
| iommus = <0x30 0x407 0x400>; | |
| }; | |
| usecase2_apps_atomic { | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-dma = "atomic"; | |
| iommus = <0x2f 0x7e0 0x00>; | |
| }; | |
| usecase1_apps_fastmap { | |
| compatible = "qcom,iommu-debug-usecase"; | |
| qcom,iommu-dma = "fastmap"; | |
| iommus = <0x2f 0x7e0 0x00>; | |
| }; | |
| }; | |
| qcom,msm-pcm-dsp-noirq { | |
| qcom,latency-level = "ultra"; | |
| qcom,msm-pcm-low-latency; | |
| compatible = "qcom,msm-pcm-dsp-noirq"; | |
| phandle = <0x37f>; | |
| }; | |
| qcom,qup_uart@980000 { | |
| qcom,wrapper-core = <0x19a>; | |
| clocks = <0x24 0x3e 0x24 0x54 0x24 0x55>; | |
| reg-names = "se_phys"; | |
| reg = <0x980000 0x4000>; | |
| interrupts = <0x00 0x259 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x19d>; | |
| compatible = "qcom,msm-geni-console"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x333>; | |
| pinctrl-0 = <0x19b 0x19c>; | |
| }; | |
| replicator@1004e000 { | |
| coresight-name = "coresight-replicator_etr"; | |
| clocks = <0x31>; | |
| reg-names = "replicator-base"; | |
| reg = <0x1004e000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x26c>; | |
| arm,primecell-periphid = <0xbb909>; | |
| out-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x10b>; | |
| phandle = <0x10e>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x10c>; | |
| phandle = <0x10f>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x10a>; | |
| phandle = <0x109>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm1 { | |
| coresight-name = "coresight-etm1"; | |
| clocks = <0x31>; | |
| cpu = <0x1b>; | |
| qcom,skip-power-up; | |
| reg = <0x12140000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x02>; | |
| clock-names = "apb_pclk"; | |
| arm,primecell-periphid = <0xbb95d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x112>; | |
| phandle = <0x11b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10010000 { | |
| coresight-name = "coresight-cti-qc_cti"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10010000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| pinctrl-names = "cti-trigout-pctrl"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x270>; | |
| qcom,cti-gpio-trigout = <0x10>; | |
| pinctrl-0 = <0x110>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| wsa_core_tx_clk { | |
| qcom,codec-ext-clk-src = <0x0e>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x314>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x476>; | |
| }; | |
| cti@12900000 { | |
| coresight-name = "coresight-cti-apss_cti2"; | |
| clocks = <0x31>; | |
| reg = <0x12900000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x282>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| sdhc1-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x149>; | |
| opp-384000000 { | |
| opp-hz = <0x00 0x16e36000>; | |
| opp-peak-kBps = <0x557300 0x16e360>; | |
| opp-avg-kBps = <0x61a80 0x00>; | |
| }; | |
| opp-100000000 { | |
| opp-hz = <0x00 0x5f5e100>; | |
| opp-peak-kBps = <0x186a00 0x445c0>; | |
| opp-avg-kBps = <0x19640 0x00>; | |
| }; | |
| }; | |
| qcom,dsi-display-primary { | |
| qcom,panel-te-source = <0x00>; | |
| qcom,dsi-phy = <0x371>; | |
| qcom,mdp = <0x36e>; | |
| extvdd-supply = <0x415>; | |
| clocks = <0x371 0x00 0x371 0x01 0x12a 0x0c>; | |
| qcom,dsi-default-panel = <0x454>; | |
| qcom,platform-te-gpio = <0x126 0x5d 0x00>; | |
| vci-supply = <0x452>; | |
| qcom,dsi-ctrl = <0x370>; | |
| pinctrl-1 = <0x44f 0x450>; | |
| vddio-supply = <0x451>; | |
| compatible = "qcom,dsi-display"; | |
| ibb-supply = <0x453>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| clock-names = "pll_byte_clk0\0pll_dsi_clk0\0mdp_core_clk"; | |
| phandle = <0x456>; | |
| label = "primary"; | |
| pinctrl-0 = <0x44d 0x44e>; | |
| qcom,demura-panel-id = <0x122e700 0xb0>; | |
| }; | |
| cti@10C7B000 { | |
| coresight-name = "coresight-cti-wlan_q6_cti"; | |
| clocks = <0x31>; | |
| reg = <0x10c7b000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x27b>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| interconnect@1760000 { | |
| qcom,bcm-voter-names = "hlos"; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x1760000 0x1100>; | |
| compatible = "qcom,ravelin-video_aggre_noc"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x2d1>; | |
| }; | |
| msm_cdc_pinctrl@54 { | |
| pinctrl-1 = <0x2fd>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x481>; | |
| pinctrl-0 = <0x2fc>; | |
| }; | |
| rx_mclk2_2x_clk { | |
| qcom,codec-ext-clk-src = <0x10>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x318>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x47a>; | |
| }; | |
| tpda@10ac3000 { | |
| coresight-name = "coresight-tpda-dlct2"; | |
| qcom,dsb-elem-size = <0x07 0x20 0x11 0x20 0x1a 0x20>; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x10ac3000 0x1000>; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x08 0x40 0x0d 0x40 0x0e 0x40 0x1b 0x40>; | |
| qcom,tpda-atid = <0x4f>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x25c>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xd8>; | |
| phandle = <0xd9>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@1a { | |
| reg = <0x1a>; | |
| endpoint { | |
| remote-endpoint = <0xd6>; | |
| phandle = <0x67>; | |
| }; | |
| }; | |
| port@11 { | |
| reg = <0x11>; | |
| endpoint { | |
| remote-endpoint = <0xd5>; | |
| phandle = <0x8a>; | |
| }; | |
| }; | |
| port@e { | |
| reg = <0x0e>; | |
| endpoint { | |
| remote-endpoint = <0xd4>; | |
| phandle = <0x9c>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0xd1>; | |
| phandle = <0xcc>; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0x08>; | |
| endpoint { | |
| remote-endpoint = <0xd2>; | |
| phandle = <0xce>; | |
| }; | |
| }; | |
| port@1b { | |
| reg = <0x1b>; | |
| endpoint { | |
| remote-endpoint = <0xd7>; | |
| phandle = <0x68>; | |
| }; | |
| }; | |
| port@d { | |
| reg = <0x0d>; | |
| endpoint { | |
| remote-endpoint = <0xd3>; | |
| phandle = <0x9a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,bwmon-ddr@19091000 { | |
| qcom,count-unit = <0x10000>; | |
| reg-names = "base"; | |
| reg = <0x19091000 0x1000>; | |
| interrupts = <0x00 0x51 0x04>; | |
| qcom,target-dev = <0x143>; | |
| compatible = "qcom,bwmon5"; | |
| phandle = <0x2cb>; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| }; | |
| interconnect@3C40000 { | |
| qcom,bcm-voter-names = "hlos"; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x3c40000 0x17200>; | |
| compatible = "qcom,ravelin-lpass_ag_noc"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x2b>; | |
| }; | |
| qcom,gdsc@18d08c { | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc"; | |
| reg = <0x18d08c 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x324>; | |
| }; | |
| tpdm@10c22000 { | |
| coresight-name = "coresight-tpdm-ipa"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x10c22000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x235>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5e>; | |
| phandle = <0xc0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,tmecom-qmp-client { | |
| mbox-names = "tmecom"; | |
| depends-on-supply = <0x13e>; | |
| compatible = "qcom,tmecom-qmp-client"; | |
| label = "tmecom"; | |
| mboxes = <0x13e 0x00>; | |
| }; | |
| tpdm_lpass_lpi { | |
| coresight-name = "coresight-tpdm-lpass-lpi"; | |
| compatible = "qcom,coresight-dummy"; | |
| qcom,dummy-source; | |
| atid = <0x1a>; | |
| phandle = <0x225>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4b>; | |
| phandle = <0x87>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm7 { | |
| coresight-name = "coresight-etm7"; | |
| clocks = <0x31>; | |
| cpu = <0x21>; | |
| qcom,skip-power-up; | |
| reg = <0x12740000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x08>; | |
| clock-names = "apb_pclk"; | |
| arm,primecell-periphid = <0xbb95d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x118>; | |
| phandle = <0x121>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| vote_lpass_audio_hw { | |
| qcom,codec-ext-clk-src = <0x0b>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x379>; | |
| }; | |
| display_panel_ibb_stub { | |
| regulator-max-microvolt = <0x5b8d80>; | |
| regulator-name = "display_panel_ibb"; | |
| compatible = "qcom,stub-regulator"; | |
| regulator-min-microvolt = <0x4630c0>; | |
| phandle = <0x453>; | |
| }; | |
| dummy_sink { | |
| coresight-name = "coresight-eud"; | |
| qcom,dummy-sink; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x268>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x102>; | |
| phandle = <0x107>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@109Ae000 { | |
| coresight-name = "coresight-cti-wcss2"; | |
| clocks = <0x31>; | |
| reg = <0x109ae000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x28e>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| etm6 { | |
| coresight-name = "coresight-etm6"; | |
| clocks = <0x31>; | |
| cpu = <0x20>; | |
| qcom,skip-power-up; | |
| reg = <0x12640000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x07>; | |
| clock-names = "apb_pclk"; | |
| arm,primecell-periphid = <0xbb95d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x117>; | |
| phandle = <0x120>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@17b004 { | |
| regulator-name = "gcc_pcie_0_gdsc"; | |
| reg = <0x17b004 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x1e8>; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| qcom,collapse-vote = <0x18b 0x00>; | |
| }; | |
| funnel@10cc5000 { | |
| coresight-name = "coresight-funnel-tmess"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10cc5000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x252>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa3>; | |
| phandle = <0xec>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa2>; | |
| phandle = <0xa1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| apps-smmu@15000000 { | |
| #iommu-cells = <0x02>; | |
| qcom,handoff-smrs = <0x800 0x402>; | |
| clocks = <0x24 0x90>; | |
| qcom,active-only; | |
| #size-cells = <0x01>; | |
| ranges; | |
| reg-names = "base\0tcu-base"; | |
| #address-cells = <0x01>; | |
| qcom,num-smr-override = <0x85>; | |
| reg = <0x15000000 0x100000 0x151e2000 0x20>; | |
| interrupts = <0x00 0x41 0x04 0x00 0x5e 0x04 0x00 0x5f 0x04 0x00 0x60 0x04 0x00 0x29e 0x04 0x00 0x29f 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x158 0x04 0x00 0x159 0x04 0x00 0x18b 0x04 0x00 0x18c 0x04 0x00 0x18d 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04 0x00 0x194 0x04 0x00 0x195 0x04 0x00 0x196 0x04 0x00 0x197 0x04 0x00 0x198 0x04 0x00 0x199 0x04 0x00 0x1a2 0x04 0x00 0x1a3 0x04 0x00 0x19c 0x04 0x00 0x1a5 0x04 0x00 0x2c3 0x04 0x00 0x1a7 0x04 0x00 0x1a8 0x04 0x00 0x1a9 0x04 0x00 0x2b2 0x04 0x00 0x2b3 0x04 0x00 0x2b4 0x04>; | |
| #global-interrupts = <0x01>; | |
| qcom,actlr = <0x1980 0x3f 0x103 0x1900 0x3f 0x01 0x1800 0xff 0x01 0x800 0x7ff 0x01>; | |
| interconnects = <0x25 0x02 0x26 0x24f>; | |
| dma-coherent; | |
| compatible = "qcom,qsmmu-v500"; | |
| clock-names = "gcc_hlos1_vote_mmu_tcu_clk"; | |
| phandle = <0x2f>; | |
| qcom,use-3-lvl-tables; | |
| qcom,num-context-banks-override = <0x52>; | |
| anoc_1_tbu@151e5000 { | |
| qcom,micro-idle; | |
| qcom,stream-id-range = <0x00 0x400>; | |
| clocks = <0x24 0x8b>; | |
| qcom,active-only; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x151e5000 0x1000 0x151e2200 0x08>; | |
| interconnects = <0x25 0x02 0x26 0x243>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| clock-names = "gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk"; | |
| phandle = <0x218>; | |
| }; | |
| sf_0_tbu@151fd000 { | |
| vdd-supply = <0x2d>; | |
| qcom,micro-idle; | |
| qcom,stream-id-range = <0x1800 0x400>; | |
| clocks = <0x24 0x8f>; | |
| qcom,active-only; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x151fd000 0x1000 0x151e2230 0x08>; | |
| qcom,regulator-names = "vdd"; | |
| interconnects = <0x28 0x0f 0x29 0x200>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| clock-names = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk"; | |
| phandle = <0x21e>; | |
| }; | |
| mnoc_hf_0_tbu@151ed000 { | |
| vdd-supply = <0x27>; | |
| qcom,micro-idle; | |
| qcom,stream-id-range = <0x800 0x400>; | |
| clocks = <0x24 0x8d>; | |
| qcom,active-only; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x151ed000 0x1000 0x151e2210 0x08>; | |
| qcom,regulator-names = "vdd"; | |
| interconnects = <0x28 0x0d 0x29 0x200>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| clock-names = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk"; | |
| phandle = <0x21a>; | |
| }; | |
| mnoc_hf_1_tbu@151f1000 { | |
| vdd-supply = <0x2a>; | |
| qcom,micro-idle; | |
| qcom,stream-id-range = <0xc00 0x400>; | |
| clocks = <0x24 0x8e>; | |
| qcom,active-only; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x151f1000 0x1000 0x151e2218 0x08>; | |
| qcom,regulator-names = "vdd"; | |
| interconnects = <0x28 0x0d 0x29 0x200>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| clock-names = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk"; | |
| phandle = <0x21b>; | |
| }; | |
| pcie_tbu@151f9000 { | |
| qcom,micro-idle; | |
| qcom,stream-id-range = <0x1400 0x400>; | |
| clocks = <0x24 0x8a>; | |
| qcom,active-only; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x151f9000 0x1000 0x151e2228 0x08>; | |
| interconnects = <0x2c 0x2f 0x29 0x200>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| clock-names = "gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk"; | |
| phandle = <0x21d>; | |
| }; | |
| lpass_tbu@151f5000 { | |
| qcom,micro-idle; | |
| qcom,stream-id-range = <0x1000 0x400>; | |
| clocks = <0x24 0x89>; | |
| qcom,active-only; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x151f5000 0x1000 0x151e2220 0x08>; | |
| interconnects = <0x2b 0x28 0x29 0x200>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| clock-names = "gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk"; | |
| phandle = <0x21c>; | |
| }; | |
| anoc_2_tbu@151e9000 { | |
| qcom,micro-idle; | |
| qcom,stream-id-range = <0x400 0x400>; | |
| clocks = <0x24 0x8c>; | |
| qcom,active-only; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x151e9000 0x1000 0x151e2208 0x08>; | |
| interconnects = <0x25 0x02 0x26 0x243>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| clock-names = "gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk"; | |
| phandle = <0x219>; | |
| }; | |
| }; | |
| syscon@3d9953c { | |
| reg = <0x3d9953c 0x04>; | |
| compatible = "syscon"; | |
| phandle = <0x18d>; | |
| }; | |
| ipcc-self-ping-adsp { | |
| interrupts-extended = <0x13b 0x03 0x03 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x331>; | |
| mboxes = <0x13b 0x03 0x03>; | |
| }; | |
| cx_sdpm@634000 { | |
| clocks = <0x23 0x14 0x135 0x11 0x135 0x0e 0x24 0x82 0x12a 0x0d>; | |
| csr-id = <0x00 0x01 0x02 0x06 0x07>; | |
| reg = <0x634000 0x1000>; | |
| compatible = "qcom,sdpm"; | |
| clock-names = "gpu_cc_gx_gfx3d\0cam_cc_camnoc_axi\0cam_cc_bps\0gcc_video_venus\0disp_cc_mdss_mdp"; | |
| }; | |
| qcom,gdsc@af09000 { | |
| clocks = <0x24 0x16>; | |
| regulator-name = "disp_cc_mdss_core_gdsc"; | |
| reg = <0xaf09000 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "ahb_clk"; | |
| phandle = <0x188>; | |
| qcom,proxy-consumer-enable; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| proxy-supply = <0x188>; | |
| }; | |
| qcom,memshare { | |
| compatible = "qcom,memshare"; | |
| qcom,client_2 { | |
| qcom,client-id = <0x02>; | |
| compatible = "qcom,memshare-peripheral"; | |
| label = "modem"; | |
| qcom,peripheral-size = <0x00>; | |
| }; | |
| qcom,client_1 { | |
| qcom,client-id = <0x00>; | |
| qcom,allocate-boot-time; | |
| compatible = "qcom,memshare-peripheral"; | |
| label = "modem"; | |
| qcom,peripheral-size = <0x00>; | |
| }; | |
| qcom,client_3 { | |
| qcom,client-id = <0x01>; | |
| qcom,allocate-on-request; | |
| compatible = "qcom,memshare-peripheral"; | |
| phandle = <0x2c1>; | |
| label = "modem"; | |
| qcom,peripheral-size = <0x500000>; | |
| }; | |
| }; | |
| qcom,gdsc@17c000 { | |
| regulator-name = "gcc_pcie_0_phy_gdsc"; | |
| reg = <0x17c000 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x31a>; | |
| qcom,retain-regs; | |
| qcom,collapse-vote = <0x18b 0x03>; | |
| }; | |
| interconnect@19100000 { | |
| qcom,bcm-voter-names = "hlos\0disp"; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x19100000 0xbc080>; | |
| compatible = "qcom,ravelin-gem_noc"; | |
| qcom,bcm-voters = <0x14e 0x14f>; | |
| phandle = <0x25>; | |
| }; | |
| qcom,msm-hdmi-dba-codec-rx { | |
| compatible = "qcom,msm-hdmi-dba-codec-rx"; | |
| qcom,dba-bridge-chip = "adv7533"; | |
| phandle = <0x3c7>; | |
| }; | |
| dload_mode { | |
| compatible = "qcom,dload-mode"; | |
| }; | |
| qcom,msm-dai-q6-spdif-sec-rx { | |
| compatible = "qcom,msm-dai-q6-spdif"; | |
| phandle = <0x3e4>; | |
| qcom,msm-dai-q6-dev-id = <0x5002>; | |
| }; | |
| cti@109AC000 { | |
| coresight-name = "coresight-cti-sierra_a6"; | |
| clocks = <0x31>; | |
| reg = <0x109ac000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x28c>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,smp2p-modem { | |
| qcom,smem = <0x1b3 0x1ac>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x01>; | |
| interrupts = <0x02 0x02 0x01>; | |
| interrupt-parent = <0x13b>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x13b 0x02 0x02>; | |
| qcom,smp2p-ipa-1-in { | |
| qcom,entry-name = "ipa"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x161>; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x15b>; | |
| }; | |
| qcom,smp2p-ipa-1-out { | |
| qcom,entry-name = "ipa"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x160>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x15a>; | |
| }; | |
| }; | |
| qcom,mdss_rotator { | |
| qcom,mdss-default-ot-rd-limit = <0x20>; | |
| qcom,mdss-rot-mode = <0x01>; | |
| power-domains = <0x36e>; | |
| qcom,mdss-highest-bank-bit = <0x08 0x02 0x07 0x01>; | |
| qcom,mdss-sbuf-headroom = <0x14>; | |
| clocks = <0x12a 0x03 0x12a 0x14>; | |
| qcom,mdss-rot-qos-lut = <0x00 0x00 0x00 0x00>; | |
| qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x12c00>; | |
| reg-names = "mdp_phys\0rot_vbif_phys"; | |
| qcom,mdss-default-ot-wr-limit = <0x20>; | |
| qcom,mdss-rot-vbif-qos-setting = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,mdss-rot-danger-lut = <0x00 0x00>; | |
| reg = <0xae00000 0xac000 0xaeb0000 0x2008>; | |
| qcom,mdss-rot-xin-id = <0x0a 0x0b>; | |
| interrupts = <0x02 0x00>; | |
| interrupt-parent = <0x36e>; | |
| qcom,mdss-rot-parent = <0x36e 0x00>; | |
| interconnect-names = "qcom,rot-data-bus0\0qcom,sde-reg-bus"; | |
| interconnects = <0x28 0x17 0x29 0x200 0x25 0x02 0x3d 0x20c>; | |
| compatible = "qcom,sde_rotator"; | |
| qcom,mdss-rot-cdp-setting = <0x01 0x01>; | |
| clock-names = "iface_clk\0rot_clk"; | |
| #list-cells = <0x01>; | |
| phandle = <0x373>; | |
| qcom,mdss-rot-vbif-memtype = <0x03 0x03>; | |
| qcom,mdss-rot-safe-lut = <0xffff 0xffff>; | |
| qcom,smmu_rot_sec_cb { | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| dma-coherent; | |
| compatible = "qcom,smmu_sde_rot_sec"; | |
| qcom,iommu-vmid = <0x0a>; | |
| phandle = <0x375>; | |
| iommus = <0x2f 0x81d 0x00 0x2f 0xc1d 0x00>; | |
| }; | |
| qcom,smmu_rot_unsec_cb { | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| dma-coherent; | |
| compatible = "qcom,smmu_sde_rot_unsec"; | |
| phandle = <0x374>; | |
| iommus = <0x2f 0x81c 0x400>; | |
| }; | |
| }; | |
| qcom,msm-sen-auxpcm { | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| qcom,msm-auxpcm-interface = "senary"; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| phandle = <0x3c6>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| }; | |
| etm0 { | |
| coresight-name = "coresight-etm0"; | |
| clocks = <0x31>; | |
| cpu = <0x1a>; | |
| qcom,skip-power-up; | |
| reg = <0x12040000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x01>; | |
| clock-names = "apb_pclk"; | |
| arm,primecell-periphid = <0xbb95d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x111>; | |
| phandle = <0x11a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| syscon@3d99058 { | |
| reg = <0x3d99058 0x04>; | |
| compatible = "syscon"; | |
| phandle = <0x18f>; | |
| }; | |
| spi@a84000 { | |
| dmas = <0x1c4 0x00 0x01 0x01 0x40 0x00 0x1c4 0x01 0x01 0x01 0x40 0x00>; | |
| qcom,wrapper-core = <0x1c0>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x4c 0x24 0x56 0x24 0x57>; | |
| #size-cells = <0x00>; | |
| reg-names = "se_phys"; | |
| #address-cells = <0x01>; | |
| spi-max-frequency = <0x2faf080>; | |
| reg = <0xa84000 0x4000>; | |
| interrupts = <0x00 0x162 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1d1>; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x340>; | |
| pinctrl-0 = <0x1cd 0x1ce 0x1cf 0x1d0>; | |
| }; | |
| tpda@10c2b000 { | |
| coresight-name = "coresight-tpda-dlct0"; | |
| qcom,dsb-elem-size = <0x05 0x20 0x09 0x20 0x0b 0x20 0x14 0x20 0x15 0x20 0x19 0x20 0x1a 0x20>; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x10c2b000 0x1000>; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x06 0x20 0x0b 0x20 0x0c 0x40 0x13 0x40 0x16 0x20 0x18 0x40 0x19 0x40 0x1b 0x40>; | |
| qcom,tpda-atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x259>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xc4>; | |
| phandle = <0xc5>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@14 { | |
| reg = <0x14>; | |
| endpoint { | |
| remote-endpoint = <0xbd>; | |
| phandle = <0x59>; | |
| }; | |
| }; | |
| port@1a { | |
| reg = <0x1a>; | |
| endpoint { | |
| remote-endpoint = <0xc2>; | |
| phandle = <0x60>; | |
| }; | |
| }; | |
| port@15 { | |
| reg = <0x15>; | |
| endpoint { | |
| remote-endpoint = <0xbe>; | |
| phandle = <0x5a>; | |
| }; | |
| }; | |
| port@9 { | |
| reg = <0x09>; | |
| endpoint { | |
| remote-endpoint = <0xb9>; | |
| phandle = <0x92>; | |
| }; | |
| }; | |
| port@13 { | |
| reg = <0x13>; | |
| endpoint { | |
| remote-endpoint = <0xbc>; | |
| phandle = <0x58>; | |
| }; | |
| }; | |
| port@19 { | |
| reg = <0x19>; | |
| endpoint { | |
| remote-endpoint = <0xc1>; | |
| phandle = <0x5f>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0xb7>; | |
| phandle = <0x7f>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xb8>; | |
| phandle = <0x81>; | |
| }; | |
| }; | |
| port@c { | |
| reg = <0x0b>; | |
| endpoint { | |
| remote-endpoint = <0xba>; | |
| phandle = <0x94>; | |
| }; | |
| }; | |
| port@18 { | |
| reg = <0x18>; | |
| endpoint { | |
| remote-endpoint = <0xc0>; | |
| phandle = <0x5e>; | |
| }; | |
| }; | |
| port@1b { | |
| reg = <0x1b>; | |
| endpoint { | |
| remote-endpoint = <0xc3>; | |
| phandle = <0x61>; | |
| }; | |
| }; | |
| port@16 { | |
| reg = <0x16>; | |
| endpoint { | |
| remote-endpoint = <0xbf>; | |
| phandle = <0x5b>; | |
| }; | |
| }; | |
| port@d { | |
| reg = <0x0c>; | |
| endpoint { | |
| remote-endpoint = <0xbb>; | |
| phandle = <0x96>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-q6-spdif-pri-tx { | |
| compatible = "qcom,msm-dai-q6-spdif"; | |
| phandle = <0x3e3>; | |
| qcom,msm-dai-q6-dev-id = <0x5001>; | |
| }; | |
| wsa2_core_clk { | |
| qcom,codec-ext-clk-src = <0x0c>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x310>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x474>; | |
| }; | |
| tpdm@10b09000 { | |
| coresight-name = "coresight-tpdm-swao-prio-0"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10b09000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x229>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4f>; | |
| phandle = <0xf8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interconnect@1740000 { | |
| qcom,bcm-voter-names = "hlos\0disp"; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x1740000 0x19080>; | |
| compatible = "qcom,ravelin-mmss_noc"; | |
| qcom,bcm-voters = <0x14e 0x14f>; | |
| phandle = <0x28>; | |
| }; | |
| etm3 { | |
| coresight-name = "coresight-etm3"; | |
| clocks = <0x31>; | |
| cpu = <0x1d>; | |
| qcom,skip-power-up; | |
| reg = <0x12340000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x04>; | |
| clock-names = "apb_pclk"; | |
| arm,primecell-periphid = <0xbb95d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x114>; | |
| phandle = <0x11d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@10d22000 { | |
| coresight-name = "coresight-funnel-ddr_ch01"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10d22000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x24e>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8e>; | |
| phandle = <0x8f>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8d>; | |
| phandle = <0x54>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply_labibb { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| phandle = <0x46d>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-max-voltage = <0x13d620>; | |
| qcom,supply-disable-load = <0x64>; | |
| reg = <0x01>; | |
| qcom,supply-name = "extdvdd"; | |
| qcom,supply-post-off-sleep = <0x0a>; | |
| qcom,supply-min-voltage = <0x13d620>; | |
| qcom,supply-post-on-sleep = <0x0a>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-max-voltage = <0x1e8480>; | |
| qcom,supply-disable-load = <0x50>; | |
| reg = <0x00>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-post-on-sleep = <0x0a>; | |
| qcom,supply-enable-load = <0x30d40>; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| qcom,supply-max-voltage = "\0Us"; | |
| qcom,supply-disable-load = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-name = "lab"; | |
| qcom,supply-min-voltage = <0x5265c0>; | |
| qcom,supply-enable-load = <0x00>; | |
| }; | |
| qcom,panel-supply-entry@3 { | |
| qcom,supply-max-voltage = "\0Us"; | |
| qcom,supply-disable-load = <0x00>; | |
| reg = <0x01>; | |
| qcom,supply-name = "ibb"; | |
| qcom,supply-min-voltage = <0x5265c0>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-enable-load = <0x00>; | |
| }; | |
| }; | |
| rsc@af20000 { | |
| qcom,drv-id = <0x00>; | |
| lable = "disp_rsc"; | |
| clocks = <0x12a 0x16>; | |
| reg-names = "drv-0"; | |
| reg = <0xaf20000 0x10000>; | |
| interrupts = <0x00 0x81 0x04>; | |
| qcom,tcs-offset = <0x1c00>; | |
| compatible = "qcom,rpmh-rsc"; | |
| phandle = <0x2b5>; | |
| qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x04 0x00>; | |
| sde_rsc_rpmh { | |
| cell-index = <0x00>; | |
| compatible = "qcom,sde-rsc-rpmh"; | |
| }; | |
| bcm_voter { | |
| qcom,tcs-wait = <0x01>; | |
| compatible = "qcom,bcm-voter"; | |
| phandle = <0x14f>; | |
| }; | |
| }; | |
| qcom,rimps_log@17d09c00 { | |
| reg = <0x17d09c00 0x200 0x17d09e00 0x200>; | |
| compatible = "qcom,rimps-log"; | |
| phandle = <0x2be>; | |
| mboxes = <0x12e 0x01>; | |
| }; | |
| funnel@10045000 { | |
| coresight-name = "coresight-funnel-merg"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10045000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x265>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf7>; | |
| phandle = <0x100>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xf6>; | |
| phandle = <0xef>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xf5>; | |
| phandle = <0xf4>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,pmic_glink_log { | |
| qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; | |
| compatible = "qcom,pmic-glink"; | |
| qcom,spmi_glink_debug { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| depends-on-supply = <0x162>; | |
| compatible = "qcom,spmi-glink-debug"; | |
| phandle = <0x448>; | |
| spmi@0 { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| reg = <0x00>; | |
| qcom,pm7250b-debug@8 { | |
| qcom,can-sleep; | |
| reg = <0x08 0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| }; | |
| }; | |
| }; | |
| qcom,battery_debug { | |
| compatible = "qcom,battery-debug"; | |
| }; | |
| qcom,charger_ulog_glink { | |
| compatible = "qcom,charger-ulog-glink"; | |
| }; | |
| }; | |
| spf_core_platform { | |
| compatible = "qcom,spf-core-platform"; | |
| phandle = <0x3e7>; | |
| cdc_dmic01_pinctrl { | |
| pinctrl-1 = <0x4a3 0x4a4>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x486>; | |
| pinctrl-0 = <0x4a1 0x4a2>; | |
| }; | |
| qcom,msm-audio-ion-cma { | |
| compatible = "qcom,msm-audio-ion-cma"; | |
| phandle = <0x3e9>; | |
| }; | |
| cdc_dmic23_pinctrl { | |
| pinctrl-1 = <0x4a7 0x4a8>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x487>; | |
| pinctrl-0 = <0x4a5 0x4a6>; | |
| }; | |
| rx_swr_clk_data_pinctrl { | |
| pinctrl-1 = <0x496 0x497 0x498>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x479>; | |
| pinctrl-0 = <0x493 0x494 0x495>; | |
| }; | |
| qcom,msm-audio-ion { | |
| qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>; | |
| qcom,smmu-version = <0x02>; | |
| qcom,smmu-sid-mask = <0x00 0x0f>; | |
| dma-coherent; | |
| compatible = "qcom,msm-audio-ion"; | |
| qcom,smmu-enabled; | |
| phandle = <0x3e8>; | |
| iommus = <0x2f 0x1001 0x00>; | |
| }; | |
| wsa2_swr_clk_data_pinctrl { | |
| status = "disabled"; | |
| pinctrl-1 = <0x491 0x492>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x47e>; | |
| pinctrl-0 = <0x48f 0x490>; | |
| }; | |
| tx_swr_clk_data_pinctrl { | |
| pinctrl-1 = <0x49d 0x49e 0x49f 0x4a0>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x478>; | |
| pinctrl-0 = <0x499 0x49a 0x49b 0x49c>; | |
| }; | |
| lpass-cdc { | |
| clocks = <0x378 0x00 0x379 0x00>; | |
| #size-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| compatible = "qcom,lpass-cdc"; | |
| clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; | |
| phandle = <0x3eb>; | |
| qcom,num-macros = <0x03>; | |
| qcom,lpass-cdc-version = <0x06>; | |
| wcd938x-codec { | |
| qcom,cdc-vdd-buck-current = <0x9eb10>; | |
| qcom,cdc-micbias4-mv = <0x708>; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| qcom,cdc-micbias2-mv = <0x708>; | |
| qcom,rx-slave = <0x484>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; | |
| qcom,tx-slave = <0x485>; | |
| qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; | |
| qcom,cdc-vdd-mic-bias-current = <0x7530>; | |
| cdc-vddio-supply = <0x127>; | |
| qcom,tx_swr_ch_map = <0x00 0x12 0x01 0x00 0x22 0x00 0x13 0x02 0x00 0x23 0x01 0x14 0x01 0x00 0x24 0x01 0x15 0x02 0x00 0x25 0x02 0x16 0x01 0x00 0x26 0x02 0x17 0x02 0x00 0x27 0x02 0x11 0x04 0x00 0x28 0x02 0x18 0x04 0x00 0x28 0x02 0x19 0x08 0x00 0x29 0x03 0x1a 0x01 0x00 0x2a 0x03 0x1b 0x02 0x00 0x2b 0x03 0x1c 0x04 0x00 0x2c 0x03 0x1d 0x08 0x00 0x2d>; | |
| qcom,cdc-vddio-voltage = <0x1b7740 0x1b7740>; | |
| status = "disabled"; | |
| qcom,cdc-vdd-rxtx-current = <0x7530>; | |
| compatible = "qcom,wcd938x-codec"; | |
| cdc-vdd-rxtx-supply = <0x127>; | |
| qcom,wcd-rst-gpio-node = <0x481>; | |
| qcom,cdc-vddio-current = <0x7530>; | |
| qcom,cdc-static-supplies = "cdc-vdd-rxtx\0cdc-vddio\0cdc-vdd-buck"; | |
| phandle = <0x52f>; | |
| qcom,rx_swr_ch_map = <0x00 0x09 0x01 0x00 0x09 0x00 0x0a 0x02 0x00 0x0a 0x01 0x0d 0x01 0x00 0x0d 0x02 0x0b 0x01 0x00 0x0b 0x02 0x0c 0x02 0x00 0x0c 0x03 0x0e 0x01 0x00 0x0e 0x04 0x0f 0x01 0x00 0x0f 0x04 0x10 0x02 0x00 0x10>; | |
| qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
| qcom,split-codec = <0x01>; | |
| qcom,cdc-vdd-rxtx-voltage = <0x1b7740 0x1b7740>; | |
| cdc-vdd-buck-supply = <0x2a6>; | |
| }; | |
| wsa-macro@3240000 { | |
| qcom,thermal-max-state = <0x0b>; | |
| qcom,wsa-bcl-pmic-params = [00 03 48]; | |
| reg = <0x3240000 0x00>; | |
| status = "disabled"; | |
| compatible = "qcom,lpass-cdc-wsa-macro"; | |
| qcom,default-clk-id = <0x06>; | |
| qcom,wsa-swr-gpios = <0x47b>; | |
| phandle = <0x526>; | |
| #cooling-cells = <0x02>; | |
| wsa_swr_master { | |
| qcom,swr-num-ports = <0x08>; | |
| qcom,mipi-sdw-block-packing-mode = <0x00>; | |
| qcom,swr_master_id = <0x01>; | |
| clocks = <0x379 0x00>; | |
| #size-cells = <0x00>; | |
| swrm-io-base = <0x3250000 0x00>; | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| qcom,swr-num-dev = <0x02>; | |
| interrupts = <0x00 0xaa 0x04>; | |
| interrupt-names = "swr_master_irq"; | |
| compatible = "qcom,swr-mstr"; | |
| qcom,dynamic-port-map-supported = <0x00>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,swr-port-mapping = <0x01 0x01 0x01 0x02 0x02 0x0f 0x03 0x03 0x03 0x04 0x05 0x01 0x05 0x06 0x0f 0x06 0x07 0x03 0x07 0x04 0x03 0x08 0x08 0x03>; | |
| phandle = <0x527>; | |
| wsa881x@21170213 { | |
| qcom,spkr-sd-n-node = <0x47c>; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| cdc-vdd-1p8-supply = <0x127>; | |
| wsa_dev_index = <0x01>; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| reg = <0x10 0x21170213>; | |
| sound-name-prefix = "SpkrRight"; | |
| status = "disabled"; | |
| compatible = "qcom,wsa881x"; | |
| qcom,lpass-cdc-handle = <0x3eb>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| phandle = <0x52a>; | |
| }; | |
| wsa883x@02170221 { | |
| qcom,spkr-sd-n-node = <0x47c>; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| cdc-vdd-1p8-supply = <0x127>; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| reg = <0x02 0x2170221>; | |
| sound-name-prefix = "SpkrLeft"; | |
| compatible = "qcom,wsa883x"; | |
| qcom,lpass-cdc-handle = <0x3eb>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| phandle = <0x528>; | |
| }; | |
| wsa883x@02170222 { | |
| qcom,spkr-sd-n-node = <0x47d>; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| cdc-vdd-1p8-supply = <0x127>; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| reg = <0x02 0x2170222>; | |
| sound-name-prefix = "SpkrRight"; | |
| compatible = "qcom,wsa883x"; | |
| qcom,lpass-cdc-handle = <0x3eb>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| phandle = <0x529>; | |
| }; | |
| }; | |
| }; | |
| wsa2-macro@31E0000 { | |
| qcom,wsa2-swr-gpios = <0x47e>; | |
| qcom,wsa2-bcl-pmic-params = [00 03 48]; | |
| qcom,thermal-max-state = <0x0b>; | |
| reg = <0x31e0000 0x00>; | |
| status = "disabled"; | |
| compatible = "qcom,lpass-cdc-wsa2-macro"; | |
| qcom,default-clk-id = <0x07>; | |
| phandle = <0x52b>; | |
| #cooling-cells = <0x02>; | |
| wsa2_swr_master { | |
| qcom,swr-num-ports = <0x08>; | |
| qcom,mipi-sdw-block-packing-mode = <0x00>; | |
| qcom,swr_master_id = <0x04>; | |
| clocks = <0x379 0x00>; | |
| #size-cells = <0x00>; | |
| swrm-io-base = <0x31f0000 0x00>; | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| qcom,swr-num-dev = <0x02>; | |
| interrupts = <0x00 0xab 0x04>; | |
| interrupt-names = "swr_master_irq"; | |
| compatible = "qcom,swr-mstr"; | |
| qcom,dynamic-port-map-supported = <0x00>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,swr-port-mapping = <0x01 0x01 0x01 0x02 0x02 0x0f 0x03 0x03 0x03 0x04 0x05 0x01 0x05 0x06 0x0f 0x06 0x07 0x03 0x07 0x04 0x03 0x08 0x08 0x03>; | |
| phandle = <0x52c>; | |
| wsa883x@02170221 { | |
| qcom,spkr-sd-n-node = <0x47f>; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| cdc-vdd-1p8-supply = <0x127>; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| reg = <0x02 0x2170221>; | |
| sound-name-prefix = "Spkr2Left"; | |
| compatible = "qcom,wsa883x_2"; | |
| qcom,lpass-cdc-handle = <0x3eb>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| phandle = <0x52d>; | |
| }; | |
| wsa883x@02170222 { | |
| qcom,spkr-sd-n-node = <0x480>; | |
| qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; | |
| cdc-vdd-1p8-supply = <0x127>; | |
| qcom,cdc-vdd-1p8-current = <0x4e20>; | |
| reg = <0x02 0x2170222>; | |
| sound-name-prefix = "Spkr2Right"; | |
| compatible = "qcom,wsa883x_2"; | |
| qcom,lpass-cdc-handle = <0x3eb>; | |
| qcom,cdc-static-supplies = "cdc-vdd-1p8"; | |
| phandle = <0x52e>; | |
| }; | |
| }; | |
| }; | |
| wcd937x-codec { | |
| qcom,cdc-vdd-buck-current = <0x58296>; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| qcom,cdc-vddpx-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-micbias2-mv = <0x708>; | |
| qcom,rx-slave = <0x482>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| qcom,cdc-vdd-mic-bias-voltage = <0x387520 0x387520>; | |
| qcom,tx-slave = <0x483>; | |
| qcom,swr-tx-port-params = <0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; | |
| qcom,cdc-vdd-mic-bias-current = <0x1a68>; | |
| qcom,tx_swr_ch_map = <0x00 0x12 0x01 0x493e00 0x22 0x01 0x13 0x01 0x493e00 0x26 0x01 0x14 0x02 0x493e00 0x27 0x02 0x16 0x01 0x00 0x25 0x02 0x17 0x02 0x00 0x26 0x02 0x11 0x04 0x493e00 0x27 0x03 0x18 0x01 0x00 0x28 0x03 0x19 0x02 0x00 0x29 0x03 0x1a 0x04 0x00 0x2a 0x03 0x1b 0x08 0x00 0x2b>; | |
| status = "okay"; | |
| qcom,cdc-vdd-rxtx-current = <0x3642>; | |
| compatible = "qcom,wcd937x-codec"; | |
| cdc-vdd-rxtx-supply = <0x127>; | |
| qcom,cdc-vddpx-current = <0x3642>; | |
| qcom,wcd-rst-gpio-node = <0x481>; | |
| qcom,cdc-static-supplies = "cdc-vdd-rxtx\0cdc-vddpx"; | |
| phandle = <0x489>; | |
| qcom,rx_swr_ch_map = <0x00 0x09 0x01 0x00 0x09 0x00 0x0a 0x02 0x00 0x0a 0x01 0x0d 0x01 0x00 0x0d 0x02 0x0b 0x01 0x00 0x0b 0x02 0x0c 0x02 0x00 0x0c 0x03 0x0e 0x01 0x00 0x0e 0x04 0x0f 0x01 0x00 0x0f 0x04 0x10 0x02 0x00 0x10>; | |
| qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
| qcom,split-codec = <0x01>; | |
| qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; | |
| cdc-vddpx-supply = <0x127>; | |
| qcom,cdc-vdd-rxtx-voltage = <0x1b7740 0x1b7740>; | |
| cdc-vdd-buck-supply = <0x2a6>; | |
| }; | |
| va-macro@33F0000 { | |
| qcom,va-clk-mux-select = <0x01>; | |
| qcom,va-dmic-sample-rate = <0x927c0>; | |
| clocks = <0x379 0x00>; | |
| reg = <0x33f0000 0x00>; | |
| qcom,is-used-swr-gpio = <0x01>; | |
| qcom,va-swr-gpios = <0x478>; | |
| compatible = "qcom,lpass-cdc-va-macro"; | |
| qcom,default-clk-id = <0x00>; | |
| qcom,va-island-mode-muxsel = <0x3420000>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| phandle = <0x521>; | |
| va_swr_master { | |
| qcom,is-always-on = <0x01>; | |
| qcom,swr-num-ports = <0x03>; | |
| qcom,mipi-sdw-block-packing-mode = <0x01>; | |
| qcom,swr_master_id = <0x03>; | |
| qcom,swr-mstr-irq-wakeup-capable = <0x01>; | |
| clocks = <0x379 0x00>; | |
| #size-cells = <0x00>; | |
| swrm-io-base = <0x33b0000 0x00>; | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| qcom,swr-num-dev = <0x05>; | |
| interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; | |
| interrupt-names = "swr_master_irq\0swr_wake_irq"; | |
| compatible = "qcom,swr-mstr"; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,swr-port-mapping = <0x01 0x22 0x01 0x01 0x23 0x02 0x01 0x24 0x04 0x01 0x25 0x08 0x02 0x26 0x01 0x02 0x27 0x02 0x02 0x28 0x04 0x02 0x29 0x08 0x03 0x2a 0x01 0x03 0x2b 0x02 0x03 0x2c 0x04 0x03 0x2d 0x08>; | |
| phandle = <0x522>; | |
| qcom,swr-wakeup-required = <0x01>; | |
| wcd937x-tx-slave { | |
| reg = <0x0a 0x1170223>; | |
| status = "okay"; | |
| compatible = "qcom,wcd937x-slave"; | |
| phandle = <0x483>; | |
| }; | |
| wcd938x-tx-slave { | |
| reg = <0x0d 0x1170223>; | |
| status = "disabled"; | |
| compatible = "qcom,wcd938x-slave"; | |
| phandle = <0x485>; | |
| }; | |
| }; | |
| }; | |
| rx-macro@3200000 { | |
| qcom,rx-swr-gpios = <0x479>; | |
| qcom,rx-bcl-pmic-params = [00 03 48]; | |
| clocks = <0x47a 0x00>; | |
| reg = <0x3200000 0x00>; | |
| compatible = "qcom,lpass-cdc-rx-macro"; | |
| qcom,rx_mclk_mode_muxsel = <0x33a40d8>; | |
| qcom,default-clk-id = <0x05>; | |
| clock-names = "rx_mclk2_2x_clk"; | |
| phandle = <0x524>; | |
| rx_swr_master { | |
| qcom,swr-num-ports = <0x06>; | |
| qcom,mipi-sdw-block-packing-mode = <0x01>; | |
| qcom,swr_master_id = <0x02>; | |
| clocks = <0x379 0x00>; | |
| #size-cells = <0x00>; | |
| swrm-io-base = <0x3210000 0x00>; | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| qcom,swr-num-dev = <0x02>; | |
| interrupts = <0x00 0x9b 0x04>; | |
| interrupt-names = "swr_master_irq"; | |
| compatible = "qcom,swr-mstr"; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,swr-port-mapping = <0x01 0x09 0x01 0x01 0x0a 0x02 0x02 0x0d 0x01 0x03 0x0b 0x01 0x03 0x0c 0x02 0x04 0x0e 0x01 0x05 0x0f 0x01 0x05 0x10 0x02 0x06 0x21 0x01>; | |
| phandle = <0x525>; | |
| wcd937x-rx-slave { | |
| reg = <0x0a 0x1170224>; | |
| status = "okay"; | |
| compatible = "qcom,wcd937x-slave"; | |
| phandle = <0x482>; | |
| }; | |
| wcd938x-rx-slave { | |
| reg = <0x0d 0x1170224>; | |
| status = "disabled"; | |
| compatible = "qcom,wcd938x-slave"; | |
| phandle = <0x484>; | |
| }; | |
| }; | |
| }; | |
| tx-macro@3220000 { | |
| reg = <0x3220000 0x00>; | |
| qcom,is-used-swr-gpio = <0x00>; | |
| compatible = "qcom,lpass-cdc-tx-macro"; | |
| qcom,default-clk-id = <0x00>; | |
| phandle = <0x523>; | |
| qcom,tx-dmic-sample-rate = <0x249f00>; | |
| }; | |
| lpass-cdc-clk-rsc-mngr { | |
| qcom,fs-gen-sequence = <0x3000 0x01 0x01 0x3004 0x03 0x03 0x3004 0x03 0x01 0x3080 0x02 0x02>; | |
| clocks = <0x470 0x00 0x471 0x00 0x472 0x00 0x473 0x00 0x474 0x00 0x475 0x00 0x476 0x00 0x477 0x00>; | |
| qcom,wsa_mclk_mode_muxsel = <0x33a20e0>; | |
| compatible = "qcom,lpass-cdc-clk-rsc-mngr"; | |
| qcom,rx_mclk_mode_muxsel = <0x33a40d8>; | |
| clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0va_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk"; | |
| qcom,va_mclk_mode_muxsel = <0x3420000>; | |
| }; | |
| }; | |
| cdc_dmic45_pinctrl { | |
| pinctrl-1 = <0x4ab 0x4ac>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x488>; | |
| pinctrl-0 = <0x4a9 0x4aa>; | |
| }; | |
| sen_mi2s_pinctrl { | |
| status = "okay"; | |
| pinctrl-1 = <0x4b5 0x4b6 0x4b7 0x4b8>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x48a>; | |
| pinctrl-0 = <0x4b1 0x4b2 0x4b3 0x4b4>; | |
| }; | |
| cdc_dmic67_pinctrl { | |
| status = "disabled"; | |
| pinctrl-1 = <0x4af 0x4b0>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x531>; | |
| pinctrl-0 = <0x4ad 0x4ae>; | |
| }; | |
| lpi_pinctrl@3440000 { | |
| clocks = <0x379 0x00>; | |
| reg = <0x3440000 0x00>; | |
| qcom,lpi-slew-offset-tbl = <0x00 0x02 0x04 0x08 0x0a 0x0c 0x00 0x00 0x00 0x00 0x10 0x12 0x00 0x00 0x06 0x14 0x16 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,slew-reg = <0x34da000 0x00>; | |
| compatible = "qcom,lpi-pinctrl"; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| phandle = <0x3ea>; | |
| qcom,gpios-count = <0x17>; | |
| wsa2_swr_data_pin { | |
| wsa2_swr_data_sleep { | |
| phandle = <0x492>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| wsa2_swr_data_active { | |
| phandle = <0x490>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| bias-bus-hold; | |
| drive-strength = <0x02>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s1_sd0 { | |
| lpi_i2s1_sd0_sleep { | |
| phandle = <0x4c9>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s1_sd0_active { | |
| phandle = <0x4ca>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio8"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm3_sd1 { | |
| lpi_tdm3_sd1_sleep { | |
| phandle = <0x4f7>; | |
| mux { | |
| pins = "gpio22"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_tdm3_sd1_active { | |
| phandle = <0x4f8>; | |
| mux { | |
| pins = "gpio22"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio22"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s2_ws { | |
| lpi_i2s2_ws_sleep { | |
| phandle = <0x4b6>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s2_ws_active { | |
| phandle = <0x4b2>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio11"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s2_sd1 { | |
| lpi_i2s2_sd1_sleep { | |
| phandle = <0x4b8>; | |
| mux { | |
| pins = "gpio13"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s2_sd1_active { | |
| phandle = <0x4b4>; | |
| mux { | |
| pins = "gpio13"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio13"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_aux_ws { | |
| quat_aux_ws_active { | |
| phandle = <0x4fc>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio1"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_aux_ws_sleep { | |
| phandle = <0x4fb>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| dmic01_data_active { | |
| phandle = <0x4a2>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| input-enable; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_i2s2_sck { | |
| lpi_i2s2_sck_sleep { | |
| phandle = <0x4b5>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s2_sck_active { | |
| phandle = <0x4b1>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio10"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sd1 { | |
| lpi_tdm1_sd1_active { | |
| phandle = <0x4e8>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio9"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm1_sd1_sleep { | |
| phandle = <0x4e7>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd0 { | |
| quat_tdm_sd0_sleep { | |
| phandle = <0x4d9>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_tdm_sd0_active { | |
| phandle = <0x4da>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio2"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_sck { | |
| lpi_aux3_sck_sleep { | |
| phandle = <0x515>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_aux3_sck_active { | |
| phandle = <0x516>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio19"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data0_sleep { | |
| phandle = <0x49e>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| bias-bus-hold; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| rx_swr_data_active { | |
| phandle = <0x494>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| bias-bus-hold; | |
| drive-strength = <0x02>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_tdm2_sd0 { | |
| lpi_tdm2_sd0_active { | |
| phandle = <0x4ee>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio15"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm2_sd0_sleep { | |
| phandle = <0x4ed>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_sd1 { | |
| lpi_aux3_sd1_active { | |
| phandle = <0x51c>; | |
| mux { | |
| pins = "gpio22"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio22"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_aux3_sd1_sleep { | |
| phandle = <0x51b>; | |
| mux { | |
| pins = "gpio22"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sck { | |
| lpi_tdm1_sck_sleep { | |
| phandle = <0x4e1>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_tdm1_sck_active { | |
| phandle = <0x4e2>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio6"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_ws { | |
| quat_tdm_ws_active { | |
| phandle = <0x4d8>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio1"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_tdm_ws_sleep { | |
| phandle = <0x4d7>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| spkr_0_sd_n { | |
| spkr_0_sd_n_sleep { | |
| phandle = <0x51d>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| spkr_0_sd_n_active { | |
| phandle = <0x51e>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio0"; | |
| output-high; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data2_active { | |
| phandle = <0x49c>; | |
| mux { | |
| pins = "gpio14"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| bias-bus-hold; | |
| drive-strength = <0x04>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| dmic23_clk_active { | |
| phandle = <0x4a5>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_aux2_ws { | |
| lpi_aux2_ws_sleep { | |
| phandle = <0x50f>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_aux2_ws_active { | |
| phandle = <0x510>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio11"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd3 { | |
| quat_mi2s_sd3_sleep { | |
| phandle = <0x4c3>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "func3"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_mi2s_sd3_active { | |
| phandle = <0x4c4>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "func3"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio5"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| wsa_swr_clk_pin { | |
| wsa_swr_clk_active { | |
| phandle = <0x48b>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| wsa_swr_clk_sleep { | |
| phandle = <0x48d>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| dmic01_data_sleep { | |
| phandle = <0x4a4>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| }; | |
| }; | |
| dmic45_data_active { | |
| phandle = <0x4aa>; | |
| mux { | |
| pins = "gpio13"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| input-enable; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm3_ws { | |
| lpi_tdm3_ws_active { | |
| phandle = <0x4f4>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio20"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm3_ws_sleep { | |
| phandle = <0x4f3>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| wsa2_swr_clk_pin { | |
| wsa2_swr_clk_sleep { | |
| phandle = <0x491>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| wsa2_swr_clk_active { | |
| phandle = <0x48f>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_ws { | |
| quat_mi2s_ws_sleep { | |
| phandle = <0x4bb>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_mi2s_ws_active { | |
| phandle = <0x4bc>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio1"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_ws { | |
| lpi_aux3_ws_sleep { | |
| phandle = <0x517>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_aux3_ws_active { | |
| phandle = <0x518>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio20"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux3_sd0 { | |
| lpi_aux3_sd0_sleep { | |
| phandle = <0x519>; | |
| mux { | |
| pins = "gpio21"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_aux3_sd0_active { | |
| phandle = <0x51a>; | |
| mux { | |
| pins = "gpio21"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio21"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| wsa_swr_data_pin { | |
| wsa_swr_data_sleep { | |
| phandle = <0x48e>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| wsa_swr_data_active { | |
| phandle = <0x48c>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| bias-bus-hold; | |
| drive-strength = <0x02>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s1_sd1 { | |
| lpi_i2s1_sd1_sleep { | |
| phandle = <0x4cb>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s1_sd1_active { | |
| phandle = <0x4cc>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio9"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_sck { | |
| lpi_tdm2_sck_sleep { | |
| phandle = <0x4e9>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_tdm2_sck_active { | |
| phandle = <0x4ea>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio10"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| dmic67_data_active { | |
| phandle = <0x4ae>; | |
| mux { | |
| pins = "gpio18"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| input-enable; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm3_sck { | |
| lpi_tdm3_sck_active { | |
| phandle = <0x4f2>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio19"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm3_sck_sleep { | |
| phandle = <0x4f1>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| tx_swr_clk_active { | |
| phandle = <0x499>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio0"; | |
| drive-strength = <0x04>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_i2s3_sd1 { | |
| lpi_i2s3_sd1_active { | |
| phandle = <0x4d4>; | |
| mux { | |
| pins = "gpio22"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio22"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_i2s3_sd1_sleep { | |
| phandle = <0x4d3>; | |
| mux { | |
| pins = "gpio22"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio22"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s3_sd0 { | |
| lpi_i2s3_sd0_active { | |
| phandle = <0x4d2>; | |
| mux { | |
| pins = "gpio21"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio21"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_i2s3_sd0_sleep { | |
| phandle = <0x4d1>; | |
| mux { | |
| pins = "gpio21"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| dmic23_clk_sleep { | |
| phandle = <0x4a7>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio8"; | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| rx_swr_data1_active { | |
| phandle = <0x495>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| bias-bus-hold; | |
| drive-strength = <0x02>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| quat_tdm_sd2 { | |
| quat_tdm_sd2_active { | |
| phandle = <0x4de>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio4"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_tdm_sd2_sleep { | |
| phandle = <0x4dd>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sd1 { | |
| lpi_aux1_sd1_active { | |
| phandle = <0x50c>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio9"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_aux1_sd1_sleep { | |
| phandle = <0x50b>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| dmic67_data_sleep { | |
| phandle = <0x4b0>; | |
| mux { | |
| pins = "gpio18"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| }; | |
| }; | |
| quat_mi2s_sck { | |
| quat_mi2s_sck_active { | |
| phandle = <0x4ba>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio0"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_mi2s_sck_sleep { | |
| phandle = <0x4b9>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_ws { | |
| lpi_aux1_ws_active { | |
| phandle = <0x508>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio7"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_aux1_ws_sleep { | |
| phandle = <0x507>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s3_ws { | |
| lpi_i2s3_ws_active { | |
| phandle = <0x4d0>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio20"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_i2s3_ws_sleep { | |
| phandle = <0x4cf>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd2 { | |
| quat_aux_sd2_sleep { | |
| phandle = <0x501>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_aux_sd2_active { | |
| phandle = <0x502>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio4"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_ws { | |
| lpi_tdm2_ws_active { | |
| phandle = <0x4ec>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio11"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm2_ws_sleep { | |
| phandle = <0x4eb>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s2_sd0 { | |
| lpi_i2s2_sd0_sleep { | |
| phandle = <0x4b7>; | |
| mux { | |
| pins = "gpio12"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s2_sd0_active { | |
| phandle = <0x4b3>; | |
| mux { | |
| pins = "gpio12"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio12"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd2 { | |
| quat_mi2s_sd2_sleep { | |
| phandle = <0x4c1>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_mi2s_sd2_active { | |
| phandle = <0x4c2>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio4"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data_sleep { | |
| phandle = <0x497>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s1_ws { | |
| lpi_i2s1_ws_active { | |
| phandle = <0x4c8>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio7"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_i2s1_ws_sleep { | |
| phandle = <0x4c7>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_ws { | |
| lpi_tdm1_ws_active { | |
| phandle = <0x4e4>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio7"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm1_ws_sleep { | |
| phandle = <0x4e3>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| dmic67_clk_sleep { | |
| phandle = <0x4af>; | |
| mux { | |
| pins = "gpio17"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio17"; | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| dmic23_data_active { | |
| phandle = <0x4a6>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| input-enable; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| tx_swr_data0_active { | |
| phandle = <0x49a>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| bias-bus-hold; | |
| drive-strength = <0x04>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| spkr_3_sd_n { | |
| spkr_3_sd_n_sleep { | |
| phandle = <0x51f>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| spkr_3_sd_n_active { | |
| phandle = <0x520>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio3"; | |
| output-high; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| }; | |
| dmic01_clk_sleep { | |
| phandle = <0x4a3>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio6"; | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_tdm_sck { | |
| quat_tdm_sck_sleep { | |
| phandle = <0x4d5>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_tdm_sck_active { | |
| phandle = <0x4d6>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio0"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd3 { | |
| quat_aux_sd3_sleep { | |
| phandle = <0x503>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "func3"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_aux_sd3_active { | |
| phandle = <0x504>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "func3"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio5"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd3 { | |
| quat_tdm_sd3_sleep { | |
| phandle = <0x4df>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "func3"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_tdm_sd3_active { | |
| phandle = <0x4e0>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "func3"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio5"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_sd1 { | |
| lpi_tdm2_sd1_active { | |
| phandle = <0x4f0>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio16"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm2_sd1_sleep { | |
| phandle = <0x4ef>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd1 { | |
| quat_tdm_sd1_active { | |
| phandle = <0x4dc>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio3"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_tdm_sd1_sleep { | |
| phandle = <0x4db>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data1_active { | |
| phandle = <0x49b>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| bias-bus-hold; | |
| drive-strength = <0x04>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_aux2_sck { | |
| lpi_aux2_sck_sleep { | |
| phandle = <0x50d>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_aux2_sck_active { | |
| phandle = <0x50e>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio10"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd0 { | |
| quat_mi2s_sd0_active { | |
| phandle = <0x4be>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio2"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_mi2s_sd0_sleep { | |
| phandle = <0x4bd>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sd0 { | |
| lpi_aux1_sd0_sleep { | |
| phandle = <0x509>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_aux1_sd0_active { | |
| phandle = <0x50a>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio8"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_sd0 { | |
| lpi_aux2_sd0_active { | |
| phandle = <0x512>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio15"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_aux2_sd0_sleep { | |
| phandle = <0x511>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd1 { | |
| quat_mi2s_sd1_active { | |
| phandle = <0x4c0>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio3"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_mi2s_sd1_sleep { | |
| phandle = <0x4bf>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_sd1 { | |
| lpi_aux2_sd1_active { | |
| phandle = <0x514>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio16"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_aux2_sd1_sleep { | |
| phandle = <0x513>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| dmic23_data_sleep { | |
| phandle = <0x4a8>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| }; | |
| }; | |
| dmic45_data_sleep { | |
| phandle = <0x4ac>; | |
| mux { | |
| pins = "gpio13"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| }; | |
| }; | |
| dmic67_clk_active { | |
| phandle = <0x4ad>; | |
| mux { | |
| pins = "gpio17"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_tdm3_sd0 { | |
| lpi_tdm3_sd0_sleep { | |
| phandle = <0x4f5>; | |
| mux { | |
| pins = "gpio21"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_tdm3_sd0_active { | |
| phandle = <0x4f6>; | |
| mux { | |
| pins = "gpio21"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio21"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sd0 { | |
| lpi_tdm1_sd0_sleep { | |
| phandle = <0x4e5>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_tdm1_sd0_active { | |
| phandle = <0x4e6>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio8"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| dmic45_clk_active { | |
| phandle = <0x4a9>; | |
| mux { | |
| pins = "gpio12"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_aux_sd1 { | |
| quat_aux_sd1_sleep { | |
| phandle = <0x4ff>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_aux_sd1_active { | |
| phandle = <0x500>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio3"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sck { | |
| quat_aux_sck_sleep { | |
| phandle = <0x4f9>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| quat_aux_sck_active { | |
| phandle = <0x4fa>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio0"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd0 { | |
| quat_aux_sd0_active { | |
| phandle = <0x4fe>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio2"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| quat_aux_sd0_sleep { | |
| phandle = <0x4fd>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sck { | |
| lpi_aux1_sck_sleep { | |
| phandle = <0x505>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_aux1_sck_active { | |
| phandle = <0x506>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio6"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| dmic45_clk_sleep { | |
| phandle = <0x4ab>; | |
| mux { | |
| pins = "gpio12"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio12"; | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s1_sck { | |
| lpi_i2s1_sck_active { | |
| phandle = <0x4c6>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "func2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio6"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| lpi_i2s1_sck_sleep { | |
| phandle = <0x4c5>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data1_sleep { | |
| phandle = <0x49f>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s3_sck { | |
| lpi_i2s3_sck_sleep { | |
| phandle = <0x4cd>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_i2s3_sck_active { | |
| phandle = <0x4ce>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio19"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| rx_swr_clk_sleep { | |
| phandle = <0x496>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| rx_swr_clk_active { | |
| phandle = <0x493>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "func1"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| rx_swr_data1_sleep { | |
| phandle = <0x498>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| tx_swr_clk_sleep { | |
| phandle = <0x49d>; | |
| mux { | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| function = "func1"; | |
| input-enable; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| tx_swr_data2_sleep { | |
| phandle = <0x4a0>; | |
| mux { | |
| pins = "gpio14"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| dmic01_clk_active { | |
| phandle = <0x4a1>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| wsa_swr_clk_data_pinctrl { | |
| status = "disabled"; | |
| pinctrl-1 = <0x48d 0x48e>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| #gpio-cells = <0x00>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x47b>; | |
| pinctrl-0 = <0x48b 0x48c>; | |
| }; | |
| sound { | |
| qcom,msm-mbhc-gnd-swh = <0x00>; | |
| qcom,msm-mbhc-hphl-swh = <0x01>; | |
| qcom,msm_audio_ssr_devs = <0x3f6 0x3ea 0x3eb>; | |
| qcom,cdc-dmic01-gpios = <0x486>; | |
| qcom,afe-rxtx-lb = <0x00>; | |
| qcom,mi2s-tdm-is-hw-vote-needed = <0x01 0x00 0x01 0x00 0x00 0x00>; | |
| qcom,msm-mbhc-usbc-audio-supported = <0x00>; | |
| qcom,cdc-dmic45-gpios = <0x488>; | |
| qcom,tdm-max-slots = <0x08>; | |
| qcom,upd_lpass_reg_addr = <0x418 0x33b0300>; | |
| clocks = <0x379 0x00>; | |
| qcom,auxpcm-audio-intf = <0x01>; | |
| qcom,mi2s-audio-intf = <0x01>; | |
| qcom,upd_backends_used = "wcd"; | |
| qcom,wsa-max-devs = <0x00>; | |
| fsa4480-i2c-handle = <0x342>; | |
| qcom,cdc-dmic23-gpios = <0x487>; | |
| qcom,ext-disp-audio-rx = <0x00>; | |
| qcom,sen-mi2s-gpios = <0x48a>; | |
| qcom,msm-mi2s-master = <0x01 0x01 0x01 0x01 0x01 0x01>; | |
| compatible = "qcom,waipio-asoc-snd"; | |
| asoc-codec = <0x384 0x3eb 0x489>; | |
| qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01>; | |
| qcom,audio-routing = "AMIC1\0Analog Mic1\0AMIC1\0MIC BIAS1\0AMIC2\0Analog Mic2\0AMIC2\0MIC BIAS2\0AMIC3\0Analog Mic3\0AMIC3\0MIC BIAS3\0TX DMIC0\0Digital Mic0\0TX DMIC0\0MIC BIAS3\0TX DMIC1\0Digital Mic1\0TX DMIC1\0MIC BIAS3\0TX DMIC2\0Digital Mic2\0TX DMIC2\0MIC BIAS1\0TX DMIC3\0Digital Mic3\0TX DMIC3\0MIC BIAS1\0IN1_HPHL\0HPHL_OUT\0IN2_HPHR\0HPHR_OUT\0IN3_AUX\0AUX_OUT\0RX_TX DEC0_INP\0TX DEC0 MUX\0RX_TX DEC1_INP\0TX DEC1 MUX\0RX_TX DEC2_INP\0TX DEC2 MUX\0RX_TX DEC3_INP\0TX DEC3 MUX\0TX SWR_INPUT\0WCD_TX_OUTPUT\0VA SWR_INPUT\0VA_SWR_CLK\0VA SWR_INPUT\0WCD_TX_OUTPUT\0VA_AIF1 CAP\0VA_SWR_CLK\0VA_AIF2 CAP\0VA_SWR_CLK\0VA_AIF3 CAP\0VA_SWR_CLK\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC0\0VA MIC BIAS3\0VA DMIC1\0VA MIC BIAS3\0VA DMIC2\0VA MIC BIAS1\0VA DMIC3\0VA MIC BIAS1"; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01>; | |
| phandle = <0x530>; | |
| qcom,model = "ravelin-idp-snd-card"; | |
| qcom,upd_ear_pa_reg_addr = <0x300a>; | |
| qcom,wcn-btfm = <0x01>; | |
| asoc-codec-names = "msm-stub-codec.1\0lpass-cdc\0wcd937x_codec"; | |
| qcom,wcn-bt = <0x00>; | |
| }; | |
| }; | |
| reboot_reason { | |
| nvmem-cells = <0x400>; | |
| compatible = "qcom,reboot-reason"; | |
| nvmem-cell-names = "restart_reason"; | |
| }; | |
| debug-clock-controller@0 { | |
| qcom,gcc = <0x24>; | |
| qcom,gpucc = <0x23>; | |
| #clock-cells = <0x01>; | |
| clocks = <0x45 0x00 0x24 0x00 0x135 0x00 0x12a 0x00 0x23 0x00>; | |
| qcom,mccc = <0x137>; | |
| qcom,camcc = <0x135>; | |
| compatible = "qcom,ravelin-debugcc"; | |
| clock-names = "xo_clk_src\0gcc\0camcc\0dispcc\0gpucc"; | |
| qcom,apsscc = <0x136>; | |
| phandle = <0x2c3>; | |
| qcom,dispcc = <0x12a>; | |
| }; | |
| tpdm@10c20000 { | |
| coresight-name = "coresight-tpdm-sdcc"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x10c20000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x234>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5d>; | |
| phandle = <0xdd>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,mpm2-sleep-counter@c221000 { | |
| reg = <0xc221000 0x1000>; | |
| clock-frequency = <0x8000>; | |
| compatible = "qcom,mpm2-sleep-counter"; | |
| }; | |
| qcom,smp2p-adsp { | |
| qcom,smem = <0x1bb 0x1ad>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x02>; | |
| interrupts = <0x03 0x02 0x01>; | |
| interrupt-parent = <0x13b>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x13b 0x03 0x02>; | |
| qcom,smp2p-rdbg2-out { | |
| qcom,entry-name = "rdbg"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x1f9>; | |
| }; | |
| qcom,sleepstate-in { | |
| qcom,entry-name = "sleepstate_see"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x13d>; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x157>; | |
| }; | |
| sleepstate-out { | |
| qcom,entry-name = "sleepstate"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x13c>; | |
| }; | |
| qcom,smp2p-rdbg2-in { | |
| qcom,entry-name = "rdbg"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1fa>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x156>; | |
| }; | |
| }; | |
| psci { | |
| method = "smc"; | |
| compatible = "arm,psci-1.0"; | |
| cpu-pd4 { | |
| power-domains = <0x123>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x10>; | |
| }; | |
| cpu-pd2 { | |
| power-domains = <0x123>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x0c>; | |
| }; | |
| cpu-pd1 { | |
| power-domains = <0x123>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x0a>; | |
| }; | |
| cpu-pd7 { | |
| power-domains = <0x123>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x18>; | |
| }; | |
| cpu-pd6 { | |
| power-domains = <0x123>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x16>; | |
| }; | |
| cpu-pd3 { | |
| power-domains = <0x123>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x0e>; | |
| }; | |
| cpu-pd0 { | |
| power-domains = <0x123>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x06>; | |
| }; | |
| cluster-pd { | |
| #power-domain-cells = <0x00>; | |
| domain-idle-states = <0x12b 0x12c>; | |
| phandle = <0x123>; | |
| }; | |
| cpu-pd5 { | |
| power-domains = <0x123>; | |
| #power-domain-cells = <0x00>; | |
| phandle = <0x12>; | |
| }; | |
| }; | |
| tpdm@10c29000 { | |
| coresight-name = "coresight-tpdm-ipcc"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10c29000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x238>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x61>; | |
| phandle = <0xc3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@17200000 { | |
| #redistributor-regions = <0x01>; | |
| reg = <0x17200000 0x10000 0x17260000 0x100000>; | |
| interrupts = <0x01 0x09 0x08>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x03>; | |
| compatible = "arm,gic-v3"; | |
| phandle = <0x01>; | |
| redistributor-stride = <0x00 0x20000>; | |
| }; | |
| qmi-ts-sensors { | |
| compatible = "qcom,qmi-sensors"; | |
| phandle = <0x164>; | |
| #thermal-sensor-cells = <0x01>; | |
| modem { | |
| qcom,instance-id = <0x00>; | |
| qcom,qmi-sensor-names = "pa\0pa_1\0modem_bcl_warn\0modem_cfg\0lte_cc\0mcg_fr1_cc\0scg_fr1_cc\0sub1_modem_cfg\0sub1_lte_cc\0sub1_mcg_fr1_cc\0sub1_scg_fr1_cc\0sdr0_pa0\0sdr1_pa0\0sdr0\0sdr1"; | |
| }; | |
| }; | |
| remoteproc-adsp@03000000 { | |
| qcom,smem-states = <0x157 0x00>; | |
| qcom,smem-state-names = "stop"; | |
| qcom,qmp = <0x31>; | |
| interrupts-extended = <0x3b 0x06 0x01 0x156 0x00 0x00 0x156 0x02 0x00 0x156 0x01 0x00 0x156 0x03 0x00 0x156 0x07 0x00>; | |
| clocks = <0x45 0x00>; | |
| reg-names = "cx\0mx"; | |
| reg = <0x3000000 0x10000>; | |
| mx-supply = <0x154>; | |
| interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack"; | |
| interconnect-names = "crypto_ddr"; | |
| status = "ok"; | |
| interconnects = <0x3c 0x26 0x29 0x200>; | |
| compatible = "qcom,ravelin-adsp-pas"; | |
| cx-supply = <0x153>; | |
| memory-region = <0x155>; | |
| clock-names = "xo"; | |
| phandle = <0x2d4>; | |
| cx-uV-uA = <0x180 0x00>; | |
| mx-uV-uA = <0x180 0x00>; | |
| glink-edge { | |
| qcom,remote-pid = <0x02>; | |
| interrupts = <0x03 0x00 0x01>; | |
| interrupt-parent = <0x13b>; | |
| mbox-names = "adsp_smem"; | |
| transport = "smem"; | |
| phandle = <0x2d5>; | |
| label = "adsp"; | |
| mboxes = <0x13b 0x03 0x00>; | |
| qcom,glink-label = "lpass"; | |
| qcom,pmic_glink_rpmsg { | |
| qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; | |
| }; | |
| qcom,adsp_qrtr { | |
| qcom,no-wake-svc = <0x190>; | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| qcom,pmic_glink_log_rpmsg { | |
| qcom,intents = <0x800 0x05 0xc00 0x03 0x2000 0x01>; | |
| qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; | |
| }; | |
| qcom,msm_fastrpc_rpmsg { | |
| qcom,intents = <0x64 0x40>; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| compatible = "qcom,msm-fastrpc-rpmsg"; | |
| }; | |
| qcom,gpr { | |
| qcom,intents = <0x200 0x14>; | |
| reg = <0x02>; | |
| qcom,glink-channels = "adsp_apps"; | |
| compatible = "qcom,gpr"; | |
| phandle = <0x3f6>; | |
| audio-pkt { | |
| reg = <0x17>; | |
| compatible = "qcom,audio-pkt"; | |
| qcom,audiopkt-ch-name = "apr_audio_svc"; | |
| }; | |
| q6prm { | |
| reg = <0x07>; | |
| compatible = "qcom,audio_prm"; | |
| phandle = <0x3f7>; | |
| }; | |
| spf_core { | |
| reg = <0x03>; | |
| compatible = "qcom,spf_core"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| spi@a90000 { | |
| dmas = <0x1c4 0x00 0x04 0x01 0x40 0x00 0x1c4 0x01 0x04 0x01 0x40 0x00>; | |
| qcom,wrapper-core = <0x1c0>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x52 0x24 0x56 0x24 0x57>; | |
| #size-cells = <0x00>; | |
| reg-names = "se_phys"; | |
| #address-cells = <0x01>; | |
| spi-max-frequency = <0x2faf080>; | |
| reg = <0xa90000 0x4000>; | |
| interrupts = <0x00 0x165 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1e1>; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x345>; | |
| pinctrl-0 = <0x1dd 0x1de 0x1df 0x1e0>; | |
| }; | |
| qcom,msm-stub-codec { | |
| compatible = "qcom,msm-stub-codec"; | |
| phandle = <0x384>; | |
| }; | |
| mem_dump { | |
| compatible = "qcom,mem-dump"; | |
| memory-region = <0x122>; | |
| pmic { | |
| qcom,dump-size = <0x200000>; | |
| qcom,dump-id = <0xe4>; | |
| }; | |
| rpmh { | |
| qcom,dump-size = <0x400000>; | |
| qcom,dump-id = <0xec>; | |
| }; | |
| l2_tlb600 { | |
| qcom,dump-size = <0x6100>; | |
| qcom,dump-id = <0x126>; | |
| }; | |
| rpm_sw { | |
| qcom,dump-size = <0x28000>; | |
| qcom,dump-id = <0xea>; | |
| }; | |
| etf_lpass { | |
| qcom,dump-size = <0x4000>; | |
| qcom,dump-id = <0xf4>; | |
| }; | |
| l2_tlb100 { | |
| qcom,dump-size = <0x5b00>; | |
| qcom,dump-id = <0x121>; | |
| }; | |
| l1_icache500 { | |
| qcom,dump-size = <0x10900>; | |
| qcom,dump-id = <0x65>; | |
| }; | |
| l2_tlb0 { | |
| qcom,dump-size = <0x5b00>; | |
| qcom,dump-id = <0x120>; | |
| }; | |
| l1_icache700 { | |
| qcom,dump-size = <0x15100>; | |
| qcom,dump-id = <0x67>; | |
| }; | |
| c0_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x00>; | |
| }; | |
| l1_dtlb600 { | |
| qcom,dump-size = <0x300>; | |
| qcom,dump-id = <0x46>; | |
| }; | |
| l1_dcache500 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x85>; | |
| }; | |
| misc_data { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0xe8>; | |
| }; | |
| l2_tlb500 { | |
| qcom,dump-size = <0x5b00>; | |
| qcom,dump-id = <0x125>; | |
| }; | |
| c600_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x06>; | |
| }; | |
| cpuss_reg { | |
| qcom,dump-size = <0x30000>; | |
| qcom,dump-id = <0xef>; | |
| }; | |
| pcu_reg { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x164>; | |
| }; | |
| l1_dcache300 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x83>; | |
| }; | |
| c400_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x04>; | |
| }; | |
| etfswao_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x102>; | |
| }; | |
| l1_dcache600 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x86>; | |
| }; | |
| l1_icache0 { | |
| qcom,dump-size = <0x10900>; | |
| qcom,dump-id = <0x60>; | |
| }; | |
| etr1_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x105>; | |
| }; | |
| l1_icache100 { | |
| qcom,dump-size = <0x10900>; | |
| qcom,dump-id = <0x61>; | |
| }; | |
| c700_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x07>; | |
| }; | |
| c100_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x01>; | |
| }; | |
| fcm { | |
| qcom,dump-size = <0x8400>; | |
| qcom,dump-id = <0xee>; | |
| }; | |
| l1_icache600 { | |
| qcom,dump-size = <0x15100>; | |
| qcom,dump-id = <0x66>; | |
| }; | |
| l1_icache200 { | |
| qcom,dump-size = <0x10900>; | |
| qcom,dump-id = <0x62>; | |
| }; | |
| l1_itlb600 { | |
| qcom,dump-size = <0x300>; | |
| qcom,dump-id = <0x26>; | |
| }; | |
| l1_dcache0 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x80>; | |
| }; | |
| l1_dcache700 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x87>; | |
| }; | |
| l1_icache300 { | |
| qcom,dump-size = <0x10900>; | |
| qcom,dump-id = <0x63>; | |
| }; | |
| l1_dcache200 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x82>; | |
| }; | |
| l1_icache400 { | |
| qcom,dump-size = <0x10900>; | |
| qcom,dump-id = <0x64>; | |
| }; | |
| etr_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x100>; | |
| }; | |
| c500_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x05>; | |
| }; | |
| l1_dcache400 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x84>; | |
| }; | |
| l2_tlb300 { | |
| qcom,dump-size = <0x5b00>; | |
| qcom,dump-id = <0x123>; | |
| }; | |
| l2_tlb700 { | |
| qcom,dump-size = <0x6100>; | |
| qcom,dump-id = <0x127>; | |
| }; | |
| l2_cache700 { | |
| qcom,dump-size = <0x48100>; | |
| qcom,dump-id = <0xc7>; | |
| }; | |
| l2_tlb400 { | |
| qcom,dump-size = <0x5b00>; | |
| qcom,dump-id = <0x124>; | |
| }; | |
| l1_itlb700 { | |
| qcom,dump-size = <0x300>; | |
| qcom,dump-id = <0x27>; | |
| }; | |
| l2_cache600 { | |
| qcom,dump-size = <0x48100>; | |
| qcom,dump-id = <0xc6>; | |
| }; | |
| fsm_data { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x165>; | |
| }; | |
| l1_dtlb700 { | |
| qcom,dump-size = <0x300>; | |
| qcom,dump-id = <0x47>; | |
| }; | |
| etflpass_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x104>; | |
| }; | |
| osm_reg { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x163>; | |
| }; | |
| l1_dcache100 { | |
| qcom,dump-size = <0x9100>; | |
| qcom,dump-id = <0x81>; | |
| }; | |
| c200_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x02>; | |
| }; | |
| etf_swao { | |
| qcom,dump-size = <0x10000>; | |
| qcom,dump-id = <0xf1>; | |
| }; | |
| c300_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x03>; | |
| }; | |
| l2_tlb200 { | |
| qcom,dump-size = <0x5b00>; | |
| qcom,dump-id = <0x122>; | |
| }; | |
| }; | |
| qcom,msm-rtb { | |
| compatible = "qcom,msm-rtb"; | |
| qcom,rtb-size = <0x100000>; | |
| }; | |
| qcom,gpi-dma@900000 { | |
| qcom,gpii-mask = <0x3e>; | |
| qcom,ev-factor = <0x02>; | |
| qcom,iommu-dma-addr-pool = <0x100000 0x100000>; | |
| qcom,gpi-ee-offset = <0x10000>; | |
| qcom,max-num-gpii = <0x0c>; | |
| reg-names = "gpi-top"; | |
| #dma-cells = <0x05>; | |
| reg = <0x900000 0x60000>; | |
| interrupts = <0x00 0xf4 0x04 0x00 0xf5 0x04 0x00 0xf6 0x04 0x00 0xf7 0x04 0x00 0xf8 0x04 0x00 0xf9 0x04 0x00 0xfa 0x04 0x00 0xfb 0x04 0x00 0xfc 0x04 0x00 0xfd 0x04 0x00 0xfe 0x04 0x00 0xff 0x04>; | |
| status = "ok"; | |
| dma-coherent; | |
| compatible = "qcom,gpi-dma"; | |
| phandle = <0x1a1>; | |
| iommus = <0x2f 0x176 0x00>; | |
| qcom,static-gpii-mask = <0x01>; | |
| }; | |
| qcom,mdss_mdp@ae00000 { | |
| qcom,sde-min-llcc-ib-kbps = <0x00>; | |
| qcom,sde-dsc-hw-rev = "dsc_1_2"; | |
| qcom,sde-intf-off = <0x00 0x36000>; | |
| qcom,sde-has-cdp; | |
| qcom,sde-dither-version = <0x20000>; | |
| qcom,sde-sspp-csc-off = <0x1a00>; | |
| qcom,sde-dspp-top-size = <0x80>; | |
| qcom,sde-sspp-linewidth = <0x1000>; | |
| qcom,sde-vbif-id = <0x00>; | |
| qcom,sde-dsc-ctl-size = <0x10>; | |
| qcom,sde-dsc-ctl = <0xf00>; | |
| qcom,sde-uidle-off = <0x80000>; | |
| qcom,sde-uidle-size = <0x70>; | |
| qcom,sde-max-trusted-vm-displays = <0x01>; | |
| qcom,sde-dspp-top-off = <0x1300>; | |
| qcom,sde-dsc-linewidth = <0xa00>; | |
| qcom,sde-max-bw-high-kbps = <0x08 0x70ea40 0x07 0x6acfc0>; | |
| qcom,sde-danger-lut = <0x3fffff 0x3fffff 0x00 0x00 0x00 0x3ffffff 0x3ffffff 0x3ffffff 0x3ffffff 0x00 0x00 0x00 0x3ffffff 0x3ffffff>; | |
| qcom,sde-lm-noise-off = <0x320>; | |
| qcom,sde-safe-lut = <0xf800 0xf800 0x00 0x00 0x00 0xe000 0xe000 0xe000 0xe000 0x00 0x00 0x00 0xe000 0xe000>; | |
| qcom,sde-dram-channels = <0x02>; | |
| qcom,sde-reg-dma-version = <0x20000>; | |
| qcom,sde-ctl-display-pref = "primary"; | |
| qcom,sde-vbif-memtype-1 = <0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-len = <0x494>; | |
| qcom,sde-vbif-qos-lutdma-remap = <0x03 0x03 0x03 0x03 0x04 0x04 0x04 0x06 0x03 0x03 0x03 0x03 0x04 0x04 0x04 0x06>; | |
| qcom,sde-sspp-excl-rect = <0x01 0x01>; | |
| qcom,sde-lm-noise-version = <0x10000>; | |
| qcom,sde-qos-cpu-mask = <0x03>; | |
| qcom,sde-has-idle-pc; | |
| qcom,sde-intf-tear-irq-off = <0x00 0x36800>; | |
| qcom,sde-ib-bw-vote = <0x2625a0 0x00 0x186a00>; | |
| qcom,sde-vbif-default-ot-wr-limit = <0x20>; | |
| qcom,sde-reg-dma-trigger-off = <0x119c>; | |
| qcom,sde-vbif-dynamic-ot-wr-limit = <0x3b53800 0x02 0x76a7000 0x06 0x1da9c000 0x10>; | |
| clocks = <0x24 0x17 0x12a 0x03 0x12a 0x0c 0x12a 0x0d 0x12a 0x19 0x12a 0x0f 0x12a 0x14>; | |
| qcom,sde-dither-size = <0x20>; | |
| qcom,sde-mixer-pair-mask = <0x00>; | |
| qcom,sde-pp-slave = <0x00>; | |
| qcom,sde-vbif-qos-rt-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>; | |
| qcom,sde-smart-panel-align-mode = <0x0c>; | |
| qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x12110 0x00 0x4c4b40 0x00 0x9402a0>; | |
| reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0sid_phys"; | |
| qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; | |
| qcom,sde-cdp-setting = <0x01 0x01 0x01 0x00>; | |
| qcom,sde-ddr-type = <0x08 0x07>; | |
| qcom,sde-sspp-xin-id = <0x00 0x01>; | |
| qcom,sde-dspp-rc-size = <0x100>; | |
| qcom,sde-sspp-type = "vig\0dma"; | |
| qcom,sde-intf-type = "none\0dsi"; | |
| qcom,sde-sspp-src-size = <0x328>; | |
| #power-domain-cells = <0x00>; | |
| qcom,sde-dsc-native422-supp = <0x01>; | |
| qcom,sde-qseed-scalar-version = <0x3001>; | |
| qcom,sde-reg-dma-off = <0x00 0x400>; | |
| reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaeac000 0x800 0xae8f000 0x30>; | |
| qcom,sde-dspp-off = <0x55000>; | |
| interrupts = <0x00 0x53 0x04>; | |
| qcom,sde-intf-size = <0x2c4>; | |
| qcom,sde-dspp-rc-version = <0x10000>; | |
| qcom,sde-highest-bank-bit = <0x08 0x02 0x07 0x01>; | |
| qcom,sde-sspp-smart-dma-priority = <0x02 0x01>; | |
| qcom,sde-has-dim-layer; | |
| clock-rate = <0x00 0x00 0x1e28f280 0x1e28f280 0x124f800 0x1e28f280 0xbebc200>; | |
| qcom,sde-ubwc-bw-calc-version = <0x01>; | |
| qcom,sde-ctl-size = <0x204>; | |
| qcom,sde-mixer-off = <0x45000>; | |
| qcom,sde-qos-refresh-rates = <0x78 0xf0>; | |
| qcom,sde-dsc-off = <0x81000>; | |
| qcom,sde-num-nrt-paths = <0x00>; | |
| qcom,sde-max-bw-low-kbps = <0x08 0x61a800 0x07 0x401640>; | |
| qcom,sde-dsc-size = <0x10>; | |
| qcom,sde-min-dram-ib-kbps = <0x186a00>; | |
| interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; | |
| qcom,sde-smart-dma-rev = "smart_dma_v2p5"; | |
| interrupt-controller; | |
| qcom,sde-dspp-rc-mem-size = <0xaa0>; | |
| qcom,sde-vbif-size = <0x1040>; | |
| interconnects = <0x28 0x17 0x25 0x234 0x29 0x03 0x29 0x200 0x25 0x02 0x3d 0x20c>; | |
| qcom,sde-dsc-enc = <0x100>; | |
| qcom,sde-has-src-split; | |
| #interrupt-cells = <0x01>; | |
| qcom,sde-dither-off = <0xe0>; | |
| qcom,sde-off = <0x1000>; | |
| qcom,sde-secure-sid-mask = <0x801 0xc01>; | |
| compatible = "qcom,sde-kms"; | |
| qcom,sde-vbif-memtype-0 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| connectors = <0x456 0x376 0x377>; | |
| qcom,sde-vm-exclude-reg-names = "sid_phys"; | |
| qcom,sde-pp-off = <0x6a000>; | |
| qcom,sde-sspp-clk-status = <0x2b0 0x00 0x2b0 0x0c>; | |
| qcom,sde-mixer-size = <0x400>; | |
| qcom,sde-mixer-display-pref = "primary"; | |
| qcom,sde-vbif-off = <0x00>; | |
| qcom,sde-qos-cpu-mask-performance = <0x0f>; | |
| qcom,sde-dspp-size = <0x1800>; | |
| qcom,sde-vig-sspp-linewidth = <0x1400>; | |
| qcom,sde-qos-cpu-dma-latency = <0x12c>; | |
| qcom,sde-dspp-rc-off = <0x15800>; | |
| qcom,sde-reg-dma-id = <0x00 0x01>; | |
| qcom,sde-csc-type = "csc-10bit"; | |
| qcom,sde-pp-size = <0xd4>; | |
| clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk\0rot_clk"; | |
| qcom,sde-ubwc-swizzle = <0x06>; | |
| #list-cells = <0x01>; | |
| phandle = <0x36e>; | |
| qcom,sde-sspp-off = <0x5000 0x25000>; | |
| #cooling-cells = <0x02>; | |
| qcom,sde-sspp-qseed-off = <0xa00>; | |
| qcom,sde-num-ddr-channels = <0x02>; | |
| qcom,sde-ctl-off = <0x16000>; | |
| qcom,sde-max-per-pipe-bw-kbps = <0x3e8fa0 0x3e8fa0 0x3567e0 0x3567e0>; | |
| qcom,sde-mixer-blendstages = <0x05>; | |
| qcom,sde-ubwc-version = <0x200>; | |
| qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; | |
| qcom,sde-macrotile-mode = <0x00>; | |
| qcom,sde-mixer-linewidth = <0xa00>; | |
| qcom,sde-min-core-ib-kbps = <0x2625a0>; | |
| qcom,sde-creq-lut = <0x1223344 0x45566777 0x112236 0x67777777 0x1223344 0x45566777 0x112236 0x67777777 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x123445 0x56677777 0x123667 0x77777777 0x123445 0x56677777 0x123667 0x77777777 0x2344455 0x56667777 0x2366677 0x77777777 0x2344455 0x56667777 0x2366677 0x77777777 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x2344455 0x56667777 0x2366677 0x77777777 0x123445 0x56677777 0x123667 0x77777777>; | |
| qcom,sde-sspp-clk-ctrl = <0x2ac 0x00 0x2ac 0x08>; | |
| qcom,sde-dsc-enc-size = <0x100>; | |
| qcom,sde-pipe-order-version = <0x01>; | |
| qcom,sde-reg-dma-clk-ctrl = <0x2bc 0x14>; | |
| clock-max-rate = <0x00 0x00 0x243d5800 0x243d5800 0x124f800 0x243d5800 0x11e1a300>; | |
| qcom,sde-reg-dma-xin-id = <0x07>; | |
| qcom,sde-panic-per-pipe; | |
| qcom,sde-qos-cpu-irq-latency = <0x12c>; | |
| qcom,sde-ubwc-static = <0x01>; | |
| qcom,mdss_dsi_ft8726_fhd_plus_90_video { | |
| qcom,qsync-enable; | |
| qcom,platform-bklight-en-gpio = <0x42b 0x06 0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-panel-name = "ft8726 lcd video mode dsi focaltech panel with DSC"; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x5a 0x3c 0x30>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,platform-reset-gpio = <0x126 0x5c 0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x469>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,panel-supply-entries = <0x44b>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 04 ff 87 20 01 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 03 ff 87 20 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 05 2a 00 00 04 37 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 05 2b 00 00 09 67 15 01 00 00 00 00 02 00 a3 39 01 00 00 00 00 05 b3 09 68 00 18 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 07 c0 00 64 00 31 00 11 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 07 c0 00 64 00 31 00 11 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 07 c0 00 5a 00 31 00 11 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 06 c0 00 d4 00 31 11 15 01 00 00 00 00 02 00 60 39 01 00 00 00 00 07 c0 00 b4 00 31 00 11 15 01 00 00 00 00 02 00 70 39 01 00 00 00 00 0d c0 00 c8 00 c8 0d 03 14 00 00 15 01 11 15 01 00 00 00 00 02 00 a3 39 01 00 00 00 00 07 c1 00 48 00 27 00 02 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 11 ce 01 81 ff ff 00 78 00 98 00 00 00 00 01 90 01 90 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 10 ce 00 bd 12 75 00 bd 80 ff ff 00 06 40 14 0e 00 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 04 ce 00 00 00 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 04 ce 22 00 00 15 01 00 00 00 00 02 00 d1 39 01 00 00 00 00 08 ce 00 00 01 00 00 00 00 15 01 00 00 00 00 02 00 e1 39 01 00 00 00 00 0c ce 04 03 14 03 14 00 00 00 00 00 00 15 01 00 00 00 00 02 00 f1 39 01 00 00 00 00 0a ce 1f 2a 00 01 53 01 0d 00 00 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 05 cf 00 00 58 5c 15 01 00 00 00 00 02 00 b5 39 01 00 00 00 00 05 cf 04 04 de e2 15 01 00 00 00 00 02 00 c0 39 01 00 00 00 00 05 cf 09 09 63 67 15 01 00 00 00 00 02 00 c5 39 01 00 00 00 00 05 cf 09 09 69 6d 15 01 00 00 00 00 02 00 d1 39 01 00 00 00 00 0d c1 0a a6 0e c8 19 67 07 e3 0b 11 13 04 15 01 00 00 00 00 02 00 e1 39 01 00 00 00 00 03 c1 0e c8 15 01 00 00 00 00 02 00 e4 39 01 00 00 00 00 0d cf 09 fd 09 fc 09 fc 09 fc 09 fc 09 fc 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 03 c1 44 44 15 01 00 00 00 00 02 00 90 15 01 00 00 00 00 02 c1 03 15 01 00 00 00 00 02 00 f5 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 00 f6 15 01 00 00 00 00 02 cf 5a 15 01 00 00 00 00 02 00 f1 15 01 00 00 00 00 02 cf 5a 15 01 00 00 00 00 02 00 f0 15 01 00 00 00 00 02 c1 00 15 01 00 00 00 00 02 00 cc 15 01 00 00 00 00 02 c1 18 15 01 00 00 00 00 02 00 91 15 01 00 00 00 00 02 c4 88 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 c5 88 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 09 c2 82 01 1f 1f 00 00 00 00 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 05 c2 00 00 00 00 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 10 c2 00 00 00 17 8d 01 00 00 17 8d 02 00 00 17 8d 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 0b c2 03 00 00 17 8d 80 08 03 02 02 15 01 00 00 00 00 02 00 ca 39 01 00 00 00 00 06 c2 84 08 03 01 81 15 01 00 00 00 00 02 00 e0 39 01 00 00 00 00 06 c2 33 33 70 00 70 15 01 00 00 00 00 02 00 e8 39 01 00 00 00 00 09 c2 00 00 00 00 00 00 00 00 15 01 00 00 00 00 02 00 d0 39 01 00 00 00 00 11 c3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 11 cb 00 01 00 03 fd 01 01 00 00 00 fd 01 00 03 00 00 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 11 cb 00 00 00 0f f0 00 00 00 00 00 ff 00 00 00 00 00 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 05 cb 00 00 00 00 15 01 00 00 00 00 02 00 a4 39 01 00 00 00 00 05 cb 03 00 0c 00 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 05 cb 13 58 05 30 15 01 00 00 00 00 02 00 c0 39 01 00 00 00 00 05 cb 13 58 05 30 15 01 00 00 00 00 02 00 d5 39 01 00 00 00 00 0c cb 00 00 00 00 00 00 00 00 00 00 00 15 01 00 00 00 00 02 00 e0 39 01 00 00 00 00 0e cb 00 00 00 00 00 00 00 00 00 00 00 00 00 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 11 cc 23 12 23 1c 23 0a 23 23 09 08 07 06 23 23 23 23 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 09 cc 23 18 16 17 23 19 1a 1b 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 11 cc 23 12 23 1d 23 0e 23 23 06 07 08 09 23 23 23 23 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 09 cc 23 18 16 17 23 19 1a 1b 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 11 cd 23 23 23 02 23 0a 23 23 09 08 07 06 23 23 23 23 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 09 cd 23 18 16 17 23 19 1a 1b 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 11 cd 23 23 23 02 23 0e 23 23 06 07 08 09 23 23 23 23 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 09 cd 23 18 16 17 23 19 1a 1b 15 01 00 00 00 00 02 00 86 39 01 00 00 00 00 07 c0 00 00 00 01 15 05 15 01 00 00 00 00 02 00 96 39 01 00 00 00 00 07 c0 00 00 00 01 15 05 15 01 00 00 00 00 02 00 a6 39 01 00 00 00 00 07 c0 00 00 00 01 15 03 15 01 00 00 00 00 02 00 a3 39 01 00 00 00 00 07 ce 00 00 00 01 15 05 15 01 00 00 00 00 02 00 b3 39 01 00 00 00 00 07 ce 00 00 00 01 15 05 15 01 00 00 00 00 02 00 69 39 01 00 00 00 00 04 c0 01 14 01 15 01 00 00 00 00 02 00 82 39 01 00 00 00 00 03 a7 10 00 15 01 00 00 00 00 02 00 8d 15 01 00 00 00 00 02 a7 01 15 01 00 00 00 00 02 00 8f 15 01 00 00 00 00 02 a7 01 15 01 00 00 00 00 02 00 93 15 01 00 00 00 00 02 c5 37 15 01 00 00 00 00 02 00 97 15 01 00 00 00 00 02 c5 37 15 01 00 00 00 00 02 00 9a 15 01 00 00 00 00 02 c5 32 15 01 00 00 00 00 02 00 9c 15 01 00 00 00 00 02 c5 32 15 01 00 00 00 00 02 00 b6 39 01 00 00 00 00 09 c5 10 10 0e 0e 10 10 0e 0e 15 01 00 00 00 00 02 00 88 15 01 00 00 00 00 02 c4 08 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 a7 03 15 01 00 00 00 00 02 00 b0 15 01 00 00 00 00 02 c5 d1 15 01 00 00 00 00 02 00 b3 15 01 00 00 00 00 02 c5 d1 15 01 00 00 00 00 02 00 99 15 01 00 00 00 00 02 cf 50 15 01 00 00 00 00 02 00 8c 15 01 00 00 00 00 02 c3 00 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 03 c3 35 21 15 01 00 00 00 00 02 00 a4 39 01 00 00 00 00 03 c3 01 20 15 01 00 00 00 00 02 00 aa 15 01 00 00 00 00 02 c3 21 15 01 00 00 00 00 02 00 ad 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 00 ae 15 01 00 00 00 00 02 c3 20 15 01 00 00 00 00 02 00 b3 15 01 00 00 00 00 02 c3 21 15 01 00 00 00 00 02 00 b6 39 01 00 00 00 00 03 c3 01 20 15 01 00 00 00 00 02 00 c3 15 01 00 00 00 00 02 c5 ff 15 01 00 00 00 00 02 00 a9 15 01 00 00 00 00 02 f5 8e 15 01 00 00 00 00 02 00 b0 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 00 83 15 01 00 00 00 00 02 b0 63 15 01 00 00 00 00 02 00 93 15 01 00 00 00 00 02 c4 08 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 b3 22 15 01 00 00 00 00 02 00 90 15 01 00 00 00 00 02 c3 08 15 01 00 00 00 00 02 00 fa 15 01 00 00 00 00 02 c2 14 15 01 00 00 00 00 02 00 ca 15 01 00 00 00 00 02 c0 80 15 01 00 00 00 00 02 00 82 15 01 00 00 00 00 02 f5 01 15 01 00 00 00 00 02 00 93 15 01 00 00 00 00 02 f5 01 15 01 00 00 00 00 02 00 9b 15 01 00 00 00 00 02 f5 49 15 01 00 00 00 00 02 00 9d 15 01 00 00 00 00 02 f5 49 15 01 00 00 00 00 02 00 be 39 01 00 00 00 00 03 c5 f0 f0 15 01 00 00 00 00 02 00 85 15 01 00 00 00 00 02 a7 01 15 01 00 00 00 00 02 00 dc 15 01 00 00 00 00 02 c3 37 15 01 00 00 00 00 02 00 8a 15 01 00 00 00 00 02 f5 c7 15 01 00 00 00 00 02 00 99 15 01 00 00 00 00 02 cf 50 15 01 00 00 00 00 02 00 9c 15 01 00 00 00 00 02 f5 00 15 01 00 00 00 00 02 00 9e 15 01 00 00 00 00 02 f5 00 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 07 c5 d0 4a 39 d0 4a 0f 15 01 00 00 00 00 02 00 c2 15 01 00 00 00 00 02 f5 42 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 29 e1 00 05 0a 12 1a 1d 25 2c 37 b4 3f 46 4c 52 a8 56 5f 66 6d c9 73 7a 81 89 ed 91 96 9b a2 ec a8 b0 b9 bf 9d c5 cb d0 d3 38 15 01 00 00 00 00 02 00 30 39 01 00 00 00 00 29 e1 00 05 0a 12 1a 1d 25 2c 37 b4 3f 46 4c 52 a8 56 5f 66 6d c9 73 7a 81 89 ed 91 96 9b a2 ec a8 b0 b9 bf 9d c5 cb d0 d3 38 15 01 00 00 00 00 02 00 60 39 01 00 00 00 00 29 e1 00 05 0a 13 2c 1e 26 2d 37 13 40 47 4d 53 68 57 60 67 6f ec 75 7c 84 8c a0 95 9b a1 a7 83 af b9 c5 cd e9 d5 e1 e9 ed fa 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 29 e1 00 05 0a 13 2c 1e 26 2d 37 13 40 47 4d 53 68 57 60 67 6f ec 75 7c 84 8c a0 95 9b a1 a7 83 af b9 c5 cd e9 d5 e1 e9 ed fa 15 01 00 00 00 00 02 00 c0 39 01 00 00 00 00 29 e1 00 05 0a 12 1b 1d 26 2c 37 cf 40 47 4d 53 6d 58 60 68 6f 36 76 7d 85 8d 10 96 9c a2 a9 86 b1 bc c9 d2 d9 dd ec f7 ff fc 15 01 00 00 00 00 02 00 f0 39 01 00 00 00 00 11 e1 00 05 0a 12 1b 1d 26 2c 37 cf 40 47 4d 53 6d 58 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 19 e2 60 68 6f 36 76 7d 85 8d 10 96 9c a2 a9 86 b1 bc c9 d2 d9 dd ec f7 ff fc 15 01 00 00 00 00 02 00 d4 15 01 00 00 00 00 02 cb 03 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 0f b4 00 08 02 00 00 bb 00 07 0d b7 0c b7 10 f0 15 01 00 00 00 00 02 00 e8 15 01 00 00 00 00 02 c0 40 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 04 ff ff ff ff 15 01 00 00 00 00 02 51 f0 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 c8 00 01 11 05 01 00 00 96 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x32000110>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x28>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x24>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 1f 06 05 06 02 04 00 13 0a]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x2e>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-panel-height = <0x968>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ft8726_fhd_plus_60_video { | |
| qcom,qsync-enable; | |
| qcom,platform-bklight-en-gpio = <0x42b 0x06 0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-panel-name = "ft8726 lcd video mode dsi focaltech panel with DSC"; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,platform-reset-gpio = <0x126 0x5c 0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x46a>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,panel-supply-entries = <0x44b>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x200 0x390100 0x04 0xff872001 0x15010000 0x200 0x80390100 0x03 0xff872015 0x1000000 0x20000 0x39010000 0x52a 0x437 0x15010000 0x200 0x390100 0x05 0x2b000009 0x67150100 0x02 0xa33901 0x00 0x5b30968 0x181501 0x00 0x2008039 0x1000000 0x7c000 0x93003100 0x11150100 0x02 0x903901 0x00 0x7c00093 0x310011 0x15010000 0x200 0xa0390100 0x07 0xc0005a00 0x31001115 0x1000000 0x200b0 0x39010000 0x6c0 0xd40031 0x11150100 0x02 0x603901 0x00 0x7c000b4 0x310011 0x15010000 0x200 0x70390100 0x0d 0xc000c800 0xc80d0314 0x1501 0x11150100 0x02 0xa33901 0x00 0x7c10048 0x270002 0x15010000 0x200 0x80390100 0x11 0xce0181ff 0xff007800 0x60000000 0x19001 0x90150100 0x02 0x903901 0x00 0x10ce00bd 0x127500bd 0x80ffff00 0x640030e 0x150100 0x02 0xa03901 0x00 0x4ce0000 0x150100 0x02 0xb03901 0x00 0x4ce2200 0x150100 0x02 0xd13901 0x00 0x8ce0000 0x1000000 0x150100 0x02 0xe13901 0x00 0xcce0403 0x14031400 0x00 0x150100 0x02 0xf13901 0x00 0xace152a 0x10d01 0xd000015 0x1000000 0x200b0 0x39010000 0x5cf 0x6266 0x15010000 0x200 0xb5390100 0x05 0xcf0404e3 0xe7150100 0x02 0xc03901 0x00 0x5cf0909 0x63671501 0x00 0x200c539 0x1000000 0x5cf09 0x9696d15 0x1000000 0x200d1 0x39010000 0xdc1 0xaa60ec8 0x196707e3 0xb111304 0x15010000 0x200 0xe1390100 0x03 0xc10ec815 0x1000000 0x200e4 0x39010000 0xdcf 0x9fd09fc 0x9fc09fc 0x9fc09fc 0x15010000 0x200 0x80390100 0x03 0xc1444415 0x1000000 0x20090 0x15010000 0x2c1 0x3150100 0x02 0xf51501 0x00 0x2cf0215 0x1000000 0x200f6 0x15010000 0x2cf 0x3c150100 0x02 0xf11501 0x00 0x2cf3c15 0x1000000 0x200f0 0x15010000 0x2c1 0x150100 0x02 0xcc1501 0x00 0x2c11815 0x1000000 0x20091 0x15010000 0x2c4 0x88150100 0x02 0x801501 0x00 0x2c58815 0x1000000 0x20080 0x39010000 0x9c2 0x82011f1f 0x00 0x15010000 0x200 0x90390100 0x05 0xc2000000 0x150100 0x02 0xa03901 0x00 0x10c20000 0x308b01 0x308b 0x2000030 0x8b150100 0x02 0xb03901 0x00 0xbc20300 0x308b80 0x8030202 0x15010000 0x200 0xca390100 0x06 0xc2840803 0x1811501 0x00 0x200e039 0x1000000 0x6c233 0x33700070 0x15010000 0x200 0xe8390100 0x09 0xc2000000 0x00 0x150100 0x02 0xd03901 0x00 0x11c30000 0x00 0x00 0x00 0x1501 0x00 0x2008039 0x1000000 0x11cb00 0x10003fd 0x1010000 0xfd0100 0x3000015 0x1000000 0x20090 0x39010000 0x11cb 0x0f 0xf0000000 0xff00 0x00 0x15010000 0x200 0xa0390100 0x05 0xcb000000 0x150100 0x02 0xa43901 0x00 0x5cb0300 0xc001501 0x00 0x200b039 0x1000000 0x5cb13 0x58053015 0x1000000 0x200c0 0x39010000 0x5cb 0x13580530 0x15010000 0x200 0xd5390100 0x0c 0xcb000000 0x00 0x00 0x15010000 0x200 0xe0390100 0x0e 0xcb000000 0x00 0x00 0x1501 0x00 0x2008039 0x1000000 0x11cc23 0x12231c23 0xa232309 0x8070623 0x23232315 0x1000000 0x20090 0x39010000 0x9cc 0x23181617 0x23191a1b 0x15010000 0x200 0xa0390100 0x11 0xcc231223 0x1d230e23 0x23060708 0x9232323 0x23150100 0x02 0xb03901 0x00 0x9cc2318 0x16172319 0x1a1b1501 0x00 0x2008039 0x1000000 0x11cd23 0x23230223 0xa232309 0x8070623 0x23232315 0x1000000 0x20090 0x39010000 0x9cd 0x23181617 0x23191a1b 0x15010000 0x200 0xa0390100 0x11 0xcd232323 0x2230e23 0x23060708 0x9232323 0x23150100 0x02 0xb03901 0x00 0x9cd2318 0x16172319 0x1a1b1501 0x00 0x2008639 0x1000000 0x7c000 0x126 0x7150100 0x02 0x963901 0x00 0x7c00000 0x12607 0x15010000 0x200 0xa6390100 0x07 0xc0000000 0x1260715 0x1000000 0x200a3 0x39010000 0x7ce 0x01 0x26071501 0x00 0x200b339 0x1000000 0x7ce00 0x126 0x7150100 0x02 0x693901 0x00 0x4c00114 0x1150100 0x02 0x823901 0x00 0x3a71000 0x15010000 0x200 0x8d150100 0x02 0xa7011501 0x00 0x2008f15 0x1000000 0x2a701 0x15010000 0x200 0x93150100 0x02 0xc5371501 0x00 0x2009715 0x1000000 0x2c537 0x15010000 0x200 0x9a150100 0x02 0xc5321501 0x00 0x2009c15 0x1000000 0x2c532 0x15010000 0x200 0xb6390100 0x09 0xc510100e 0xe10100e 0xe150100 0x02 0x881501 0x00 0x2c40815 0x1000000 0x20080 0x15010000 0x2a7 0x3150100 0x02 0xb01501 0x00 0x2c5d115 0x1000000 0x200b3 0x15010000 0x2c5 0xd1150100 0x02 0x991501 0x00 0x2cf5015 0x1000000 0x2008c 0x15010000 0x2c3 0x150100 0x02 0xa03901 0x00 0x3c33521 0x15010000 0x200 0xa4390100 0x03 0xc3012015 0x1000000 0x200aa 0x15010000 0x2c3 0x21150100 0x02 0xad1501 0x00 0x2c30115 0x1000000 0x200ae 0x15010000 0x2c3 0x20150100 0x02 0xb31501 0x00 0x2c32115 0x1000000 0x200b6 0x39010000 0x3c3 0x1201501 0x00 0x200c315 0x1000000 0x2c5ff 0x15010000 0x200 0xa9150100 0x02 0xf58e1501 0x00 0x200b015 0x1000000 0x2b300 0x15010000 0x200 0x83150100 0x02 0xb0631501 0x00 0x2009315 0x1000000 0x2c408 0x15010000 0x200 0x80150100 0x02 0xb3221501 0x00 0x2009015 0x1000000 0x2c308 0x15010000 0x200 0xfa150100 0x02 0xc2141501 0x00 0x200ca15 0x1000000 0x2c080 0x15010000 0x200 0x82150100 0x02 0xf5011501 0x00 0x2009315 0x1000000 0x2f501 0x15010000 0x200 0x9b150100 0x02 0xf5491501 0x00 0x2009d15 0x1000000 0x2f549 0x15010000 0x200 0xbe390100 0x03 0xc5f0f015 0x1000000 0x20085 0x15010000 0x2a7 0x1150100 0x02 0xdc1501 0x00 0x2c33715 0x1000000 0x2008a 0x15010000 0x2f5 0xc7150100 0x02 0x991501 0x00 0x2cf5015 0x1000000 0x2009c 0x15010000 0x2f5 0x150100 0x02 0x9e1501 0x00 0x2f50015 0x1000000 0x200b0 0x39010000 0x7c5 0xd04a39d0 0x4a0f1501 0x00 0x200c215 0x1000000 0x2f542 0x15010000 0x200 0x390100 0x29 0xe100050a 0x121a1d25 0x2c37b43f 0x464c52a8 0x565f666d 0xc9737a81 0x89ed9196 0x9ba2eca8 0xb0b9bf9d 0xc5cbd0d3 0x38150100 0x02 0x303901 0x00 0x29e10005 0xa121a1d 0x252c37b4 0x3f464c52 0xa8565f66 0x6dc9737a 0x8189ed91 0x969ba2ec 0xa8b0b9bf 0x9dc5cbd0 0xd3381501 0x00 0x2006039 0x1000000 0x29e100 0x50a132c 0x1e262d37 0x1340474d 0x53685760 0x676fec75 0x7c848ca0 0x959ba1a7 0x83afb9c5 0xcde9d5e1 0xe9edfa15 0x1000000 0x20090 0x39010000 0x29e1 0x50a13 0x2c1e262d 0x37134047 0x4d536857 0x60676fec 0x757c848c 0xa0959ba1 0xa783afb9 0xc5cde9d5 0xe1e9edfa 0x15010000 0x200 0xc0390100 0x29 0xe100050a 0x121b1d26 0x2c37cf40 0x474d536d 0x5860686f 0x36767d85 0x8d10969c 0xa2a986b1 0xbcc9d2d9 0xddecf7ff 0xfc150100 0x02 0xf03901 0x00 0x11e10005 0xa121b1d 0x262c37cf 0x40474d53 0x6d581501 0x00 0x2000039 0x1000000 0x19e260 0x686f3676 0x7d858d10 0x969ca2a9 0x86b1bcc9 0xd2d9ddec 0xf7fffc15 0x1000000 0x200d4 0x15010000 0x2cb 0x3150100 0x02 0xb03901 0x00 0xfb40008 0x20000bb 0x70db7 0xcb710f0 0x15010000 0x200 0xe8150100 0x02 0xc0401501 0x00 0x2008239 0x1000000 0x3ce17 0x17150100 0x02 0x3901 0x00 0x4ffffff 0xff150100 0x02 0x51f01501 0x00 0x2532c15 0x1000000 0x25500 0x5010000 0xc8000111 0x5010000 0x96000129>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x32000110>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x28>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x24>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04 04 03 02 04 00 0e 09]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x2e>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-panel-height = <0x968>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_vtdr6130_fhd_plus_vid { | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "vtdr6130 amoled video mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x45d>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 01 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_video { | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled video mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x462>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 13 d8 00 00 00 00 00 00 00 00 00 5b 00 5b 00 5b 00 5b 00 5b 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 04 04 04 04 04 05 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 04 03 02 04 00 0e 09]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x45e>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@2 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x02>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 00 00 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x01>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 06 06 02 04 00 14 0b]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 04 03 02 04 00 0e 09]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_dsc_10b_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC3:1 10bit dsi panel"; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x1e>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x45a>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x44a>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@5 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x01>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 06 06 02 04 00 13 0b]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 03 02 02 04 00 0c 08]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-t-clk-pre = <0x27>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-t-clk-post = <0x03>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x458>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x44a>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@2 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 08 08 02 04 00 19 0d]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x2e4>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x21c 0x28 0x21c 0x28>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| }; | |
| timing@7 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| cell-index = <0x03>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 3b 0f 0f 18 15 0f 0f 0d 02 04 00 2d 12]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x2e4>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| }; | |
| timing@3 { | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| cell-index = <0x01>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x348>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 17 05 05 14 1f 06 06 06 02 04 00 14 0b]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x564>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,panel-roi-alignment = <0x168 0x14 0x168 0x14 0x168 0x14>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| }; | |
| timing@4 { | |
| qcom,src-chroma-format = <0x01>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| cell-index = <0x02>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 2b 0b 0b 1c 27 0b 0c 0b 02 04 00 23 10]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x2e4>; | |
| qcom,mdss-dsc-version = <0x12>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_dsc_375_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC 3.75:1 dsi panel"; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x45b>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x44a>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0xf0000100>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 03 02 02 04 00 0b 08]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_vtdr6130_fhd_plus_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x45c>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@2 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e 01 0c c3 09 06 00 60 00 53 00 3a 00 0c 00 0c 07 00 54 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x02>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e 01 0c c3 09 06 00 60 00 53 00 3a 00 0c 00 0c 07 00 54]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-clockrate = <0x32838600>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a 81 09 92 06 c5 00 48 00 3e 00 2b 00 0c 00 0c 05 00 3f 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x01>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a 81 09 92 06 c5 00 48 00 3e 00 2b 00 0c 00 0c 05 00 3f]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-clockrate = <0x32838600>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,cmd-on-commands = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,video-mode-switch-out-commands = [39 01 00 00 00 00 02 6f 03 39 01 00 00 00 00 02 6f 02]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,vid-on-commands = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 01 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35]; | |
| qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,cmd-mode-switch-out-commands = [39 01 00 00 00 00 02 6f 07]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-video-mode; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,video-mode-switch-in-commands = [39 01 00 00 00 00 02 6f 01]; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-cmd-mode; | |
| qcom,mdss-dsi-panel-clockrate = <0x32838600>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| timing@3 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 02 13 25 0d 8a 00 90 00 7d 00 57 00 0c 00 0c 0b 00 7e 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x03>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 02 13 25 0d 8a 00 90 00 7d 00 57 00 0c 00 0c 0b 00 7e]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-clockrate = <0x32838600>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_cphy_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-rx-eot-ignore; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,panel-cphy-mode; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x461>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 02 f7 00 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 13 d8 00 00 00 00 00 00 00 00 00 5b 00 5b 00 5b 00 5b 00 5b 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 06 b6 6c 00 06 23 af 39 01 00 00 00 00 02 b4 20 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 04 04 04 04 04 05 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3bc4>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 10 13 03 19 02 02 04 00 00 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-dspp-blocks { | |
| qcom,sde-dspp-vlut = <0xa00 0x10008>; | |
| qcom,sde-dspp-hist = <0x800 0x10007>; | |
| qcom,sde-dspp-dither = <0x82c 0x10007>; | |
| qcom,sde-dspp-gc = <0x17c0 0x10008>; | |
| qcom,sde-dspp-sixzone = <0x900 0x10007>; | |
| qcom,sde-dspp-memcolor = <0x880 0x10007>; | |
| qcom,sde-dspp-hsic = <0x800 0x10007>; | |
| qcom,sde-dspp-pcc = <0x1700 0x40000>; | |
| qcom,sde-dspp-igc = <0x1260 0x40000>; | |
| }; | |
| qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,dsi-dyn-clk-enable; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x466>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@2 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 02 13 25 0d 8a 00 90 00 7d 00 57 00 0c 00 0c 0b 00 7e 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,dsi-dyn-clk-list = <0x2a184500 0x29eb5e50 0x29be77a0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x02>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 02 13 25 0d 8a 00 90 00 7d 00 57 00 0c 00 0c 0b 00 7e]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-clockrate = <0x2a184500>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x28 0x28 0x438 0x28>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e 01 0c c3 09 06 00 60 00 53 00 3a 00 0c 00 0c 07 00 54 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,dsi-dyn-clk-list = <0x2a184500 0x29eb5e50 0x29be77a0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x01>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 02 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e 01 0c c3 09 06 00 60 00 53 00 3a 00 0c 00 0c 07 00 54]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-panel-clockrate = <0x2a184500>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x28 0x28 0x438 0x28>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,cmd-on-commands = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 02 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a 81 09 92 06 c5 00 48 00 3e 00 2b 00 0c 00 0c 05 00 3f 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,dsi-dyn-clk-list = <0x2a184500 0x29eb5e50 0x29be77a0>; | |
| qcom,video-mode-switch-out-commands = [39 01 00 00 00 00 02 6f 03 39 01 00 00 00 00 02 6f 02]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,vid-on-commands = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 01 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 01 fc 00 01 66 00 14 0d 6c 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a 81 09 92 06 c5 00 48 00 3e 00 2b 00 0c 00 0c 05 00 3f]; | |
| qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; | |
| qcom,cmd-mode-switch-out-commands = [39 01 00 00 00 00 02 6f 07]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-video-mode; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,video-mode-switch-in-commands = [39 01 00 00 00 00 02 6f 01]; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-cmd-mode; | |
| qcom,mdss-dsi-panel-clockrate = <0x2a184500>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x28 0x28 0x438 0x28>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_g1392_fhd_plus_60_video { | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-panel-name = "g1392 lcd video mode dsi"; | |
| qcom,mdss-color-order = <0xff>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-brightness-max-level = <0xff>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,platform-reset-gpio = <0x126 0x5c 0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x454>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,panel-supply-entries = <0x44c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x14>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 f0 50 15 01 00 00 00 00 02 b9 00 05 01 00 00 78 00 01 11 05 01 00 00 96 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x32000110>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x0c>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 13 1e 05 05 06 02 04 00 11 0a]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-panel-clockrate = <0x1e25dd70>; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-panel-height = <0x4d8>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_video { | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
| qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,platform-reset-gpio = <0x126 0x5c 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-t-clk-post = <0x04>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x459>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x44a>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x280>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>; | |
| qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x08>; | |
| qcom,mdss-dsi-h-back-porch = <0x08>; | |
| qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 01 02 02 04 00 08 06]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-back-porch = <0x06>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x1e0>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid { | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "vtdr6130 amoled video mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x467>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 03 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 03 51 00 00 39 01 00 00 00 00 02 59 00 39 01 00 00 00 00 02 6c 01 39 01 00 00 00 00 02 6d 00 39 01 00 00 00 00 02 6f 01 39 01 00 00 00 00 5f 70 12 00 00 ab 30 80 09 60 04 38 00 28 02 1c 02 1c 02 00 02 0e 00 20 03 dd 00 07 00 0c 02 77 02 8b 18 00 10 f0 07 10 20 00 06 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 02 02 22 00 2a 40 2a be 3a fc 3a fa 3a f8 3b 38 3b 78 3b b6 4b b6 4b f4 4b f4 6c 34 84 74 00 00 00 00 00 00 39 01 00 00 00 00 03 f0 aa 10 39 01 00 00 00 00 02 65 16 39 01 00 00 00 00 03 eb 00 00 39 01 00 00 00 00 16 b1 01 38 00 14 00 1c 00 01 66 00 14 00 14 00 01 66 00 14 05 cc 00 39 01 00 00 00 00 03 f0 aa 13 39 01 00 00 00 00 18 ce 09 11 09 11 08 c1 07 fa 05 a4 00 3c 00 34 00 24 00 0c 00 0c 04 00 35 39 01 00 00 00 00 03 f0 aa 14 39 01 00 00 00 00 03 b2 03 33 39 01 00 00 00 00 0d b4 00 33 00 00 00 3e 00 00 00 3e 00 00 39 01 00 00 00 00 0a b5 00 09 09 09 09 09 09 06 01 39 01 00 00 00 00 07 b9 00 00 08 09 09 09 39 01 00 00 00 00 0d bc 10 00 00 06 11 09 3b 09 47 09 47 00 39 01 00 00 00 00 0d be 10 10 00 08 22 09 19 09 25 09 25 00 39 01 00 00 00 00 03 ff 5a 80 39 01 00 00 00 00 02 65 14 39 01 00 00 00 00 04 fa 08 08 08 39 01 00 00 00 00 03 ff 5a 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 f3 0f 39 01 00 00 00 00 03 f0 aa 00 39 01 00 00 00 00 03 ff 5a 82 39 01 00 00 00 00 02 f9 00 39 01 00 00 00 00 03 ff 51 83 39 01 00 00 00 00 02 65 04 39 01 00 00 00 00 02 f8 00 39 01 00 00 00 00 03 ff 5a 00 39 01 00 00 00 00 02 65 01 39 01 00 00 00 00 02 f4 9a 39 01 00 00 00 00 03 ff 5a 00 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x14>; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 06 07 02 04 00 16 0b]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x960>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x464>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x0a 0x01 0x14>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 13 d8 00 00 00 00 00 00 00 00 00 5b 00 5b 00 5b 00 5b 00 5b 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 04 04 04 04 04 05 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 04 03 02 04 00 0e 09]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_cphy_120hz_vid { | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled video mode dsi visionox panel with DSC"; | |
| qcom,panel-cphy-mode; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x465>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 86 cf 64 0b 00 22 00 cd 03 33 04 00 0b 77 01 01 01 02 02 03 03 04 04 04 04 05 00 00 00 3b 00 3b 01 64 01 64 01 64 01 64 01 64 01 64 03 ff 03 ff 03 ff 00 00 00 3b 00 3b 01 64 01 64 01 64 01 64 01 64 01 64 03 ff 03 ff 03 ff 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 19 19 19 19 19 19 19 19 19 19 19 19 00 00 00 43 00 43 01 98 01 98 06 61 06 61 0f f6 0f f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 09 d1 05 00 21 02 24 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 f0 0f 00 40 00 00 00 00 00 00 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 14 1b 05 19 06 02 04 00 00 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_cphy_vid { | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled video mode dsi visionox panel with DSC"; | |
| qcom,panel-cphy-mode; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x463>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2b0 0x390100 0x02 0xb3013901 0x00 0x2b08039 0x1000000 0x2e600 0x39010000 0x2b0 0x390100 0x06 0xb66c0006 0x23a63901 0x00 0x2b42039 0x1000000 0x19cf64 0xb000000 0x08 0xb7701 0x1010101 0x1040404 0x4040539 0x1000000 0x2b004 0x39010000 0x2f7 0x1390100 0x03 0xdf504039 0x1000000 0x6f350 0x00 0x39010000 0x2f2 0x11390100 0x06 0xf3010000 0x13901 0x00 0x3f40002 0x39010000 0x2f2 0x19390100 0x03 0xdf504239 0x1000000 0x23500 0x39010000 0x52a 0x437 0x39010000 0x52b 0x923 0x5010000 0x78000111 0x5010000 0x129>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 12 17 04 19 03 02 04 00 00 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd { | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-rx-eot-ignore; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,panel-cphy-mode; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| phandle = <0x460>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@2 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x02>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 14 1b 05 19 06 02 04 00 00 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| }; | |
| timing@1 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x01>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 12 17 04 19 03 02 04 00 00 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 0c c2 09 24 0c 00 00 0c 00 00 00 09 3c 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 14 de 40 00 18 00 18 00 18 00 18 10 00 18 00 18 00 18 02 00 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 03 b4 20 1c 39 01 00 00 00 00 0d b6 6c 00 06 23 af 13 1a 05 04 fa 05 20 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 00 00 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c]; | |
| qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 10 13 03 19 02 02 04 00 00 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x20>; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-sspp-vig-blocks { | |
| vcm@0 { | |
| qcom,sde-vig-csc-off = <0x1a00>; | |
| qcom,sde-vig-qseed-size = <0xe0>; | |
| cell-index = <0x00>; | |
| qcom,sde-vig-qseed-off = <0xa00>; | |
| qcom,sde-vig-top-off = <0xa00>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_visionox_r66451_fhd_plus_video { | |
| qcom,spr-pack-type = "pentile"; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled video mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x45f>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 01 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 11 c4 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9c 39 01 00 00 00 00 1a d7 00 b9 34 00 40 04 00 a0 0a 00 40 00 00 00 00 00 00 19 34 00 40 04 00 a0 0a 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 32 00 0a 00 22 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 f1 00 00 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 39 04 09 34 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| cell-index = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ft8726_fhd_plus_120_video { | |
| qcom,platform-bklight-en-gpio = <0x42b 0x06 0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-panel-name = "ft8726 lcd video mode dsi focaltech panel with DSC"; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,platform-reset-gpio = <0x126 0x5c 0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| phandle = <0x468>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,panel-supply-entries = <0x44b>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 04 ff 87 20 01 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 03 ff 87 20 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 05 2a 00 00 04 37 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 05 2b 00 00 09 67 15 01 00 00 00 00 02 00 a3 39 01 00 00 00 00 05 b3 09 68 00 18 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 07 c0 00 4a 00 3b 00 11 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 07 c0 00 4a 00 3b 00 11 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 07 c0 00 5a 00 3b 00 11 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 06 c0 00 d3 00 3b 11 15 01 00 00 00 00 02 00 60 39 01 00 00 00 00 07 c0 00 b4 00 3b 00 11 15 01 00 00 00 00 02 00 70 39 01 00 00 00 00 0d c0 00 c8 00 c8 0d 03 14 00 00 15 01 11 15 01 00 00 00 00 02 00 a3 39 01 00 00 00 00 07 c1 00 55 00 27 00 02 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 11 ce 01 81 ff ff 00 c8 00 c8 00 00 00 00 01 90 01 90 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 10 ce 00 bd 12 75 00 bd 80 ff ff 00 06 40 0a 0e 00 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 04 ce 00 00 00 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 04 ce 22 00 00 15 01 00 00 00 00 02 00 d1 39 01 00 00 00 00 08 ce 00 00 01 00 00 00 00 15 01 00 00 00 00 02 00 e1 39 01 00 00 00 00 0c ce 04 03 14 03 14 00 00 00 00 00 00 15 01 00 00 00 00 02 00 f1 39 01 00 00 00 00 0a ce 2a 2a 00 01 20 01 0d 00 00 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 05 cf 00 00 9d a1 15 01 00 00 00 00 02 00 b5 39 01 00 00 00 00 05 cf 05 05 00 04 15 01 00 00 00 00 02 00 c0 39 01 00 00 00 00 05 cf 09 09 63 67 15 01 00 00 00 00 02 00 c5 39 01 00 00 00 00 05 cf 09 09 69 6d 15 01 00 00 00 00 02 00 d1 39 01 00 00 00 00 0d c1 0a a6 0e c8 19 67 07 e3 0b 11 13 04 15 01 00 00 00 00 02 00 e1 39 01 00 00 00 00 03 c1 0e c8 15 01 00 00 00 00 02 00 e4 39 01 00 00 00 00 0d cf 0a 07 0a 06 0a 06 0a 06 0a 06 0a 06 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 03 c1 44 44 15 01 00 00 00 00 02 00 90 15 01 00 00 00 00 02 c1 03 15 01 00 00 00 00 02 00 f5 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 00 f6 15 01 00 00 00 00 02 cf 78 15 01 00 00 00 00 02 00 f1 15 01 00 00 00 00 02 cf 78 15 01 00 00 00 00 02 00 f0 15 01 00 00 00 00 02 c1 00 15 01 00 00 00 00 02 00 cc 15 01 00 00 00 00 02 c1 18 15 01 00 00 00 00 02 00 91 15 01 00 00 00 00 02 c4 88 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 c5 88 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 09 c2 82 01 1f 1f 00 00 00 00 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 05 c2 00 00 00 00 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 10 c2 00 00 00 17 8d 01 00 00 17 8d 02 00 00 17 8d 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 0b c2 03 00 00 17 8d 80 08 03 02 02 15 01 00 00 00 00 02 00 ca 39 01 00 00 00 00 06 c2 84 08 03 01 81 15 01 00 00 00 00 02 00 e0 39 01 00 00 00 00 06 c2 33 33 70 00 70 15 01 00 00 00 00 02 00 e8 39 01 00 00 00 00 09 c2 00 00 00 00 00 00 00 00 15 01 00 00 00 00 02 00 d0 39 01 00 00 00 00 11 c3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 11 cb 00 01 00 03 fd 01 01 00 00 00 fd 01 00 03 00 00 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 11 cb 00 00 00 0f f0 00 00 00 00 00 ff 00 00 00 00 00 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 05 cb 00 00 00 00 15 01 00 00 00 00 02 00 a4 39 01 00 00 00 00 05 cb 03 00 0c 00 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 05 cb 13 58 05 30 15 01 00 00 00 00 02 00 c0 39 01 00 00 00 00 05 cb 13 58 05 30 15 01 00 00 00 00 02 00 d5 39 01 00 00 00 00 0c cb 00 00 00 00 00 00 00 00 00 00 00 15 01 00 00 00 00 02 00 e0 39 01 00 00 00 00 0e cb 00 00 00 00 00 00 00 00 00 00 00 00 00 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 11 cc 23 12 23 1c 23 0a 23 23 09 08 07 06 23 23 23 23 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 09 cc 23 18 16 17 23 19 1a 1b 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 11 cc 23 12 23 1d 23 0e 23 23 06 07 08 09 23 23 23 23 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 09 cc 23 18 16 17 23 19 1a 1b 15 01 00 00 00 00 02 00 80 39 01 00 00 00 00 11 cd 23 23 23 02 23 0a 23 23 09 08 07 06 23 23 23 23 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 09 cd 23 18 16 17 23 19 1a 1b 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 11 cd 23 23 23 02 23 0e 23 23 06 07 08 09 23 23 23 23 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 09 cd 23 18 16 17 23 19 1a 1b 15 01 00 00 00 00 02 00 86 39 01 00 00 00 00 07 c0 00 00 00 01 0f 05 15 01 00 00 00 00 02 00 96 39 01 00 00 00 00 07 c0 00 00 00 01 0f 05 15 01 00 00 00 00 02 00 a6 39 01 00 00 00 00 07 c0 00 00 00 01 0f 03 15 01 00 00 00 00 02 00 a3 39 01 00 00 00 00 07 ce 00 00 00 01 0f 05 15 01 00 00 00 00 02 00 b3 39 01 00 00 00 00 07 ce 00 00 00 01 0f 05 15 01 00 00 00 00 02 00 69 39 01 00 00 00 00 04 c0 01 14 01 15 01 00 00 00 00 02 00 82 39 01 00 00 00 00 03 a7 10 00 15 01 00 00 00 00 02 00 8d 15 01 00 00 00 00 02 a7 01 15 01 00 00 00 00 02 00 8f 15 01 00 00 00 00 02 a7 01 15 01 00 00 00 00 02 00 93 15 01 00 00 00 00 02 c5 37 15 01 00 00 00 00 02 00 97 15 01 00 00 00 00 02 c5 37 15 01 00 00 00 00 02 00 9a 15 01 00 00 00 00 02 c5 32 15 01 00 00 00 00 02 00 9c 15 01 00 00 00 00 02 c5 32 15 01 00 00 00 00 02 00 b6 39 01 00 00 00 00 09 c5 10 10 0e 0e 10 10 0e 0e 15 01 00 00 00 00 02 00 88 15 01 00 00 00 00 02 c4 08 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 a7 03 15 01 00 00 00 00 02 00 b0 15 01 00 00 00 00 02 c5 d1 15 01 00 00 00 00 02 00 b3 15 01 00 00 00 00 02 c5 d1 15 01 00 00 00 00 02 00 99 15 01 00 00 00 00 02 cf 50 15 01 00 00 00 00 02 00 8c 15 01 00 00 00 00 02 c3 00 15 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 03 c3 35 21 15 01 00 00 00 00 02 00 a4 39 01 00 00 00 00 03 c3 01 20 15 01 00 00 00 00 02 00 aa 15 01 00 00 00 00 02 c3 21 15 01 00 00 00 00 02 00 ad 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 00 ae 15 01 00 00 00 00 02 c3 20 15 01 00 00 00 00 02 00 b3 15 01 00 00 00 00 02 c3 21 15 01 00 00 00 00 02 00 b6 39 01 00 00 00 00 03 c3 01 20 15 01 00 00 00 00 02 00 c3 15 01 00 00 00 00 02 c5 ff 15 01 00 00 00 00 02 00 a9 15 01 00 00 00 00 02 f5 8e 15 01 00 00 00 00 02 00 b0 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 00 83 15 01 00 00 00 00 02 b0 63 15 01 00 00 00 00 02 00 93 15 01 00 00 00 00 02 c4 08 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 b3 22 15 01 00 00 00 00 02 00 90 15 01 00 00 00 00 02 c3 08 15 01 00 00 00 00 02 00 fa 15 01 00 00 00 00 02 c2 14 15 01 00 00 00 00 02 00 ca 15 01 00 00 00 00 02 c0 80 15 01 00 00 00 00 02 00 82 15 01 00 00 00 00 02 f5 01 15 01 00 00 00 00 02 00 93 15 01 00 00 00 00 02 f5 01 15 01 00 00 00 00 02 00 9b 15 01 00 00 00 00 02 f5 49 15 01 00 00 00 00 02 00 9d 15 01 00 00 00 00 02 f5 49 15 01 00 00 00 00 02 00 be 39 01 00 00 00 00 03 c5 f0 f0 15 01 00 00 00 00 02 00 85 15 01 00 00 00 00 02 a7 01 15 01 00 00 00 00 02 00 dc 15 01 00 00 00 00 02 c3 37 15 01 00 00 00 00 02 00 8a 15 01 00 00 00 00 02 f5 c7 15 01 00 00 00 00 02 00 99 15 01 00 00 00 00 02 cf 50 15 01 00 00 00 00 02 00 9c 15 01 00 00 00 00 02 f5 00 15 01 00 00 00 00 02 00 9e 15 01 00 00 00 00 02 f5 00 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 07 c5 d0 4a 39 d0 4a 0f 15 01 00 00 00 00 02 00 c2 15 01 00 00 00 00 02 f5 42 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 29 e1 00 05 0a 12 1a 1d 25 2c 37 b4 3f 46 4c 52 a8 56 5f 66 6d c9 73 7a 81 89 ed 91 96 9b a2 ec a8 b0 b9 bf 9d c5 cb d0 d3 38 15 01 00 00 00 00 02 00 30 39 01 00 00 00 00 29 e1 00 05 0a 12 1a 1d 25 2c 37 b4 3f 46 4c 52 a8 56 5f 66 6d c9 73 7a 81 89 ed 91 96 9b a2 ec a8 b0 b9 bf 9d c5 cb d0 d3 38 15 01 00 00 00 00 02 00 60 39 01 00 00 00 00 29 e1 00 05 0a 13 2c 1e 26 2d 37 13 40 47 4d 53 68 57 60 67 6f ec 75 7c 84 8c a0 95 9b a1 a7 83 af b9 c5 cd e9 d5 e1 e9 ed fa 15 01 00 00 00 00 02 00 90 39 01 00 00 00 00 29 e1 00 05 0a 13 2c 1e 26 2d 37 13 40 47 4d 53 68 57 60 67 6f ec 75 7c 84 8c a0 95 9b a1 a7 83 af b9 c5 cd e9 d5 e1 e9 ed fa 15 01 00 00 00 00 02 00 c0 39 01 00 00 00 00 29 e1 00 05 0a 12 1b 1d 26 2c 37 cf 40 47 4d 53 6d 58 60 68 6f 36 76 7d 85 8d 10 96 9c a2 a9 86 b1 bc c9 d2 d9 dd ec f7 ff fc 15 01 00 00 00 00 02 00 f0 39 01 00 00 00 00 11 e1 00 05 0a 12 1b 1d 26 2c 37 cf 40 47 4d 53 6d 58 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 19 e2 60 68 6f 36 76 7d 85 8d 10 96 9c a2 a9 86 b1 bc c9 d2 d9 dd ec f7 ff fc 15 01 00 00 00 00 02 00 d4 15 01 00 00 00 00 02 cb 03 15 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 0f b4 00 08 02 00 00 bb 00 07 0d b7 0c b7 10 f0 15 01 00 00 00 00 02 00 e8 15 01 00 00 00 00 02 c0 40 15 01 00 00 00 00 02 00 00 39 01 00 00 00 00 04 ff ff ff ff 15 01 00 00 00 00 02 51 f0 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 32 00 01 11 05 01 00 00 14 00 01 29]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x32000110>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-h-front-porch = <0x28>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x24>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x38>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-panel-height = <0x968>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dcc_v2@100ff000 { | |
| dcc-ram-offset = <0x00>; | |
| reg-names = "dcc-base\0dcc-ram-base"; | |
| reg = <0x100ff000 0x1000 0x10080000 0x18000>; | |
| compatible = "qcom,dcc-v2"; | |
| phandle = <0x293>; | |
| qcom,transaction_timeout = <0x00>; | |
| link_list_0 { | |
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| qcom,data-sink = "sram"; | |
| qcom,curr-link-list = <0x06>; | |
| }; | |
| link_list_1 { | |
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0x03 0x00 0x00 0x8a8c124 0x01 0x00 0x00 0x8a8c01c 0x01 0x00 0x00 0x8b00038 0x01 0x00 0x00 0x8b00040 0x01 0x00 0x00 0x8a8c138 0x01 0x00 0x00 0x8b00208 0x03 0x00 0x00 0x8b00228 0x03 0x00 0x00 0x8b00248 0x03 0x00 0x00 0x8b00268 0x03 0x00 0x00 0x8a8c124 0x01 0x00 0x00 0x8a8c01c 0x01 0x00 0x00 0x8b00038 0x01 0x00 0x00 0x8b00040 0x01 0x00 0x00 0x8a8c138 0x01 0x00 0x00 0x8aa3020 0x02 0x00 0x00 0x8aa3000 0x02 0x00 0x00 0x8aa2000 0x02 0x00 0x00 0x8a90500 0x20 0x00 0x00 0x12015c 0x02 0x00 0x00 0x120464 0x02 0x00 0x00 0x12c15c 0x02 0x00 0x00 0x12c464 0x02 0x00 0x00 0x188040 0x01 0x00 0x00 0x1a0884 0x01 0x00 0x00 0x120018 0x04 0x00 0x00 0x12002c 0x03 0x00 0x00 0x12015c 0x02 0x00 0x00 0x120464 0x02 0x00 0x00 0x121004 0x01 0x00 0x00 0x12100c 0x02 0x00 0x00 0x124004 0x01 0x00 0x00 0x12400c 0x02 0x00 0x00 0x125004 0x01 0x00 0x00 0x125010 0x01 0x00 0x00 0x127004 0x03 0x00 0x00 0x127140 0x01 0x00 0x00 0x127274 0x01 0x00 0x00 0x1273a8 0x01 0x00 0x00 0x1274dc 0x01 0x00 0x00 0x128004 0x03 0x00 0x00 0x128140 0x01 0x00 0x00 0x128274 0x01 0x00 0x00 0x1283a8 0x01 0x00 0x00 0x1284dc 0x01 0x00 0x00 0x12c15c 0x02 0x00 0x00 0x12c464 0x02 0x00 0x00 0x12a004 0x01 0x00 0x00 0x12b004 0x01 0x00 0x00 0x12b00c 0x01 0x00 0x00 0x12c018 0x01 0x00 0x00 0x12c020 0x01 0x00 0x00 0x12c028 0x01 0x00 0x00 0x12c030 0x05 0x00 0x00 0x12c174 0x01 0x00 0x00 0x12c2a8 0x01 0x00 0x00 0x12c2c8 0x07 0x00 0x00 0x12d004 0x02 0x00 0x00 0x12f004 0x03 0x00 0x00 0x12f014 0x12 0x00 0x00 0x12f77c 0x07 0x00 0x00 0x130004 0x02 0x00 0x00 0x131000 0x02 0x00 0x00 0x132004 0x01 0x00 0x00 0x133000 0x01 0x00 0x00 0x13300c 0x01 0x00 0x00 0x133140 0x01 0x00 0x00 0x13314c 0x01 0x00 0x00 0x134004 0x01 0x00 0x00 0x135004 0x02 0x00 0x00 0x136004 0x07 0x00 0x00 0x137004 0x03 0x00 0x00 0x137014 0x01 0x00 0x00 0x142004 0x02 0x00 0x00 0x142014 0x02 0x00 0x00 0x143004 0x03 0x00 0x00 0x144004 0x06 0x00 0x00 0x146004 0x02 0x00 0x00 0x147004 0x02 0x00 0x00 0x148004 0x01 0x00 0x00 0x149018 0x01 0x00 0x00 0x149020 0x02 0x00 0x00 0x14905c 0x03 0x00 0x00 0x149084 0x03 0x00 0x00 0x14a004 0x02 0x00 0x00 0x14b004 0x03 0x00 0x00 0x14b028 0x02 0x00 0x00 0x14c004 0x03 0x00 0x00 0x14d000 0x01 0x00 0x00 0x150004 0x07 0x00 0x00 0x151004 0x01 0x00 0x00 0x15100c 0x02 0x00 0x00 0x153000 0x06 0x00 0x00 0x154004 0x08 0x00 0x00 0x156004 0x04 0x00 0x00 0x15602c 0x02 0x00 0x00 0x157000 0x06 0x00 0x00 0x15701c 0x02 0x00 0x00 0x158000 0x04 0x00 0x00 0x158174 0x03 0x00 0x00 0x159004 0x01 0x00 0x00 0x15e004 0x02 0x00 0x00 0x172008 0x02 0x00 0x00 0x172018 0x01 0x00 0x00 0x174000 0x01 0x00 0x00 0x175000 0x01 0x00 0x00 0x176000 0x01 0x00 0x00 0x17a004 0x01 0x00 0x00 0x17b018 0x03 0x00 0x00 0x17b028 0x01 0x00 0x00 0x17b030 0x02 0x00 0x00 0x17b03c 0x01 0x00 0x00 0x17b044 0x01 0x00 0x00 0x17b08c 0x03 0x00 0x00 0x181004 0x06 0x00 0x00 0x181154 0x01 0x00 0x00 0x184004 0x18 0x00 0x00 0x184794 0x01 0x00 0x00 0x18479c 0x01 0x00 0x00 0x1847a4 0x01 0x00 0x00 0x1847ac 0x02 0x00 0x00 0x1847b8 0x0a 0x00 0x00 0x186004 0x06 0x00 0x00 0x187018 0x01 0x00 0x00 0x187020 0x03 0x00 0x00 0x187064 0x01 0x00 0x00 0x18706c 0x01 0x00 0x00 0x1870a4 0x01 0x00 0x00 0x1870c0 0x01 0x00 0x00 0x1870d4 0x01 0x00 0x00 0x188040 0x01 0x00 0x00 0x18a004 0x06 0x00 0x00 0x18a04c 0x05 0x00 0x00 0x192004 0x0f 0x00 0x00 0x1923f0 0x01 0x00 0x00 0x1923f8 0x03 0x00 0x00 0x193004 0x02 0x00 0x00 0x193140 0x01 0x00 0x00 0x194004 0x01 0x00 0x00 0x198004 0x01 0x00 0x00 0x199018 0x01 0x00 0x00 0x199020 0x01 0x00 0x00 0x199028 0x02 0x00 0x00 0x199164 0x03 0x00 0x00 0x19a000 0x09 0x00 0x00 0x19a28c 0x03 0x00 0x00 0x19b004 0x03 0x00 0x00 0x1a0884 0x01 0x00 0x00 0x1a915c 0x02 0x00 0x00 0x1a9464 0x02 0x00 0x00 0x1a0004 0x01 0x00 0x00 0x1a000c 0x01 0x00 0x00 0x1a0014 0x01 0x00 0x00 0x1a8004 0x01 0x00 0x00 0x1b0134 0x02 0x00 0x00 0x1b0154 0x09 0x00 0x00 0x1b017c 0x01 0x00 0x00 0x1b2004 0x07 0x00 0x00 0x1b3004 0x02 0x00 0x00 0x1b3028 0x01 0x00 0x00 0x1b3048 0x01 0x00 0x00 0x100000 0x02 0x00 0x00 0x101000 0x02 0x00 0x00 0x102000 0x02 0x00 0x00 0x103000 0x02 0x00 0x00 0x104000 0x02 0x00 0x00 0x105000 0x02 0x00 0x00 0x106000 0x02 0x00 0x00 0x107000 0x02 0x00 0x00 0x108000 0x02 0x00 0x00 0x109000 0x02 0x00 0x00 0x10a000 0x02 0x00 0x00 0x116100 0x01 0x00 0x00 0x120004 0x02 0x00 0x00 0x127028 0x01 0x00 0x00 0x12715c 0x01 0x00 0x00 0x127290 0x01 0x00 0x00 0x1273c4 0x01 0x00 0x00 0x1274f8 0x01 0x00 0x00 0x128028 0x01 0x00 0x00 0x12815c 0x01 0x00 0x00 0x128290 0x01 0x00 0x00 0x1283c4 0x01 0x00 0x00 0x1284f8 0x01 0x00 0x00 0x12c004 0x02 0x00 0x00 0x12c058 0x01 0x00 0x00 0x133028 0x01 0x00 0x00 0x146020 0x01 0x00 0x00 0x149004 0x02 0x00 0x00 0x151028 0x01 0x00 0x00 0x154164 0x01 0x00 0x00 0x16301c 0x01 0x00 0x00 0x163024 0x01 0x00 0x00 0x16302c 0x01 0x00 0x00 0x163034 0x01 0x00 0x00 0x165000 0x01 0x00 0x00 0x165008 0x01 0x00 0x00 0x165010 0x01 0x00 0x00 0x165018 0x01 0x00 0x00 0x166000 0x01 0x00 0x00 0x166008 0x01 0x00 0x00 0x166010 0x01 0x00 0x00 0x166018 0x01 0x00 0x00 0x167000 0x01 0x00 0x00 0x167008 0x01 0x00 0x00 0x167010 0x01 0x00 0x00 0x167018 0x01 0x00 0x00 0x16a000 0x01 0x00 0x00 0x16a008 0x01 0x00 0x00 0x16a010 0x01 0x00 0x00 0x16a018 0x01 0x00 0x00 0x17901c 0x01 0x00 0x00 0x179024 0x01 0x00 0x00 0x17902c 0x01 0x00 0x00 0x179034 0x01 0x00 0x00 0x17b004 0x02 0x00 0x00 0x184078 0x01 0x00 0x00 0x186038 0x01 0x00 0x00 0x187004 0x02 0x00 0x00 0x193024 0x01 0x00 0x00 0x199004 0x02 0x00 0x00 0x199044 0x01 0x00 0x00 0x1b101c 0x01 0x00 0x00 0x1b1024 0x01 0x00 0x00 0x1b102c 0x01 0x00 0x00 0x1b1034 0x01 0x00 0x00 0xc2a0000 0x02 0x00 0x00 0xc2a1000 0x02 0x00 0x00 0xc2a900c 0x01 0x00 0x00 0xc2a901c 0x01 0x00 0x00 0xc2a9024 0x01 0x00 0x00 0x17260000 0x01 0x00 0x00 0x17260014 0x01 0x00 0x00 0x17280000 0x01 0x00 0x00 0x17280014 0x01 0x00 0x00 0x172a0000 0x01 0x00 0x00 0x172a0014 0x01 0x00 0x00 0x172c0000 0x01 0x00 0x00 0x172c0014 0x01 0x00 0x00 0x172e0000 0x01 0x00 0x00 0x172e0014 0x01 0x00 0x00 0x17421000 0x10 0x00 0x00 0x17206138 0x01 0x00 0x00 0x17206140 0x01 0x00 0x00 0x17206148 0x01 0x00 0x00 0xc2f0000 0x01 0x00 0x00 0xc2f1000 0x01 0x00 0x00 0xc2f1004 0x01 0x00 0x00 0xc2a8014 0x01 0x00 0x00 0xc2a8030 0x01 0x00 0x00 0xc2a8028 0x01 0x00 0x00 0xc2a8130 0x01 0x00 0x00 0x190a8188 0x01 0x00 0x00 0x190a818c 0x01 0x00 0x00 0x190a8198 0x01 0x00 0x00 0x190a8194 0x01 0x00 0x00 0xc2f3000 0x01 0x00 0x00 0xc2a8038 0x01 0x00 0x00 0xc2a80dc 0x01 0x00 0x00 0xc2a80e0 0x01 0x00 0x00 0xc2a80e4 0x01 0x00 0x00 0xc2a80e8 0x01 0x00 0x00 0xc2a803c 0x01 0x00 0x00 0xc2a81a0 0x01 0x00 0x00 0xc2a8180 0x01 0x00 0x00 0xc2a8178 0x01 0x00 0x00 0xc2a817c 0x01 0x00 0x00 0xc2a8048 0x01 0x00 0x00 0xadf4004 0x01 0x00 0x00 0xadf2004 0x01 0x00 0x00 0xadf3004 0x01 0x00 0x00 0xadf302c 0x01 0x00 0x00 0xadf300c 0x01 0x00>; | |
| qcom,data-sink = "sram"; | |
| qcom,curr-link-list = <0x04>; | |
| }; | |
| }; | |
| rx_core_tx_clk { | |
| qcom,codec-ext-clk-src = <0x0d>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x312>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x475>; | |
| }; | |
| qcom,msm-pcm-loopback { | |
| compatible = "qcom,msm-pcm-loopback"; | |
| phandle = <0x389>; | |
| }; | |
| qcom,guestvm_loader@e0600000 { | |
| compatible = "qcom,guestvm-loader"; | |
| qcom,vmid = <0x32>; | |
| memory-region = <0x187>; | |
| qcom,firmware-name = "cpusys_vm"; | |
| qcom,pas-id = <0x23>; | |
| }; | |
| qcom,msm-dai-tdm-quat-tx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9131>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9031>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3d8>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-quat-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9031>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3d9>; | |
| }; | |
| }; | |
| qcom,gdsc@ad13004 { | |
| regulator-name = "cam_cc_ife_0_gdsc"; | |
| reg = <0xad13004 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x310>; | |
| qcom,retain-regs; | |
| }; | |
| wsa2_core_tx_clk { | |
| qcom,codec-ext-clk-src = <0x0f>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x316>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x477>; | |
| }; | |
| qcom,gdsc@aaf81a4 { | |
| regulator-name = "video_cc_mvs0_gdsc"; | |
| reg = <0xaaf81a4 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x32a>; | |
| qcom,retain-regs; | |
| }; | |
| spi@98c000 { | |
| dmas = <0x1a1 0x00 0x03 0x01 0x40 0x00 0x1a1 0x01 0x03 0x01 0x40 0x00>; | |
| qcom,wrapper-core = <0x19a>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x44 0x24 0x54 0x24 0x55>; | |
| #size-cells = <0x00>; | |
| reg-names = "se_phys"; | |
| #address-cells = <0x01>; | |
| spi-max-frequency = <0x2faf080>; | |
| reg = <0x98c000 0x4000>; | |
| interrupts = <0x00 0x25c 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1b1>; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x338>; | |
| pinctrl-0 = <0x1ad 0x1ae 0x1af 0x1b0>; | |
| }; | |
| qcom,msm-dai-tdm-sen-rx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9150>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9050>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3de>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-sen-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9050>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3df>; | |
| }; | |
| }; | |
| replicator@10b06000 { | |
| qcom,replicator-loses-context; | |
| coresight-name = "coresight-replicator_swao"; | |
| clocks = <0x31>; | |
| reg-names = "replicator-base"; | |
| reg = <0x10b06000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x26a>; | |
| arm,primecell-periphid = <0xbb909>; | |
| out-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@0 { | |
| endpoint { | |
| remote-endpoint = <0x106>; | |
| phandle = <0x108>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x107>; | |
| phandle = <0x102>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x105>; | |
| phandle = <0x104>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-sec-tx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9111>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9011>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3d0>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-sec-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9011>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3d1>; | |
| }; | |
| }; | |
| wsa_spkr_en2_pinctrl { | |
| status = "disabled"; | |
| pinctrl-1 = <0x2fa>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x47d>; | |
| pinctrl-0 = <0x2fb>; | |
| }; | |
| cti@10cc3000 { | |
| coresight-name = "coresight-cti-tmess_cti_1"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10cc3000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x287>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,gdsc@18d060 { | |
| regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; | |
| reg = <0x18d060 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x327>; | |
| }; | |
| syscon@1f40000 { | |
| reg = <0x1f40000 0x20000>; | |
| compatible = "syscon"; | |
| phandle = <0x138>; | |
| }; | |
| ufshc@1d84000 { | |
| vcc-max-microamp = <0x101d00>; | |
| reset-gpios = <0x126 0x88 0x01>; | |
| vcc-supply = <0x2ae>; | |
| qcom,vddp-ref-clk-supply = <0x2a2>; | |
| ufs-dev-types = <0x02>; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| qcom,ufs-bus-bw,vectors-KBps = <0x00 0x00 0x00 0x00 0x39a 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x1f334 0x00 0x3e8 0x00 0x3e667 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x3e667 0x00 0x3e8 0x00 0x7cccd 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x00 0x2c7b80 0x00 0x64000 0x00 0x247ae 0x00 0x3e8 0x00 0x48ccd 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x48ccd 0x00 0x3e8 0x00 0x9199a 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x64000 0x2c7b80 0x00 0x64000 0x64000 0x74a000 0x00 0x4b000 0x00>; | |
| resets = <0x24 0x11>; | |
| phy-names = "ufsphy"; | |
| clocks = <0x24 0x63 0x24 0x09 0x24 0x62 0x24 0x6f 0x24 0x65 0x45 0x00 0x24 0x6d 0x24 0x69 0x24 0x6b>; | |
| dev-ref-clk-freq = <0x00>; | |
| reg-names = "ufs_mem\0ufs_ice\0ufs_ice_hwkm"; | |
| vccq-supply = <0x2a2>; | |
| qcom,vddp-ref-clk-max-microamp = <0x64>; | |
| nvmem-cells = <0x41a 0x152>; | |
| lanes-per-direction = <0x02>; | |
| qcom,ufs-bus-bw,num-cases = <0x1a>; | |
| reg = <0x1d84000 0x3000 0x1d88000 0x8000 0x1d90000 0x9000>; | |
| qcom,ufs-bus-bw,num-paths = <0x02>; | |
| reset-names = "rst"; | |
| interrupts = <0x00 0x109 0x04>; | |
| vdd-hba-supply = <0x18c>; | |
| vccq-max-microamp = <0xb71b0>; | |
| interconnect-names = "ufs-ddr\0cpu-ufs"; | |
| status = "ok"; | |
| vccq2-max-microamp = <0xb71b0>; | |
| interconnects = <0x3c 0x35 0x29 0x200 0x25 0x02 0x3d 0x225>; | |
| dma-coherent; | |
| compatible = "qcom,ufshc"; | |
| phys = <0x140>; | |
| qcom,ufs-dev-revert; | |
| freq-table-hz = <0x47868c0 0x11e1a300 0x00 0x00 0x00 0x00 0x47868c0 0x11e1a300 0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk"; | |
| qcom,ufs-bus-bw,name = "ufshc_mem"; | |
| phandle = <0x13f>; | |
| qcom,iommu-dma = "fastmap"; | |
| iommus = <0x2f 0x580 0x00>; | |
| vccq2-supply = <0x2a5>; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0PWM_G1_L2\0PWM_G2_L2\0PWM_G3_L2\0PWM_G4_L2\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RA_G4_L1\0HS_RA_G1_L2\0HS_RA_G2_L2\0HS_RA_G3_L2\0HS_RA_G4_L2\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0HS_RB_G4_L1\0HS_RB_G1_L2\0HS_RB_G2_L2\0HS_RB_G3_L2\0HS_RB_G4_L2\0MAX"; | |
| nvmem-cell-names = "ufs_dev\0boot_conf"; | |
| #reset-cells = <0x01>; | |
| qos1 { | |
| mask = <0x0f>; | |
| vote = <0x2c>; | |
| }; | |
| qos0 { | |
| mask = <0xf0>; | |
| perf; | |
| vote = <0x2c>; | |
| }; | |
| }; | |
| qcom,userspace-cdev { | |
| compatible = "qcom,userspace-cooling-devices"; | |
| display-fps { | |
| qcom,max-level = <0x03>; | |
| phandle = <0x357>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| pinctrl@f000000 { | |
| reg = <0xf000000 0x1000000>; | |
| interrupts = <0x00 0xd0 0x04>; | |
| wakeup-parent = <0x3b>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| compatible = "qcom,ravelin-pinctrl"; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| phandle = <0x126>; | |
| qupv3_se3_4uart_pins { | |
| phandle = <0x2eb>; | |
| qupv3_se3_4uart_tx_active { | |
| phandle = <0x1b2>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "qup0_se3_l2"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| bias-pull-up; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| qupv3_se3_4uart_sleep { | |
| phandle = <0x1b4>; | |
| mux { | |
| pins = "gpio20\0gpio21"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio20\0gpio21"; | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se3_4uart_rx_active { | |
| phandle = <0x1b3>; | |
| mux { | |
| pins = "gpio21"; | |
| function = "qup0_se3_l3"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| bias-pull-up; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| }; | |
| pm8010n-active { | |
| phandle = <0x407>; | |
| mux { | |
| pins = "gpio30"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio30"; | |
| output-high; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pmx_sde { | |
| phandle = <0x46b>; | |
| sde_dsi_active { | |
| phandle = <0x44d>; | |
| mux { | |
| pins = "gpio92"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable = <0x00>; | |
| pins = "gpio92"; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| sde_dsi_suspend { | |
| phandle = <0x44f>; | |
| mux { | |
| pins = "gpio92"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio92"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se8_spi_pins { | |
| phandle = <0x2f3>; | |
| qupv3_se8_spi_sleep { | |
| phandle = <0x1d9>; | |
| mux { | |
| pins = "gpio24\0gpio25\0gpio51\0gpio50"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio24\0gpio25\0gpio51\0gpio50"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se8_spi_mosi_active { | |
| phandle = <0x1d5>; | |
| mux { | |
| pins = "gpio25"; | |
| function = "qup1_se3_l1"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se8_spi_clk_active { | |
| phandle = <0x1d7>; | |
| mux { | |
| pins = "gpio51"; | |
| function = "qup1_se3_l2"; | |
| }; | |
| config { | |
| pins = "gpio51"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se8_spi_miso_active { | |
| phandle = <0x1d6>; | |
| mux { | |
| pins = "gpio24"; | |
| function = "qup1_se3_l0"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se8_spi_cs_active { | |
| phandle = <0x1d8>; | |
| mux { | |
| pins = "gpio50"; | |
| function = "qup1_se3_l3"; | |
| }; | |
| config { | |
| pins = "gpio50"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| }; | |
| wcd_reset_sleep { | |
| phandle = <0x2fd>; | |
| mux { | |
| pins = "gpio96"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio96"; | |
| output-low; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| display_panel_avdd_default { | |
| phandle = <0x455>; | |
| mux { | |
| pins = "gpio127"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable = <0x00>; | |
| pins = "gpio127"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| pcie0 { | |
| pcie0_clkreq_default { | |
| phandle = <0x1e5>; | |
| mux { | |
| pins = "gpio107"; | |
| function = "pcie0_clk_req"; | |
| }; | |
| config { | |
| pins = "gpio107"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pcie0_wake_default { | |
| phandle = <0x1e6>; | |
| mux { | |
| pins = "gpio31"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio31"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pcie0_clkreq_sleep { | |
| phandle = <0x1e7>; | |
| mux { | |
| pins = "gpio107"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio107"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pcie0_perst_default { | |
| phandle = <0x1e4>; | |
| mux { | |
| pins = "gpio32"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio32"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| sdc1_off { | |
| phandle = <0x2ff>; | |
| clk { | |
| bias-disable; | |
| pins = "sdc1_clk"; | |
| drive-strength = <0x02>; | |
| }; | |
| rclk { | |
| pins = "sdc1_rclk"; | |
| bias-pull-down; | |
| }; | |
| data { | |
| pins = "sdc1_data"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| cmd { | |
| pins = "sdc1_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se5_spi_pins { | |
| phandle = <0x2ef>; | |
| qupv3_se5_spi_sleep { | |
| phandle = <0x1c9>; | |
| mux { | |
| pins = "gpio0\0gpio1\0gpio2\0gpio3"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio0\0gpio1\0gpio2\0gpio3"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se5_spi_mosi_active { | |
| phandle = <0x1c5>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "qup1_se0_l1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se5_spi_clk_active { | |
| phandle = <0x1c7>; | |
| mux { | |
| pins = "gpio2"; | |
| function = "qup1_se0_l2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se5_spi_cs_active { | |
| phandle = <0x1c8>; | |
| mux { | |
| pins = "gpio3"; | |
| function = "qup1_se0_l3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se5_spi_miso_active { | |
| phandle = <0x1c6>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "qup1_se0_l0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se1_i2c_pins { | |
| phandle = <0x2e7>; | |
| qupv3_se1_i2c_sda_active { | |
| phandle = <0x1a2>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "qup0_se1_l0"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se1_i2c_scl_active { | |
| phandle = <0x1a3>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "qup0_se1_l1"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se1_i2c_sleep { | |
| phandle = <0x1a4>; | |
| mux { | |
| pins = "gpio10\0gpio11"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio10\0gpio11"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se2_4uart_pins { | |
| phandle = <0x2e4>; | |
| qupv3_se2_default_cts { | |
| phandle = <0x192>; | |
| mux { | |
| pins = "gpio14"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se2_default_tx { | |
| phandle = <0x194>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se2_rts { | |
| phandle = <0x197>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "qup0_se2_l1"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se2_default_rx { | |
| phandle = <0x195>; | |
| mux { | |
| pins = "gpio17"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se2_tx { | |
| phandle = <0x198>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "qup0_se2_l2"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se2_cts { | |
| phandle = <0x196>; | |
| mux { | |
| pins = "gpio14"; | |
| function = "qup0_se2_l0"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio14"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se2_default_rts { | |
| phandle = <0x193>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se2_rx { | |
| phandle = <0x199>; | |
| mux { | |
| pins = "gpio17"; | |
| function = "qup0_se2_l3"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| spkr_1_sd_n { | |
| spkr_1_sd_n_sleep { | |
| phandle = <0x2f8>; | |
| mux { | |
| pins = "gpio99"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio99"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| spkr_1_sd_n_active { | |
| phandle = <0x2f9>; | |
| mux { | |
| pins = "gpio99"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio99"; | |
| output-high; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se6_spi_pins { | |
| phandle = <0x2f1>; | |
| qupv3_se6_spi_sleep { | |
| phandle = <0x1d1>; | |
| mux { | |
| pins = "gpio50\0gpio51\0gpio26\0gpio27"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio50\0gpio51\0gpio26\0gpio27"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se6_spi_cs_active { | |
| phandle = <0x1d0>; | |
| mux { | |
| pins = "gpio27"; | |
| function = "qup1_se1_l3"; | |
| }; | |
| config { | |
| pins = "gpio27"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se6_spi_clk_active { | |
| phandle = <0x1cf>; | |
| mux { | |
| pins = "gpio26"; | |
| function = "qup1_se1_l2"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se6_spi_miso_active { | |
| phandle = <0x1ce>; | |
| mux { | |
| pins = "gpio50"; | |
| function = "qup1_se1_l0"; | |
| }; | |
| config { | |
| pins = "gpio50"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se6_spi_mosi_active { | |
| phandle = <0x1cd>; | |
| mux { | |
| pins = "gpio51"; | |
| function = "qup1_se1_l1"; | |
| }; | |
| config { | |
| pins = "gpio51"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| }; | |
| spkr_2_sd_n { | |
| spkr_2_sd_n_sleep { | |
| phandle = <0x2fa>; | |
| mux { | |
| pins = "gpio100"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio100"; | |
| bias-pull-down; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| spkr_2_sd_n_active { | |
| phandle = <0x2fb>; | |
| mux { | |
| pins = "gpio100"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio100"; | |
| output-high; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_release { | |
| ts_spi_release { | |
| phandle = <0x309>; | |
| mux { | |
| pins = "gpio90\0gpio91"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio90\0gpio91"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| ts_release { | |
| phandle = <0x308>; | |
| mux { | |
| pins = "gpio12\0gpio13"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio12\0gpio13"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| bt_en_sleep { | |
| phandle = <0x1f0>; | |
| mux { | |
| pins = "gpio39"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio39"; | |
| bias-pull-down; | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| sdc1_on { | |
| phandle = <0x2fe>; | |
| clk { | |
| bias-disable; | |
| pins = "sdc1_clk"; | |
| drive-strength = <0x10>; | |
| }; | |
| rclk { | |
| pins = "sdc1_rclk"; | |
| bias-pull-down; | |
| }; | |
| data { | |
| pins = "sdc1_data"; | |
| bias-pull-up; | |
| drive-strength = <0x0a>; | |
| }; | |
| cmd { | |
| pins = "sdc1_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x0a>; | |
| }; | |
| }; | |
| key_vol_up_default { | |
| phandle = <0x404>; | |
| mux { | |
| pins = "gpio53"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio53"; | |
| bias-pull-up; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se4_spi_pins { | |
| phandle = <0x2ed>; | |
| qupv3_se4_spi_cs_active { | |
| phandle = <0x1bb>; | |
| mux { | |
| pins = "gpio7"; | |
| function = "qup0_se4_l3"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se4_spi_sleep { | |
| phandle = <0x1bc>; | |
| mux { | |
| pins = "gpio8\0gpio9\0gpio6\0gpio7"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio8\0gpio9\0gpio6\0gpio7"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se4_spi_mosi_active { | |
| phandle = <0x1b8>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "qup0_se4_l1_mira"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se4_spi_miso_active { | |
| phandle = <0x1b9>; | |
| mux { | |
| pins = "gpio8"; | |
| function = "qup0_se4_l0_mira"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se4_spi_clk_active { | |
| phandle = <0x1ba>; | |
| mux { | |
| pins = "gpio6"; | |
| function = "qup0_se4_l2"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se0_2uart_pins { | |
| phandle = <0x2e5>; | |
| qupv3_se0_2uart_rx_active { | |
| phandle = <0x19c>; | |
| mux { | |
| pins = "gpio35"; | |
| function = "qup0_se0_l3"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio35"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se0_2uart_sleep { | |
| phandle = <0x19d>; | |
| mux { | |
| pins = "gpio34\0gpio35"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio34\0gpio35"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se0_2uart_tx_active { | |
| phandle = <0x19b>; | |
| mux { | |
| pins = "gpio34"; | |
| function = "qup0_se0_l2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio34"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se1_spi_pins { | |
| phandle = <0x2e8>; | |
| qupv3_se1_spi_cs_active { | |
| phandle = <0x1a8>; | |
| mux { | |
| pins = "gpio13"; | |
| function = "qup0_se1_l3"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se1_spi_mosi_active { | |
| phandle = <0x1a5>; | |
| mux { | |
| pins = "gpio11"; | |
| function = "qup0_se1_l1"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se1_spi_sleep { | |
| phandle = <0x1a9>; | |
| mux { | |
| pins = "gpio10\0gpio11\0gpio12\0gpio13"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio10\0gpio11\0gpio12\0gpio13"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se1_spi_clk_active { | |
| phandle = <0x1a7>; | |
| mux { | |
| pins = "gpio12"; | |
| function = "qup0_se1_l2"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se1_spi_miso_active { | |
| phandle = <0x1a6>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "qup0_se1_l0"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| }; | |
| pmx_sde_te { | |
| phandle = <0x46c>; | |
| sde_te_suspend { | |
| phandle = <0x450>; | |
| mux { | |
| pins = "gpio93"; | |
| function = "mdp_vsync_p"; | |
| }; | |
| config { | |
| pins = "gpio93"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| sde_te_active { | |
| phandle = <0x44e>; | |
| mux { | |
| pins = "gpio93"; | |
| function = "mdp_vsync_p"; | |
| }; | |
| config { | |
| pins = "gpio93"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_active { | |
| ts_spi_active { | |
| phandle = <0x303>; | |
| mux { | |
| pins = "gpio90\0gpio91"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio90\0gpio91"; | |
| bias-pull-up; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| ts_active { | |
| phandle = <0x302>; | |
| mux { | |
| pins = "gpio12\0gpio13"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio12\0gpio13"; | |
| bias-pull-up; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se4_i2c_pins { | |
| phandle = <0x2ec>; | |
| qupv3_se4_i2c_sleep { | |
| phandle = <0x1b7>; | |
| mux { | |
| pins = "gpio26\0gpio27"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio26\0gpio27"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se4_i2c_scl_active { | |
| phandle = <0x1b6>; | |
| mux { | |
| pins = "gpio27"; | |
| function = "qup0_se4_l1"; | |
| }; | |
| config { | |
| pins = "gpio27"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se4_i2c_sda_active { | |
| phandle = <0x1b5>; | |
| mux { | |
| pins = "gpio26"; | |
| function = "qup0_se4_l0"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| nfc { | |
| nfc_int_suspend { | |
| phandle = <0x30b>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| nfc_enable_suspend { | |
| phandle = <0x30d>; | |
| mux { | |
| pins = "gpio6\0gpio8\0gpio7"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio6\0gpio8\0gpio7"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| nfc_enable_active { | |
| phandle = <0x30c>; | |
| mux { | |
| pins = "gpio6\0gpio8\0gpio7"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio6\0gpio8\0gpio7"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| nfc_int_active { | |
| phandle = <0x30a>; | |
| mux { | |
| pins = "gpio9"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| usb_phy_ps { | |
| phandle = <0x30e>; | |
| usb3phy_portselect_default { | |
| phandle = <0x49>; | |
| mux { | |
| pins = "gpio94"; | |
| function = "usb0_phy_ps"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio94"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se0_i2c_pins { | |
| phandle = <0x2e6>; | |
| qupv3_se0_i2c_scl_active { | |
| phandle = <0x19f>; | |
| mux { | |
| pins = "gpio5"; | |
| function = "qup0_se0_l1"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se0_i2c_sleep { | |
| phandle = <0x1a0>; | |
| mux { | |
| pins = "gpio4\0gpio5"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio4\0gpio5"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se0_i2c_sda_active { | |
| phandle = <0x19e>; | |
| mux { | |
| pins = "gpio4"; | |
| function = "qup0_se0_l0"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| cnss_pins { | |
| cnss_wlan_en_active { | |
| phandle = <0x1eb>; | |
| mux { | |
| pins = "gpio43"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio43"; | |
| output-high; | |
| bias-pull-up; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| cnss_wlan_en_sleep { | |
| phandle = <0x1ec>; | |
| mux { | |
| pins = "gpio43"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio43"; | |
| bias-pull-down; | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se8_i2c_pins { | |
| phandle = <0x2f2>; | |
| qupv3_se8_i2c_sda_active { | |
| phandle = <0x1d2>; | |
| mux { | |
| pins = "gpio24"; | |
| function = "qup1_se3_l0"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se8_i2c_scl_active { | |
| phandle = <0x1d3>; | |
| mux { | |
| pins = "gpio25"; | |
| function = "qup1_se3_l1"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se8_i2c_sleep { | |
| phandle = <0x1d4>; | |
| mux { | |
| pins = "gpio24\0gpio25"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio24\0gpio25"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| sdc2_off { | |
| phandle = <0x301>; | |
| clk { | |
| bias-disable; | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x02>; | |
| }; | |
| data { | |
| pins = "sdc2_data"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| cmd { | |
| pins = "sdc2_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| sd-cd { | |
| pins = "gpio101"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pm8010m-active { | |
| phandle = <0x405>; | |
| mux { | |
| pins = "gpio29"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio29"; | |
| output-high; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se9_i2c_pins { | |
| phandle = <0x2f4>; | |
| qupv3_se9_i2c_scl_active { | |
| phandle = <0x1db>; | |
| mux { | |
| pins = "gpio90"; | |
| function = "qup1_se4_l1"; | |
| }; | |
| config { | |
| pins = "gpio90"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se9_i2c_sleep { | |
| phandle = <0x1dc>; | |
| mux { | |
| pins = "gpio91\0gpio90"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio91\0gpio90"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se9_i2c_sda_active { | |
| phandle = <0x1da>; | |
| mux { | |
| pins = "gpio91"; | |
| function = "qup1_se4_l0"; | |
| }; | |
| config { | |
| pins = "gpio91"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se9_spi_pins { | |
| phandle = <0x2f5>; | |
| qupv3_se9_spi_clk_active { | |
| phandle = <0x1df>; | |
| mux { | |
| pins = "gpio48"; | |
| function = "qup1_se4_l2"; | |
| }; | |
| config { | |
| pins = "gpio48"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se9_spi_sleep { | |
| phandle = <0x1e1>; | |
| mux { | |
| pins = "gpio91\0gpio90\0gpio48\0gpio43"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio91\0gpio90\0gpio48\0gpio43"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se9_spi_miso_active { | |
| phandle = <0x1de>; | |
| mux { | |
| pins = "gpio91"; | |
| function = "qup1_se4_l0"; | |
| }; | |
| config { | |
| pins = "gpio91"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se9_spi_mosi_active { | |
| phandle = <0x1dd>; | |
| mux { | |
| pins = "gpio90"; | |
| function = "qup1_se4_l1"; | |
| }; | |
| config { | |
| pins = "gpio90"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se9_spi_cs_active { | |
| phandle = <0x1e0>; | |
| mux { | |
| pins = "gpio43"; | |
| function = "qup1_se4_l3"; | |
| }; | |
| config { | |
| pins = "gpio43"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| }; | |
| hwver_gpio_default { | |
| hwver_gpio_default { | |
| phandle = <0x2f7>; | |
| mux { | |
| pins = "gpio90\0gpio95\0gpio102\0gpio83"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio90\0gpio95\0gpio102\0gpio83"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se5_i2c_pins { | |
| phandle = <0x2ee>; | |
| qupv3_se5_i2c_sleep { | |
| phandle = <0x1c3>; | |
| mux { | |
| pins = "gpio0\0gpio1"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio0\0gpio1"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se5_i2c_scl_active { | |
| phandle = <0x1c2>; | |
| mux { | |
| pins = "gpio1"; | |
| function = "qup1_se0_l1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se5_i2c_sda_active { | |
| phandle = <0x1c1>; | |
| mux { | |
| pins = "gpio0"; | |
| function = "qup1_se0_l0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se3_i2c_pins { | |
| phandle = <0x2e9>; | |
| qupv3_se3_i2c_sda_active { | |
| phandle = <0x1aa>; | |
| mux { | |
| pins = "gpio18"; | |
| function = "qup0_se3_l0"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se3_i2c_scl_active { | |
| phandle = <0x1ab>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "qup0_se3_l1"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se3_i2c_sleep { | |
| phandle = <0x1ac>; | |
| mux { | |
| pins = "gpio18\0gpio19"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio18\0gpio19"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| sdc2_on { | |
| phandle = <0x300>; | |
| clk { | |
| bias-disable; | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x10>; | |
| }; | |
| data { | |
| pins = "sdc2_data"; | |
| bias-pull-up; | |
| drive-strength = <0x0a>; | |
| }; | |
| cmd { | |
| pins = "sdc2_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x0a>; | |
| }; | |
| sd-cd { | |
| pins = "gpio101"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pmx_ts_int_suspend { | |
| ts_spi_int_suspend { | |
| phandle = <0x307>; | |
| mux { | |
| pins = "gpio91"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio91"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| ts_int_suspend { | |
| phandle = <0x306>; | |
| mux { | |
| pins = "gpio13"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_reset_suspend { | |
| ts_reset_suspend { | |
| phandle = <0x304>; | |
| mux { | |
| pins = "gpio12"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| ts_spi_reset_suspend { | |
| phandle = <0x305>; | |
| mux { | |
| pins = "gpio90"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio90"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| wcd_reset_active { | |
| phandle = <0x2fc>; | |
| mux { | |
| pins = "gpio96"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio96"; | |
| output-high; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| qupv3_se6_i2c_pins { | |
| phandle = <0x2f0>; | |
| qupv3_se6_i2c_sda_active { | |
| phandle = <0x1ca>; | |
| mux { | |
| pins = "gpio50"; | |
| function = "qup1_se1_l0"; | |
| }; | |
| config { | |
| pins = "gpio50"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se6_i2c_sleep { | |
| phandle = <0x1cc>; | |
| mux { | |
| pins = "gpio50\0gpio51"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio50\0gpio51"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se6_i2c_scl_active { | |
| phandle = <0x1cb>; | |
| mux { | |
| pins = "gpio51"; | |
| function = "qup1_se1_l1"; | |
| }; | |
| config { | |
| pins = "gpio51"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qupv3_se7_2uart_pins { | |
| phandle = <0x2e3>; | |
| qupv3_se7_2uart_rx_active { | |
| phandle = <0x1be>; | |
| mux { | |
| pins = "gpio23"; | |
| function = "qup1_se2_l3"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio23"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se7_2uart_sleep { | |
| phandle = <0x1bf>; | |
| mux { | |
| pins = "gpio22\0gpio23"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio22\0gpio23"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se7_2uart_tx_active { | |
| phandle = <0x1bd>; | |
| mux { | |
| pins = "gpio22"; | |
| function = "qup1_se2_l2"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio22"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| fan_det_default { | |
| fan_det_default { | |
| phandle = <0x2f6>; | |
| mux { | |
| pins = "gpio52"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| bias-disable; | |
| pins = "gpio52"; | |
| input-enable; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| trigout_a { | |
| phandle = <0x110>; | |
| mux { | |
| function = "qdss_cti"; | |
| }; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se3_spi_pins { | |
| phandle = <0x2ea>; | |
| qupv3_se3_spi_cs_active { | |
| phandle = <0x1b0>; | |
| mux { | |
| pins = "gpio21"; | |
| function = "qup0_se3_l3"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se3_spi_mosi_active { | |
| phandle = <0x1ad>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "qup0_se3_l1"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se3_spi_miso_active { | |
| phandle = <0x1ae>; | |
| mux { | |
| pins = "gpio18"; | |
| function = "qup0_se3_l0"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se3_spi_clk_active { | |
| phandle = <0x1af>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "qup0_se3_l2"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| bias-pull-down; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| qupv3_se3_spi_sleep { | |
| phandle = <0x1b1>; | |
| mux { | |
| pins = "gpio18\0gpio19\0gpio20\0gpio21"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio18\0gpio19\0gpio20\0gpio21"; | |
| bias-pull-down; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@10804000 { | |
| coresight-name = "coresight-funnel-modem"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10804000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x256>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xaf>; | |
| phandle = <0xf0>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0xae>; | |
| phandle = <0xab>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xad>; | |
| phandle = <0xa6>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xac>; | |
| phandle = <0x73>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| csr@10b11000 { | |
| qcom,blk-size = <0x01>; | |
| qcom,timestamp-support; | |
| coresight-name = "coresight-swao-csr"; | |
| qcom,msr-support; | |
| clocks = <0x31>; | |
| reg-names = "csr-base\0msr-base"; | |
| reg = <0x10b11000 0x1000 0x10b110f8 0x50>; | |
| compatible = "qcom,coresight-csr"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x26f>; | |
| }; | |
| syscon@3d99504 { | |
| reg = <0x3d99504 0x04>; | |
| compatible = "syscon"; | |
| phandle = <0x18e>; | |
| }; | |
| tx_core_clk { | |
| qcom,codec-ext-clk-src = <0x07>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x30c>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x470>; | |
| }; | |
| qcom,qmp-aop { | |
| qcom,qmp = <0x31>; | |
| #mbox-cells = <0x01>; | |
| compatible = "qcom,qmp-mbox"; | |
| phandle = <0x02>; | |
| label = "aop"; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_2_in { | |
| interrupts-extended = <0x1fa 0x00 0x00>; | |
| interrupt-names = "rdbg-smp2p-in"; | |
| compatible = "qcom,smp2p-interrupt-rdbg-2-in"; | |
| }; | |
| kgsl-smmu@3da0000 { | |
| #iommu-cells = <0x02>; | |
| vdd-supply = <0x22>; | |
| clocks = <0x23 0x08 0x23 0x1c 0x23 0x18 0x24 0x23 0x24 0x24 0x23 0x02>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| reg-names = "base\0tcu-base"; | |
| #address-cells = <0x01>; | |
| qcom,num-smr-override = <0x07>; | |
| reg = <0x3da0000 0x10000 0x3dc2000 0x20>; | |
| interrupts = <0x00 0x2a2 0x04 0x00 0x2a6 0x04 0x00 0x2a7 0x04 0x00 0x2a8 0x04 0x00 0x2a9 0x04 0x00 0x2aa 0x04 0x00 0x2ab 0x04 0x00 0x2ac 0x04 0x00 0x2ad 0x04 0x00 0x2ae 0x04 0x00 0x2af 0x04 0x00 0x2b0 0x04 0x00 0x1a6 0x04>; | |
| qcom,regulator-names = "vdd"; | |
| #global-interrupts = <0x01>; | |
| qcom,actlr = <0x00 0x1fff 0x32b>; | |
| dma-coherent; | |
| compatible = "qcom,qsmmu-v500\0qcom,adreno-smmu"; | |
| clock-names = "gpu_cc_cx_gmu\0gpu_cc_hub_cx_int\0gpu_cc_hlos1_vote_gpu_smmu\0gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb"; | |
| phandle = <0x30>; | |
| qcom,use-3-lvl-tables; | |
| qcom,num-context-banks-override = <0x05>; | |
| gfx_1_tbu@3dc9000 { | |
| qcom,stream-id-range = <0x400 0x400>; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x3dc9000 0x1000 0x3dc2208 0x08>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| phandle = <0x217>; | |
| }; | |
| gfx_0_tbu@3dc5000 { | |
| qcom,stream-id-range = <0x00 0x400>; | |
| reg-names = "base\0status-reg"; | |
| reg = <0x3dc5000 0x1000 0x3dc2200 0x08>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| phandle = <0x216>; | |
| }; | |
| }; | |
| funnel@10c2c000 { | |
| coresight-name = "coresight-funnel-dlct0"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10c2c000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x25a>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xc8>; | |
| phandle = <0xf2>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0xc7>; | |
| phandle = <0xb6>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xc5>; | |
| phandle = <0xc4>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xc6>; | |
| phandle = <0x83>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| syscon@3d9958c { | |
| reg = <0x3d9958c 0x04>; | |
| compatible = "syscon"; | |
| phandle = <0x329>; | |
| }; | |
| vote_lpass_core_hw { | |
| qcom,codec-ext-clk-src = <0x09>; | |
| #clock-cells = <0x01>; | |
| status = "disabled"; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x378>; | |
| }; | |
| ufsphy_mem@1d87000 { | |
| vdda-pll-supply = <0x47>; | |
| vdda-phy-supply = <0x42>; | |
| resets = <0x13f 0x00>; | |
| clocks = <0x45 0x00 0x24 0x67 0x24 0x60 0x24 0x6a 0x24 0x6c 0x24 0x6e 0x132 0x133 0x134>; | |
| reg-names = "phy_mem"; | |
| lanes-per-direction = <0x02>; | |
| reg = <0x1d87000 0xe10>; | |
| vdda-pll-max-microamp = <0x4786>; | |
| status = "ok"; | |
| vdda-phy-max-microamp = <0x159d2>; | |
| compatible = "qcom,ufs-phy-qmp-v4-parrot"; | |
| #phy-cells = <0x00>; | |
| clock-names = "ref_clk_src\0ref_aux_clk\0qref_clk\0rx_sym0_mux_clk\0rx_sym1_mux_clk\0tx_sym0_mux_clk\0rx_sym0_phy_clk\0rx_sym1_phy_clk\0tx_sym0_phy_clk"; | |
| phandle = <0x140>; | |
| }; | |
| qcom,icnss@22800000 { | |
| qcom,vdd-3.3-ch0-config = <0x2dc6c0 0x328980>; | |
| qcom,vdd-cx-mx-config = <0x00 0x00>; | |
| wpss-support-enable; | |
| qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; | |
| qcom,smem-states = <0x1f3 0x00>; | |
| qcom,smem-state-names = "wlan-smp2p-out"; | |
| vdd-1.8-xo-supply = <0x43>; | |
| qcom,wlan; | |
| reg-names = "membase"; | |
| qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; | |
| reg = <0x22800000 0x800000>; | |
| interrupts = <0x00 0x185 0x04 0x00 0x19d 0x04 0x00 0x1a0 0x04 0x00 0x1a1 0x04 0x00 0x1b2 0x04 0x00 0x1b3 0x04 0x00 0x1b6 0x04 0x00 0x1b7 0x04 0x00 0x1b8 0x04 0x00 0x1c3 0x04 0x00 0x1c5 0x04 0x00 0x1c6 0x04>; | |
| bdf-download-support; | |
| vdd-cx-mx-supply = <0x127>; | |
| vdd-1.3-rfa-supply = <0x128>; | |
| compatible = "qcom,icnss"; | |
| qcom,rproc-handle = <0x41b>; | |
| qcom,wlan-msa-fixed-region = <0x41c>; | |
| phandle = <0x449>; | |
| qcom,iommu-dma = "fastmap"; | |
| iommus = <0x2f 0x4c0 0x01>; | |
| vdd-3.3-ch0-supply = <0x129>; | |
| qcom,iommu-geometry = <0xa0000000 0x10000000>; | |
| qcom,fw-prefix; | |
| qcom,smp2p_map_wlan_1_in { | |
| interrupts-extended = <0x1f6 0x00 0x00 0x1f6 0x01 0x00>; | |
| interrupt-names = "qcom,smp2p-force-fatal-error\0qcom,smp2p-early-crash-ind"; | |
| }; | |
| }; | |
| qcom,pcie0_msi@0x17210040 { | |
| reg = <0x17210040 0x00>; | |
| interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>; | |
| interrupt-parent = <0x01>; | |
| status = "disabled"; | |
| compatible = "qcom,pci-msi"; | |
| msi-controller; | |
| phandle = <0x1e3>; | |
| }; | |
| tpda@12863000 { | |
| coresight-name = "coresight-tpda-apss"; | |
| qcom,dsb-elem-size = <0x04 0x20>; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x12863000 0x1000>; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x00 0x20 0x03 0x40>; | |
| qcom,tpda-atid = <0x42>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x257>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xb3>; | |
| phandle = <0xb5>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0xb1>; | |
| phandle = <0x6e>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xb0>; | |
| phandle = <0x6d>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xb2>; | |
| phandle = <0x6f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cpu-hotplug { | |
| compatible = "qcom,cpu-hotplug"; | |
| cpu2-hotplug { | |
| qcom,cpu = <0x1c>; | |
| qcom,cdev-alias = "cpu-hotplug2"; | |
| phandle = <0x351>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu1-hotplug { | |
| qcom,cpu = <0x1b>; | |
| qcom,cdev-alias = "cpu-hotplug1"; | |
| phandle = <0x350>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu6-hotplug { | |
| qcom,cpu = <0x20>; | |
| qcom,cdev-alias = "cpu-hotplug6"; | |
| phandle = <0x355>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu0-hotplug { | |
| qcom,cpu = <0x1a>; | |
| qcom,cdev-alias = "cpu-hotplug0"; | |
| phandle = <0x34f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu3-hotplug { | |
| qcom,cpu = <0x1d>; | |
| qcom,cdev-alias = "cpu-hotplug3"; | |
| phandle = <0x352>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu5-hotplug { | |
| qcom,cpu = <0x1f>; | |
| qcom,cdev-alias = "cpu-hotplug5"; | |
| phandle = <0x354>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu4-hotplug { | |
| qcom,cpu = <0x1e>; | |
| qcom,cdev-alias = "cpu-hotplug4"; | |
| phandle = <0x353>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu7-hotplug { | |
| qcom,cpu = <0x21>; | |
| qcom,cdev-alias = "cpu-hotplug7"; | |
| phandle = <0x356>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| clock-controller@af00000 { | |
| vdd_mx-supply = <0x125>; | |
| #clock-cells = <0x01>; | |
| clocks = <0x45 0x00 0x45 0x01 0x130 0x24 0x16>; | |
| reg-name = "cc_base"; | |
| reg = <0xaf00000 0x20000>; | |
| compatible = "qcom,ravelin-dispcc\0syscon"; | |
| clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; | |
| phandle = <0x12a>; | |
| vdd_cx-supply = <0x124>; | |
| #reset-cells = <0x01>; | |
| }; | |
| qcom,sps { | |
| compatible = "qcom,msm-sps-4k"; | |
| qcom,pipe-attr-ee; | |
| }; | |
| va_mini_dump { | |
| status = "ok"; | |
| compatible = "qcom,va-minidump"; | |
| memory-region = <0x14c>; | |
| }; | |
| cti@10982000 { | |
| coresight-name = "coresight-cti-turing_dl_cti_0"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10982000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x279>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| cti@10d0c000 { | |
| coresight-name = "coresight-cti-ddr_dl_1_cti_0"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10d0c000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x274>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| cti@10b4b000 { | |
| coresight-name = "coresight-cti-lpass_q6_cti"; | |
| clocks = <0x31>; | |
| reg = <0x10b4b000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x27f>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,devfreq-cdev { | |
| compatible = "qcom,devfreq-cdev"; | |
| qcom,devfreq = <0x179>; | |
| }; | |
| qcom,mdss_dsi_phy0@ae94900 { | |
| vdda-0p9-supply = <0x42>; | |
| pll-label = "dsi_pll_5nm"; | |
| cell-index = <0x00>; | |
| #clock-cells = <0x01>; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; | |
| pll_codes_region = <0x36f>; | |
| qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
| reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; | |
| reg = <0xae94400 0xa00 0xae94900 0x400 0xae94200 0xa0>; | |
| compatible = "qcom,dsi-phy-v4.3"; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| phandle = <0x371>; | |
| label = "dsi-phy-0"; | |
| qcom,phy-supply-entries { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-max-voltage = <0x100d60>; | |
| qcom,supply-disable-load = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| qcom,supply-enable-load = <0x17e08>; | |
| }; | |
| }; | |
| }; | |
| sys-pm-vx@c320000 { | |
| reg = <0xc320000 0x400>; | |
| mbox-names = "aop"; | |
| compatible = "qcom,sys-pm-violators\0qcom,sys-pm-ravelin"; | |
| mboxes = <0x02 0x00>; | |
| }; | |
| qcom,msm-dai-tdm-sec-rx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9110>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9010>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3ce>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-sec-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9010>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3cf>; | |
| }; | |
| }; | |
| qrtr-gunyah { | |
| gunyah-label = <0x03>; | |
| shared-buffer = <0x182>; | |
| qcom,master; | |
| compatible = "qcom,qrtr-gunyah"; | |
| peer-name = <0x02>; | |
| }; | |
| qcom,smp2p_sleepstate { | |
| qcom,smem-states = <0x13c 0x00>; | |
| interrupts = <0x00 0x00>; | |
| interrupt-parent = <0x13d>; | |
| interrupt-names = "smp2p-sleepstate-in"; | |
| compatible = "qcom,smp2p-sleepstate"; | |
| }; | |
| tpdm@12860000 { | |
| coresight-name = "coresight-tpdm-actpm"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x12860000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x42>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x241>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x6e>; | |
| phandle = <0xb1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| display_gpio_regulator@0 { | |
| enable-active-high; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-boot-on; | |
| regulator-name = "display_panel_avdd"; | |
| regulator-enable-ramp-delay = <0xe9>; | |
| compatible = "qti-regulator-fixed"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| pinctrl-names = "default"; | |
| gpio = <0x126 0x28 0x00>; | |
| phandle = <0x452>; | |
| qcom,proxy-consumer-enable; | |
| pinctrl-0 = <0x455>; | |
| proxy-supply = <0x452>; | |
| }; | |
| qcom,qup_uart@a88000 { | |
| qcom,wrapper-core = <0x1c0>; | |
| clocks = <0x24 0x4e 0x24 0x56 0x24 0x57>; | |
| reg-names = "se_phys"; | |
| reg = <0xa88000 0x4000>; | |
| interrupts = <0x00 0x163 0x04>; | |
| status = "ok"; | |
| pinctrl-1 = <0x1bf>; | |
| compatible = "qcom,msm-geni-console"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x33c>; | |
| pinctrl-0 = <0x1bd 0x1be>; | |
| }; | |
| qfprom@0 { | |
| nvmem-cells = <0x150 0x151 0x152 0x33>; | |
| compatible = "qcom,qfprom-sys"; | |
| phandle = <0x2d3>; | |
| nvmem-cell-names = "feat_conf12\0feat_conf13\0boot_config\0gpu_speed_bin"; | |
| }; | |
| qcom,hyp-core-ctl { | |
| qcom,unisolate-timeout-ms = <0x2ee0>; | |
| qcom,populate-cpus; | |
| status = "ok"; | |
| compatible = "qcom,hyp-core-ctl"; | |
| phandle = <0x2e2>; | |
| }; | |
| csr@10001000 { | |
| qcom,blk-size = <0x01>; | |
| coresight-name = "coresight-csr"; | |
| qcom,usb-bam-support; | |
| qcom,perflsheot-set-support; | |
| reg-names = "csr-base"; | |
| reg = <0x10001000 0x1000>; | |
| qcom,hwctrl-set-support; | |
| compatible = "qcom,coresight-csr"; | |
| phandle = <0x10d>; | |
| qcom,set-byte-cntr-support; | |
| }; | |
| tpdm@10003000 { | |
| coresight-name = "coresight-tpdm-dcc"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10003000 0x1000>; | |
| qcom,hw-enable-check; | |
| compatible = "arm,primecell"; | |
| atid = <0x41>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x23d>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x66>; | |
| phandle = <0xe8>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| thermal-zones { | |
| phandle = <0x2e0>; | |
| zeroc-1-step { | |
| thermal-sensors = <0x17a 0x80>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x01>; | |
| type = "passive"; | |
| hysteresis = <0x01>; | |
| }; | |
| cold-trip { | |
| temperature = <0x01>; | |
| type = "passive"; | |
| hysteresis = <0x01>; | |
| phandle = <0x17f>; | |
| }; | |
| }; | |
| cooling-maps { | |
| wcss_cx_vdd_cdev { | |
| trip = <0x17f>; | |
| cooling-device = <0x17e 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-0 { | |
| thermal-sensors = <0x165 0x09>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| cpu6-emerg0-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x172>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu10_cdev { | |
| trip = <0x172>; | |
| cooling-device = <0x173 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| mdmss-2 { | |
| thermal-sensors = <0x17a 0x04>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-2 { | |
| thermal-sensors = <0x165 0x0b>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| cpu7-emerg0-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x175>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu12_cdev { | |
| trip = <0x175>; | |
| cooling-device = <0x176 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| video { | |
| thermal-sensors = <0x165 0x0f>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-1 { | |
| thermal-sensors = <0x165 0x0a>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| cpu6-emerg1-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x174>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu11_cdev { | |
| trip = <0x174>; | |
| cooling-device = <0x173 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cx-pe { | |
| thermal-sensors = <0x180>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| cx-pe-config1 { | |
| temperature = <0x01>; | |
| type = "passive"; | |
| hysteresis = <0x01>; | |
| phandle = <0x181>; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu_cdev { | |
| trip = <0x181>; | |
| cooling-device = <0x179 0x03 0x03>; | |
| }; | |
| }; | |
| }; | |
| mdmss-0 { | |
| thermal-sensors = <0x17a 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| gpuss { | |
| thermal-sensors = <0x165 0x0d>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| tj_cfg { | |
| temperature = <0x17318>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| phandle = <0x178>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu_cdev { | |
| trip = <0x178>; | |
| cooling-device = <0x179 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| pa { | |
| thermal-sensors = <0x164 0x00>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| pm7250b-ibat-lvl0 { | |
| thermal-sensors = <0x40b 0x00>; | |
| polling-delay = <0x00>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| ibat-lvl0 { | |
| temperature = <0xfa0>; | |
| type = "passive"; | |
| hysteresis = <0xc8>; | |
| phandle = <0x446>; | |
| }; | |
| }; | |
| }; | |
| sys-therm-3 { | |
| thermal-sensors = <0x403 0x14d>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| cpu-0-4 { | |
| thermal-sensors = <0x165 0x05>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| cpu4-emerg-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x16e>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu04_cdev { | |
| trip = <0x16e>; | |
| cooling-device = <0x16f 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pm7250b-bcl-lvl2 { | |
| thermal-sensors = <0x40b 0x07>; | |
| polling-delay = <0x00>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x64>; | |
| trips { | |
| b-bcl-lvl2 { | |
| temperature = <0x01>; | |
| type = "passive"; | |
| hysteresis = <0x01>; | |
| phandle = <0x410>; | |
| }; | |
| thermal-hal-trip { | |
| temperature = <0x64>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| thermal-engine-trip { | |
| temperature = <0x64>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vbat_gpu2 { | |
| trip = <0x410>; | |
| cooling-device = <0x179 0x03 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| sub1_mcg_fr1_cc { | |
| thermal-sensors = <0x164 0x35>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| sub1-lte-cc { | |
| thermal-sensors = <0x164 0x34>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| sdr1-pa { | |
| thermal-sensors = <0x164 0x41>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| mdmss-1 { | |
| thermal-sensors = <0x17a 0x03>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| cpu-0-0 { | |
| thermal-sensors = <0x165 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| cpu0-emerg-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x166>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu00_cdev { | |
| trip = <0x166>; | |
| cooling-device = <0x167 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pm7250b-bcl-lvl0 { | |
| thermal-sensors = <0x40b 0x05>; | |
| polling-delay = <0x00>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x64>; | |
| trips { | |
| b-bcl-lvl0 { | |
| temperature = <0x01>; | |
| type = "passive"; | |
| hysteresis = <0x01>; | |
| phandle = <0x40e>; | |
| }; | |
| thermal-hal-trip { | |
| temperature = <0x64>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| thermal-engine-trip { | |
| temperature = <0x64>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vbat_nr0 { | |
| trip = <0x40e>; | |
| cooling-device = <0x35a 0x06 0x06>; | |
| }; | |
| vbat_cpu_5 { | |
| trip = <0x40e>; | |
| cooling-device = <0x171 0x01 0x01>; | |
| }; | |
| vbat_cpu_6 { | |
| trip = <0x40e>; | |
| cooling-device = <0x173 0x01 0x01>; | |
| }; | |
| vbat_gpu0 { | |
| trip = <0x40e>; | |
| cooling-device = <0x179 0x02 0x02>; | |
| }; | |
| vbat_cpu_4 { | |
| trip = <0x40e>; | |
| cooling-device = <0x16f 0x01 0x01>; | |
| }; | |
| vbat_nr0_scg { | |
| trip = <0x40e>; | |
| cooling-device = <0x35c 0x03 0x03>; | |
| }; | |
| vbat_lte0 { | |
| trip = <0x40e>; | |
| cooling-device = <0x358 0x08 0x08>; | |
| }; | |
| }; | |
| }; | |
| pm6450_tz { | |
| thermal-sensors = <0x3ff>; | |
| polling-delay = <0x00>; | |
| phandle = <0x42e>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x64>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| phandle = <0x417>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| phandle = <0x42f>; | |
| }; | |
| }; | |
| cooling-maps { | |
| pm6450_cpu1 { | |
| trip = <0x417>; | |
| cooling-device = <0x169 0x01 0x01>; | |
| }; | |
| pm6450_nr { | |
| trip = <0x417>; | |
| cooling-device = <0x35c 0xff 0xff>; | |
| }; | |
| pm6450_lte { | |
| trip = <0x417>; | |
| cooling-device = <0x358 0xff 0xff>; | |
| }; | |
| pm6450_cpu5 { | |
| trip = <0x417>; | |
| cooling-device = <0x171 0x01 0x01>; | |
| }; | |
| pm6450_cpu3 { | |
| trip = <0x417>; | |
| cooling-device = <0x16d 0x01 0x01>; | |
| }; | |
| pm6450_cpu2 { | |
| trip = <0x417>; | |
| cooling-device = <0x16b 0x01 0x01>; | |
| }; | |
| pm6450_gpu { | |
| trip = <0x417>; | |
| cooling-device = <0x179 0x03 0xffffffff>; | |
| }; | |
| pm6450_cpu0 { | |
| trip = <0x417>; | |
| cooling-device = <0x167 0x01 0x01>; | |
| }; | |
| pm6450_cpu6_7 { | |
| trip = <0x417>; | |
| cooling-device = <0x34e 0x01 0x01>; | |
| }; | |
| pm6450_cpu4 { | |
| trip = <0x417>; | |
| cooling-device = <0x16f 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| sub1_scg_fr1_cc { | |
| thermal-sensors = <0x164 0x37>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| lte-cc { | |
| thermal-sensors = <0x164 0x43>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| bcl-warn { | |
| thermal-sensors = <0x164 0x1f>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| ddr { | |
| thermal-sensors = <0x17a 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| ddr0-config { | |
| temperature = <0x15f90>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| phandle = <0x17b>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| ddr_cdev { | |
| trip = <0x17b>; | |
| cooling-device = <0x17c 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-0-3 { | |
| thermal-sensors = <0x165 0x04>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| cpu3-emerg-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x16c>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu03_cdev { | |
| trip = <0x16c>; | |
| cooling-device = <0x16d 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| socd { | |
| thermal-sensors = <0x40c>; | |
| polling-delay = <0x00>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x64>; | |
| trips { | |
| socd-trip { | |
| temperature = <0x61>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| phandle = <0x40d>; | |
| }; | |
| thermal-hal-trip { | |
| temperature = <0x64>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| thermal-engine-trip { | |
| temperature = <0x64>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| }; | |
| cooling-maps { | |
| socd_gpu0 { | |
| trip = <0x40d>; | |
| cooling-device = <0x179 0x02 0x02>; | |
| }; | |
| socd_cpu_6_7 { | |
| trip = <0x40d>; | |
| cooling-device = <0x34e 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| sys-therm-9 { | |
| thermal-sensors = <0x411 0x4f>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| zeroc-0-step { | |
| thermal-sensors = <0x165 0x80>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x01>; | |
| type = "passive"; | |
| hysteresis = <0x01>; | |
| }; | |
| cold-trip { | |
| temperature = <0x01>; | |
| type = "passive"; | |
| hysteresis = <0x01>; | |
| phandle = <0x17d>; | |
| }; | |
| }; | |
| cooling-maps { | |
| wcss_cx_vdd_cdev { | |
| trip = <0x17d>; | |
| cooling-device = <0x17e 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| sys-therm-11 { | |
| thermal-sensors = <0x403 0x14c>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| pm7250b-bcl-lvl1 { | |
| thermal-sensors = <0x40b 0x06>; | |
| polling-delay = <0x00>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x64>; | |
| trips { | |
| b-bcl-lvl1 { | |
| temperature = <0x01>; | |
| type = "passive"; | |
| hysteresis = <0x01>; | |
| phandle = <0x40f>; | |
| }; | |
| thermal-hal-trip { | |
| temperature = <0x64>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| thermal-engine-trip { | |
| temperature = <0x64>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vbat_nr1 { | |
| trip = <0x40f>; | |
| cooling-device = <0x35a 0xff 0xff>; | |
| }; | |
| vbat_cpu_7 { | |
| trip = <0x40f>; | |
| cooling-device = <0x176 0x01 0x01>; | |
| }; | |
| vbat_nr1_scg { | |
| trip = <0x40f>; | |
| cooling-device = <0x35c 0xff 0xff>; | |
| }; | |
| vbat_gpu1 { | |
| trip = <0x40f>; | |
| cooling-device = <0x179 0x04 0x04>; | |
| }; | |
| vbat_lte1 { | |
| trip = <0x40f>; | |
| cooling-device = <0x358 0xff 0xff>; | |
| }; | |
| }; | |
| }; | |
| cpu-0-1 { | |
| thermal-sensors = <0x165 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| cpu1-emerg-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x168>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu01_cdev { | |
| trip = <0x168>; | |
| cooling-device = <0x169 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-3 { | |
| thermal-sensors = <0x165 0x0c>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| trips { | |
| cpu7-emerg1-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x177>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu13_cdev { | |
| trip = <0x177>; | |
| cooling-device = <0x176 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| sys-therm-5 { | |
| thermal-sensors = <0x403 0x46>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| modem-cfg { | |
| thermal-sensors = <0x164 0x42>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| pa1 { | |
| thermal-sensors = <0x164 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| pm7250b-ibat-lvl1 { | |
| thermal-sensors = <0x40b 0x01>; | |
| polling-delay = <0x00>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| ibat-lvl1 { | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| hysteresis = <0xc8>; | |
| phandle = <0x447>; | |
| }; | |
| }; | |
| }; | |
| sub1-modem-cfg { | |
| thermal-sensors = <0x164 0x33>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| camera { | |
| thermal-sensors = <0x165 0x0e>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| sdr1 { | |
| thermal-sensors = <0x164 0x2d>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| sys-therm-1 { | |
| thermal-sensors = <0x403 0x14a>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| scg-fr1-cc { | |
| thermal-sensors = <0x164 0x46>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| sdr0 { | |
| thermal-sensors = <0x164 0x26>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| sdr0-pa { | |
| thermal-sensors = <0x164 0x40>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| aoss-1 { | |
| thermal-sensors = <0x17a 0x00>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| cpuss-0 { | |
| thermal-sensors = <0x165 0x07>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| cpu-0-5 { | |
| thermal-sensors = <0x165 0x06>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| cpu5-emerg-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x170>; | |
| }; | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu05_cdev { | |
| trip = <0x170>; | |
| cooling-device = <0x171 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| sys-therm-7 { | |
| thermal-sensors = <0x411 0x4d>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| pm8010e_tz { | |
| thermal-sensors = <0x402>; | |
| polling-delay = <0x00>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x64>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| type = "critical"; | |
| hysteresis = <0x00>; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| }; | |
| }; | |
| }; | |
| mcg-fr1-cc { | |
| thermal-sensors = <0x164 0x44>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| aoss-0 { | |
| thermal-sensors = <0x165 0x00>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| pm7250b_tz { | |
| thermal-sensors = <0x40a>; | |
| polling-delay = <0x00>; | |
| phandle = <0x442>; | |
| thermal-governor = "step_wise"; | |
| polling-delay-passive = <0x64>; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| phandle = <0x445>; | |
| }; | |
| trip0 { | |
| temperature = <0x15f90>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| phandle = <0x443>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x00>; | |
| phandle = <0x444>; | |
| }; | |
| }; | |
| }; | |
| sys-therm-6 { | |
| thermal-sensors = <0x403 0x44>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| mdmss-3 { | |
| thermal-sensors = <0x17a 0x05>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| cpu-0-2 { | |
| thermal-sensors = <0x165 0x03>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| cpu2-emerg-cfg { | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| hysteresis = <0x2710>; | |
| phandle = <0x16a>; | |
| }; | |
| thermal-hal-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu02_cdev { | |
| trip = <0x16a>; | |
| cooling-device = <0x16b 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| sys-therm-4 { | |
| thermal-sensors = <0x403 0x45>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| active-config1 { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| }; | |
| }; | |
| cpuss-1 { | |
| thermal-sensors = <0x165 0x08>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| thermal-engine-config { | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| hysteresis = <0x3e8>; | |
| }; | |
| reset-mon-cfg { | |
| temperature = <0x1c138>; | |
| type = "passive"; | |
| hysteresis = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@10902000 { | |
| coresight-name = "coresight-funnel-gfx_dl"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10902000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x24c>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8a>; | |
| phandle = <0xd5>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x89>; | |
| phandle = <0x57>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm_gsi { | |
| compatible = "qcom,msm_gsi"; | |
| }; | |
| bt_wcn3990 { | |
| qcom,bt-vdd-core-supply = <0x128>; | |
| qcom,bt-sw-ctrl-gpio = <0x126 0x38 0x00>; | |
| qcom,bt-vdd-xtal-config = <0x19f0a0 0x1cfde0 0x01 0x00>; | |
| qcom,bt-vdd-pa-supply = <0x129>; | |
| qcom,bt-vdd-xtal-supply = <0x43>; | |
| qcom,bt-vdd-pa-config = <0x2dc6c0 0x328980 0x01 0x00>; | |
| qcom,bt-vdd-io-supply = <0x127>; | |
| compatible = "qcom,wcn3990"; | |
| qcom,bt-vdd-io-config = <0x19f0a0 0x1cfde0 0x01 0x00>; | |
| phandle = <0x2b4>; | |
| qcom,bt-vdd-core-config = <0x13e5c0 0x13e5c0 0x01 0x00>; | |
| }; | |
| tgu@10b0e000 { | |
| tgu-conditions = <0x04>; | |
| tgu-steps = <0x03>; | |
| coresight-name = "coresight-tgu-ipcb"; | |
| clocks = <0x31>; | |
| reg-names = "tgu-base"; | |
| reg = <0x10b0e000 0x1000>; | |
| compatible = "arm,primecell"; | |
| tgu-regs = <0x04>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x28f>; | |
| arm,primecell-periphid = <0xbb999>; | |
| tgu-timer-counters = <0x08>; | |
| }; | |
| cti@10d11000 { | |
| coresight-name = "coresight-cti-ddrss_shrm2"; | |
| clocks = <0x31>; | |
| reg = <0x10d11000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x28a>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| tpdm@10d01000 { | |
| coresight-name = "coresight-tpdm-shrm"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x10d01000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x97>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x56>; | |
| phandle = <0x91>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10850000 { | |
| coresight-name = "coresight-tpdm-pimem"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10850000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x236>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5f>; | |
| phandle = <0xc1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| bt_qca6490 { | |
| qcom,bt-vdd-rfa2-supply = <0x1ee>; | |
| qcom,bt-vdd-aon-supply = <0x1ed>; | |
| qcom,bt-vdd-rfa2-config = <0x1312d0 0x14a140 0x00 0x01>; | |
| qcom,bt-sw-ctrl-gpio = <0x126 0x38 0x00>; | |
| qcom,wl-reset-gpio = <0x126 0x2b 0x00>; | |
| qcom,bt-vdd-aon-config = <0xcf850 0x111700 0x00 0x01>; | |
| qcom,bt-vdd-rfa1-config = <0x1c5200 0x1f20c0 0x00 0x01>; | |
| qcom,bt-reset-gpio = <0x126 0x27 0x00>; | |
| status = "disabled"; | |
| qcom,bt-vdd-io-supply = <0x127>; | |
| compatible = "qcom,qca6490"; | |
| pinctrl-names = "default"; | |
| qcom,bt-vdd-dig-config = <0xc3500 0x111700 0x00 0x01>; | |
| qcom,bt-vdd-io-config = <0x1b7740 0x1b7740 0x00 0x01>; | |
| phandle = <0x349>; | |
| pinctrl-0 = <0x1f0>; | |
| qcom,bt-vdd-dig-supply = <0x1ed>; | |
| }; | |
| ddr-freq-table { | |
| phandle = <0x141>; | |
| ddr4 { | |
| qcom,freq-tbl = <0x858b8 0xbb800 0xf84a8 0x14a780 0x17ba38 0x1a0fe0 0x1febe0>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr5 { | |
| qcom,freq-tbl = <0x858b8 0xbb800 0x17ba38 0x1a0fe0 0x1febe0 0x29bf80 0x30c460>; | |
| qcom,ddr-type = <0x08>; | |
| }; | |
| }; | |
| qcom,pcie@1c00000 { | |
| qcom,aux-clk-freq = <0x14>; | |
| linux,pci-domain = <0x00>; | |
| qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>; | |
| qcom,slv-addr-space-size = <0x4000000>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0xffffffff>; | |
| interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0x8c 0x04 0x00 0x00 0x00 0x01 0x01 0x00 0x95 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x96 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x97 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x98 0x04>; | |
| qcom,phy-status-bit = <0x06>; | |
| qcom,dbi-debug-reg = <0x104 0x110 0x80 0x204 0x730 0x734 0x738 0x73c>; | |
| iommu-map = <0x00 0x2f 0x1400 0x01 0x100 0x2f 0x1401 0x01>; | |
| qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x40 0x40 0x5f5e100>; | |
| qcom,drv-l1ss-timeout-us = <0x1388>; | |
| qcom,drv-supported; | |
| cell-index = <0x00>; | |
| resets = <0x24 0x03 0x24 0x06>; | |
| vreg-1p8-supply = <0x47>; | |
| qcom,smmu-sid-base = <0x1400>; | |
| qcom,phy-sequence = <0x240 0x03 0x00 0x94 0x08 0x00 0x154 0x34 0x00 0x16c 0x08 0x00 0x58 0x0f 0x00 0xa4 0x42 0x00 0x110 0x24 0x00 0x11c 0x03 0x00 0x118 0xb4 0x00 0x10c 0x02 0x00 0x1bc 0x11 0x00 0xbc 0x82 0x00 0xd4 0x03 0x00 0xd0 0x55 0x00 0xcc 0x55 0x00 0xb0 0x1a 0x00 0xac 0x0a 0x00 0xc4 0x68 0x00 0xe0 0x02 0x00 0xdc 0xaa 0x00 0xd8 0xab 0x00 0xb8 0x34 0x00 0xb4 0x14 0x00 0x158 0x01 0x00 0x74 0x06 0x00 0x7c 0x16 0x00 0x84 0x36 0x00 0x78 0x06 0x00 0x80 0x16 0x00 0x88 0x36 0x00 0x1b0 0x1e 0x00 0x1ac 0xca 0x00 0x1b8 0x18 0x00 0x1b4 0xa2 0x00 0x50 0x07 0x00 0x10 0x01 0x00 0x1c 0x31 0x00 0x20 0x01 0x00 0x24 0xde 0x00 0x28 0x07 0x00 0x30 0x4c 0x00 0x34 0x06 0x00 0xee4 0x20 0x00 0xe84 0x75 0x00 0xe90 0x3f 0x00 0x115c 0x7f 0x00 0x1160 0xff 0x00 0x1164 0xbf 0x00 0x1168 0x3f 0x00 0x116c 0xd8 0x00 0x1170 0xdc 0x00 0x1174 0xdc 0x00 0x1178 0x5c 0x00 0x117c 0x34 0x00 0x1180 0xa6 0x00 0x1190 0x34 0x00 0x1194 0x38 0x00 0x10d8 0x0f 0x00 0xe3c 0x12 0x00 0xe40 0x01 0x00 0x10dc 0x00 0x00 0x104c 0x08 0x00 0x1050 0x08 0x00 0x1044 0xf0 0x00 0x11a4 0x38 0x00 0x10cc 0xf0 0x00 0x10f4 0x07 0x00 0x1008 0x09 0x00 0x1014 0x05 0x00 0x694 0x00 0x00 0x654 0x00 0x00 0x6a8 0x0f 0x00 0x48 0x90 0x00 0x620 0xc1 0x00 0x388 0x77 0x00 0x398 0x0b 0x00 0x2dc 0x05 0x00 0x200 0x00 0x00 0x244 0x03 0x00>; | |
| qcom,vreg-1p8-voltage-level = <0x124f80 0x124f80 0x3ade>; | |
| clocks = <0x24 0x2c 0x45 0x00 0x24 0x25 0x24 0x27 0x24 0x29 0x24 0x30 0x24 0x28 0x24 0x31 0x24 0x2a 0x24 0x15 0x24 0x08 0x24 0x12 0x24 0x2d 0x24 0x2e 0x24 0x3a 0x131>; | |
| qcom,l1-2-th-value = <0x96>; | |
| #size-cells = <0x02>; | |
| ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0x3d00000>; | |
| reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf"; | |
| vreg-cx-supply = <0x124>; | |
| #address-cells = <0x03>; | |
| perst-gpio = <0x126 0x20 0x00>; | |
| qcom,vreg-cx-voltage-level = <0xffff 0x100 0x00>; | |
| msi-parent = <0x1e3>; | |
| qcom,phy-status-offset = <0x214>; | |
| reg = <0x1c00000 0x3000 0x1c06000 0x2000 0x60000000 0xf1d 0x60000f20 0xa8 0x60001000 0x1000 0x60100000 0x100000>; | |
| reset-names = "pcie_0_core_reset\0pcie_0_phy_reset"; | |
| wake-gpio = <0x126 0x1f 0x00>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04>; | |
| interrupt-parent = <0x1e2>; | |
| qcom,pcie-phy-ver = <0x6b>; | |
| qcom,boot-option = <0x01>; | |
| interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; | |
| interconnect-names = "icc_path"; | |
| status = "disabled"; | |
| interconnects = <0x2c 0x2f 0x29 0x200>; | |
| #interrupt-cells = <0x01>; | |
| pinctrl-1 = <0x1e4 0x1e7 0x1e6>; | |
| gdsc-vdd-supply = <0x1e8>; | |
| dma-coherent; | |
| compatible = "qcom,pci-msm"; | |
| pinctrl-names = "default\0sleep"; | |
| qcom,num-parf-testbus-sel = <0xb9>; | |
| clock-names = "pcie_0_pipe_clk\0pcie_0_ref_clk_src\0pcie_0_aux_clk\0pcie_0_cfg_ahb_clk\0pcie_0_mstr_axi_clk\0pcie_0_slv_axi_clk\0pcie_0_ldo\0pcie_0_slv_q2a_axi_clk\0pcie_phy_refgen_clk\0pcie_ddrss_sf_tbu_clk\0pcie_aggre_noc_0_axi_clk\0pcie_cfg_noc_pcie_anoc_ahb_clk\0pcie_pipe_clk_mux\0pcie_0_pipe_div2_clk\0pcie_qmip_pcie_ahb_clk\0pcie_pipe_clk_ext_src"; | |
| qcom,vreg-mx-voltage-level = <0xffff 0x100 0x00>; | |
| max-clock-frequency-hz = <0x00 0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00 0x00 0x00 0x00>; | |
| phandle = <0x1e2>; | |
| qcom,l1-2-th-scale = <0x02>; | |
| pinctrl-0 = <0x1e4 0x1e5 0x1e6>; | |
| qcom,ep-latency = <0x0a>; | |
| qcom,phy-debug-reg = <0x68 0x140 0x144 0x148 0x14c 0x150 0x160 0x178 0xed0 0xedc 0xf34 0xf38 0xf3c 0xf40 0xf44 0xf48 0xf4c 0xf50 0xf54 0xf58 0x11e8 0xa00 0xa04 0xa08 0xa0c 0xa10 0xa14 0xa18 0xc20 0x214 0x218 0x21c 0x220 0x224 0x228 0x22c 0x230 0x234 0x238 0x23c 0x600 0x604 0x1204 0x1210>; | |
| vreg-mx-supply = <0x125>; | |
| qcom,vreg-0p9-voltage-level = <0xd6d80 0xd6d80 0xb72a>; | |
| vreg-0p9-supply = <0x42>; | |
| qcom,config-recovery; | |
| qcom,phy-power-down-offset = <0x240>; | |
| pcie0_rp { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x05>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x346>; | |
| cnss_pci0 { | |
| #size-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| qcom,iommu-group = <0x1e9>; | |
| memory-region = <0x1ea>; | |
| phandle = <0x347>; | |
| cnss_pci_iommu_group0 { | |
| qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; | |
| qcom,iommu-pagetable = "coherent"; | |
| qcom,iommu-faults = "stall-disable\0HUPCF\0no-CFRE\0non-fatal"; | |
| phandle = <0x1e9>; | |
| qcom,iommu-dma = "fastmap"; | |
| qcom,iommu-msi-size = <0x1000>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@128a0000 { | |
| coresight-name = "coresight-tpdm-llm-silver"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x128a0000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x42>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x240>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x6d>; | |
| phandle = <0xb0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10b0c000 { | |
| coresight-name = "coresight-tpdm-swao-prio-3"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10b0c000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x22c>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x52>; | |
| phandle = <0xfb>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10d21000 { | |
| coresight-name = "coresight-cti-ddr_ch01_dl_cti_0"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10d21000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x275>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,msm-dai-tdm-quin-tx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9141>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9041>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3dc>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-quin-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9041>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3dd>; | |
| }; | |
| }; | |
| qcom,gdsc@aaf8124 { | |
| regulator-name = "video_cc_mvs1c_gdsc"; | |
| reg = <0xaaf8124 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x32d>; | |
| qcom,retain-regs; | |
| }; | |
| tpda@10b08000 { | |
| coresight-name = "coresight-tpda-aoss"; | |
| qcom,dsb-elem-size = <0x04 0x20>; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x10b08000 0x1000>; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x00 0x40 0x01 0x40 0x02 0x40 0x03 0x40>; | |
| qcom,tpda-atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x266>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xfd>; | |
| phandle = <0xff>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0xfb>; | |
| phandle = <0x52>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0xfa>; | |
| phandle = <0x51>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xf8>; | |
| phandle = <0x4f>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xfc>; | |
| phandle = <0x53>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xf9>; | |
| phandle = <0x50>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@ad15120 { | |
| regulator-name = "cam_cc_titan_top_gdsc"; | |
| reg = <0xad15120 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x314>; | |
| qcom,retain-regs; | |
| }; | |
| qcom,guestvm_loader@e0b00000 { | |
| compatible = "qcom,guestvm-loader"; | |
| qcom,vmid = <0x2d>; | |
| memory-region = <0x186>; | |
| qcom,firmware-name = "trustedvm"; | |
| qcom,pas-id = <0x1c>; | |
| }; | |
| spi@a80000 { | |
| dmas = <0x1c4 0x00 0x00 0x01 0x40 0x00 0x1c4 0x01 0x00 0x01 0x40 0x00>; | |
| qcom,wrapper-core = <0x1c0>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x4a 0x24 0x56 0x24 0x57>; | |
| #size-cells = <0x00>; | |
| reg-names = "se_phys"; | |
| #address-cells = <0x01>; | |
| spi-max-frequency = <0x2faf080>; | |
| reg = <0xa80000 0x4000>; | |
| interrupts = <0x00 0x161 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1c9>; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x33e>; | |
| pinctrl-0 = <0x1c5 0x1c6 0x1c7 0x1c8>; | |
| }; | |
| qcom,msm-pcm-dtmf { | |
| compatible = "qcom,msm-pcm-dtmf"; | |
| phandle = <0x38b>; | |
| }; | |
| tpdm@10b0a000 { | |
| coresight-name = "coresight-tpdm-swao-prio-1"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10b0a000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x22a>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x50>; | |
| phandle = <0xf9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| timer@17420000 { | |
| #size-cells = <0x01>; | |
| ranges; | |
| #address-cells = <0x01>; | |
| reg = <0x17420000 0x1000>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv7-timer-mem"; | |
| phandle = <0x2b8>; | |
| frame@1742d000 { | |
| frame-number = <0x06>; | |
| reg = <0x1742d000 0x1000>; | |
| interrupts = <0x00 0x0e 0x04>; | |
| status = "disabled"; | |
| }; | |
| frame@1742b000 { | |
| frame-number = <0x05>; | |
| reg = <0x1742b000 0x1000>; | |
| interrupts = <0x00 0x0d 0x04>; | |
| status = "disabled"; | |
| }; | |
| frame@17423000 { | |
| frame-number = <0x01>; | |
| reg = <0x17423000 0x1000>; | |
| interrupts = <0x00 0x09 0x04>; | |
| status = "disabled"; | |
| }; | |
| frame@17429000 { | |
| frame-number = <0x04>; | |
| reg = <0x17429000 0x1000>; | |
| interrupts = <0x00 0x0c 0x04>; | |
| status = "disabled"; | |
| }; | |
| frame@17421000 { | |
| frame-number = <0x00>; | |
| reg = <0x17421000 0x1000 0x17422000 0x1000>; | |
| interrupts = <0x00 0x08 0x04 0x00 0x06 0x04>; | |
| }; | |
| frame@17427000 { | |
| frame-number = <0x03>; | |
| reg = <0x17427000 0x1000>; | |
| interrupts = <0x00 0x0b 0x04>; | |
| status = "disabled"; | |
| }; | |
| frame@17425000 { | |
| frame-number = <0x02>; | |
| reg = <0x17425000 0x1000>; | |
| interrupts = <0x00 0x0a 0x04>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| qcom,pcie2-gdsc@19d004 { | |
| regulator-name = "gcc_pcie_2_gdsc"; | |
| reg = <0x19d004 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x31d>; | |
| qcom,retain-regs; | |
| qcom,collapse-vote = <0x18b 0x02>; | |
| }; | |
| wsa_core_clk { | |
| qcom,codec-ext-clk-src = <0x03>; | |
| #clock-cells = <0x01>; | |
| qcom,codec-lpass-clk-id = <0x309>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x472>; | |
| }; | |
| qcom,msm-pcm-hostless { | |
| compatible = "qcom,msm-pcm-hostless"; | |
| phandle = <0x3bf>; | |
| }; | |
| interconnect@1680000 { | |
| qcom,bcm-voter-names = "hlos"; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x1680000 0x19080>; | |
| compatible = "qcom,ravelin-system_noc"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x191>; | |
| }; | |
| qcom,gdsc@18d07c { | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc"; | |
| reg = <0x18d07c 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x322>; | |
| }; | |
| replicator@10046000 { | |
| coresight-name = "coresight-replicator_qdss"; | |
| clocks = <0x31>; | |
| reg-names = "replicator-base"; | |
| reg = <0x10046000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x26b>; | |
| arm,primecell-periphid = <0xbb909>; | |
| out-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@0 { | |
| endpoint { | |
| remote-endpoint = <0x109>; | |
| phandle = <0x10a>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x108>; | |
| phandle = <0x106>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-q6-afe-loopback-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x3e6>; | |
| qcom,msm-dai-q6-dev-id = <0x6001>; | |
| }; | |
| qcom,msm-pcm-voice { | |
| qcom,destroy-cvd; | |
| compatible = "qcom,msm-pcm-voice"; | |
| phandle = <0x383>; | |
| }; | |
| qcom,vidc@aa00000 { | |
| qcom,reg-presets = <0xb0080 0x00 0x03>; | |
| resets = <0x24 0x1d 0x24 0x1e>; | |
| venus-supply = <0x31f>; | |
| clocks = <0x24 0x87 0x24 0x7e 0x24 0x81 0x24 0x7d 0x24 0x80 0x24 0x82>; | |
| #size-cells = <0x01>; | |
| qcom,bus-range-kbps = <0x3e8 0x3e8 0x3e8 0x632ea0>; | |
| #address-cells = <0x01>; | |
| qcom,clock-configs = <0x00 0x00 0x00 0x00 0x00 0x01>; | |
| clock-ids = <0x87 0x7e 0x81 0x7d 0x80 0x82>; | |
| pas-id = <0x09>; | |
| reg = <0xaa00000 0xf0000>; | |
| reset-names = "video_axi_reset\0video_core_reset"; | |
| interrupts = <0x00 0xae 0x04>; | |
| interconnect-names = "venus-cnoc\0venus-ddr"; | |
| vidc,firmware-name = "venus_v7"; | |
| status = "okay"; | |
| interconnects = <0x25 0x02 0x3d 0x227 0x2d1 0x2a 0x29 0x200>; | |
| compatible = "qcom,msm-vidc\0qcom,msm-vidc-ravelin\0qcom,msm-vidc-ar50lt"; | |
| memory-region = <0x209>; | |
| clock-names = "core_clk\0bus_clk\0core0_clk\0core0_bus_clk\0throttle_clk\0video_clk_src"; | |
| phandle = <0x3f8>; | |
| qcom,allowed-clock-rates = <0x7f27450 0xe4e1c00 0x15c17540 0x16e36000>; | |
| venus-core0-supply = <0x320>; | |
| com,proxy-clock-names = "core_clk\0bus_clk\0core0_clk\0core0_bus_clk\0throttle_clk\0video_clk_src"; | |
| secure_non_pixel_cb { | |
| qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x1000000 0x24800000>; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-vmid = <0x0b>; | |
| label = "venus_sec_non_pixel"; | |
| iommus = <0x2f 0x1984 0x20>; | |
| }; | |
| secure_pixel_cb { | |
| qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x500000 0xdfb00000>; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-vmid = <0x0a>; | |
| label = "venus_sec_pixel"; | |
| iommus = <0x2f 0x1983 0x00>; | |
| }; | |
| secure_bitstream_cb { | |
| qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x500000 0xdfb00000>; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-vmid = <0x09>; | |
| label = "venus_sec_bitstream"; | |
| iommus = <0x2f 0x1981 0x04>; | |
| }; | |
| non_secure_cb { | |
| qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| virtual-addr-pool = <0x25800000 0xba800000>; | |
| dma-coherent; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| label = "venus_ns"; | |
| iommus = <0x2f 0x1980 0x20>; | |
| }; | |
| }; | |
| cti@10cc2000 { | |
| coresight-name = "coresight-cti-tmess_cti_0"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10cc2000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x286>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,disp1-gdsc@15709000 { | |
| regulator-name = "disp1_cc_mdss_core_gdsc"; | |
| reg = <0x15709000 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x18a>; | |
| qcom,proxy-consumer-enable; | |
| qcom,retain-regs; | |
| proxy-supply = <0x18a>; | |
| }; | |
| qcom,msm-pri-auxpcm { | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| qcom,msm-auxpcm-interface = "primary"; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| phandle = <0x3c1>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| }; | |
| qcom,rimps@17400000 { | |
| #mbox-cells = <0x01>; | |
| #size-cells = <0x02>; | |
| #address-cells = <0x02>; | |
| reg = <0x17400000 0x10 0x17d90000 0x2000>; | |
| interrupts = <0x00 0x3e 0x04>; | |
| compatible = "qcom,rimps"; | |
| phandle = <0x12e>; | |
| }; | |
| funnel@1080d000 { | |
| coresight-name = "coresight-funnel-modem_q6_dup"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base-dummy\0funnel-base-real"; | |
| qcom,duplicate-funnel; | |
| reg = <0x1080d000 0x1000 0x1080c000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x254>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa8>; | |
| phandle = <0xa9>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xa7>; | |
| phandle = <0x72>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@ad14004 { | |
| regulator-name = "cam_cc_ife_1_gdsc"; | |
| reg = <0xad14004 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x311>; | |
| qcom,retain-regs; | |
| }; | |
| cti@10C13000 { | |
| coresight-name = "coresight-cti-sierra_a6"; | |
| clocks = <0x31>; | |
| reg = <0x10c13000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x28b>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| tpdm@10b0b000 { | |
| coresight-name = "coresight-tpdm-swao-prio-2"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10b0b000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x47>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x22b>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x51>; | |
| phandle = <0xfa>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| hwlock { | |
| syscon = <0x138 0x00 0x1000>; | |
| compatible = "qcom,tcsr-mutex"; | |
| #hwlock-cells = <0x01>; | |
| phandle = <0x13a>; | |
| }; | |
| tpda@10c4a000 { | |
| coresight-name = "coresight-tpda-dl-west"; | |
| clocks = <0x31>; | |
| reg-names = "tpda-base"; | |
| reg = <0x10c4a000 0x1000>; | |
| compatible = "arm,primecell"; | |
| qcom,cmb-elem-size = <0x00 0x20 0x0a 0x20>; | |
| qcom,tpda-atid = <0x65>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x25e>; | |
| arm,primecell-periphid = <0xbb969>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xdf>; | |
| phandle = <0xe0>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@10 { | |
| reg = <0x0a>; | |
| endpoint { | |
| remote-endpoint = <0xde>; | |
| phandle = <0x62>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xdd>; | |
| phandle = <0x5d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| wsa2_spkr_en2_pinctrl { | |
| status = "disabled"; | |
| pinctrl-1 = <0x2fa>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x480>; | |
| pinctrl-0 = <0x2fb>; | |
| }; | |
| qcom,msm-quat-auxpcm { | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| qcom,msm-auxpcm-interface = "quaternary"; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| phandle = <0x3c4>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| }; | |
| i2c@984000 { | |
| dmas = <0x1a1 0x00 0x01 0x03 0x40 0x02 0x1a1 0x01 0x01 0x03 0x40 0x02>; | |
| qcom,wrapper-core = <0x19a>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x40 0x24 0x54 0x24 0x55>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x984000 0x4000>; | |
| interrupts = <0x00 0x25a 0x04>; | |
| status = "ok"; | |
| pinctrl-1 = <0x1a4>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x335>; | |
| pinctrl-0 = <0x1a2 0x1a3>; | |
| qcom,i2c-touch-active = "focaltech,fts_ts"; | |
| focaltech@38 { | |
| vdd-supply = <0x2ad>; | |
| focaltech,reset-gpio = <0x126 0x0c 0x00>; | |
| pinctrl-2 = <0x308>; | |
| focaltech,max-touch-number = <0x0a>; | |
| reg = <0x38>; | |
| interrupts = <0x0d 0x2008>; | |
| interrupt-parent = <0x126>; | |
| panel = <0x454>; | |
| pinctrl-1 = <0x306 0x304>; | |
| compatible = "focaltech,fts_ts"; | |
| pinctrl-names = "pmx_ts_active\0pmx_ts_suspend\0pmx_ts_release"; | |
| focaltech,irq-gpio = <0x126 0x0d 0x2008>; | |
| pinctrl-0 = <0x302>; | |
| focaltech,display-coords = <0x00 0x00 0x438 0x4d8>; | |
| }; | |
| }; | |
| modem_diag { | |
| coresight-name = "coresight-modem-diag"; | |
| compatible = "qcom,coresight-dummy"; | |
| qcom,dummy-source; | |
| atid = <0x32>; | |
| phandle = <0x245>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x74>; | |
| phandle = <0xaa>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,smmu_sde_sec_cb { | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| qcom,iommu-faults = "non-fatal"; | |
| compatible = "qcom,smmu_sde_sec"; | |
| qcom,iommu-vmid = <0x0a>; | |
| phandle = <0x377>; | |
| iommus = <0x2f 0x801 0x00 0x2f 0xc01 0x00>; | |
| }; | |
| cti@10b00000 { | |
| coresight-name = "coresight-cti-swao_cti"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10b00000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x27c>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| lpass_stm { | |
| coresight-name = "coresight-lpass-stm"; | |
| compatible = "qcom,coresight-dummy"; | |
| qcom,dummy-source; | |
| atid = <0x19>; | |
| phandle = <0x228>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4e>; | |
| phandle = <0x86>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gpio_keys { | |
| compatible = "gpio-keys"; | |
| pinctrl-names = "default"; | |
| label = "gpio-keys"; | |
| pinctrl-0 = <0x404>; | |
| vol_up { | |
| linux,can-disable; | |
| gpios = <0x126 0x35 0x01>; | |
| gpio-key,wakeup; | |
| linux,input-type = <0x01>; | |
| linux,code = <0x73>; | |
| debounce-interval = <0x0f>; | |
| label = "volume_up"; | |
| }; | |
| }; | |
| cti@10962000 { | |
| coresight-name = "coresight-cti-gpu_cortex_m3"; | |
| clocks = <0x31>; | |
| reg = <0x10962000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x278>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,disp0-gdsc@af0b000 { | |
| regulator-name = "disp0_cc_mdss_core_int2_gdsc"; | |
| reg = <0xaf0b000 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x317>; | |
| qcom,retain-regs; | |
| }; | |
| qcom,msm-dai-q6-dp1 { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| phandle = <0x388>; | |
| qcom,msm-dai-q6-dev-id = <0x01>; | |
| }; | |
| funnel@10c73000 { | |
| coresight-name = "coresight-funnel-wpss"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10c73000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x24a>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x83>; | |
| source = <0x84>; | |
| phandle = <0xc6>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x7f>; | |
| source = <0x80>; | |
| phandle = <0xb7>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x81>; | |
| source = <0x82>; | |
| phandle = <0xb8>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x7e>; | |
| phandle = <0x7b>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x7c>; | |
| phandle = <0x79>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x7d>; | |
| phandle = <0x7a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,glink { | |
| compatible = "qcom,glink"; | |
| }; | |
| qcom,msm-pcm-afe { | |
| compatible = "qcom,msm-pcm-afe"; | |
| phandle = <0x385>; | |
| }; | |
| qcom,audio-pkt-core-platform { | |
| compatible = "qcom,audio-pkt-core-platform"; | |
| phandle = <0x3c0>; | |
| }; | |
| qcom,gpi-dma@a00000 { | |
| qcom,gpii-mask = <0x3f>; | |
| qcom,ev-factor = <0x02>; | |
| qcom,iommu-dma-addr-pool = <0x100000 0x100000>; | |
| qcom,gpi-ee-offset = <0x10000>; | |
| qcom,max-num-gpii = <0x0c>; | |
| reg-names = "gpi-top"; | |
| #dma-cells = <0x05>; | |
| reg = <0xa00000 0x60000>; | |
| interrupts = <0x00 0x117 0x04 0x00 0x118 0x04 0x00 0x119 0x04 0x00 0x11a 0x04 0x00 0x11b 0x04 0x00 0x11c 0x04 0x00 0x125 0x04 0x00 0x126 0x04 0x00 0x127 0x04 0x00 0x128 0x04 0x00 0x129 0x04 0x00 0x12a 0x04>; | |
| status = "ok"; | |
| dma-coherent; | |
| compatible = "qcom,gpi-dma"; | |
| phandle = <0x1c4>; | |
| iommus = <0x2f 0x416 0x00>; | |
| }; | |
| tpdm@10c23000 { | |
| coresight-name = "coresight-tpdm-emmc"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10c23000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x233>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5c>; | |
| phandle = <0xe2>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@10846000 { | |
| coresight-name = "coresight-funnel-lpass"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10846000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x24d>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8c>; | |
| phandle = <0xe3>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8b>; | |
| phandle = <0x4c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cx_rdpm_pe@635000 { | |
| reg = <0x635000 0x1000>; | |
| interrupts = <0x00 0xf3 0x04>; | |
| compatible = "qcom,policy-engine"; | |
| phandle = <0x180>; | |
| #thermal-sensor-cells = <0x00>; | |
| }; | |
| sdhci@8804000 { | |
| vdd-io-supply = <0x2ab>; | |
| vdd-supply = <0x2a8>; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; | |
| qcom,dll-hsr-list = <0x7642c 0x00 0x10 0x2c010800 0x80040868>; | |
| vdd-en-dis-supply = <0x2b2>; | |
| clocks = <0x24 0x5d 0x24 0x5e>; | |
| qcom,vdd-current-level = <0x00 0xc3500>; | |
| reg-names = "hc"; | |
| no-sdio; | |
| reg = <0x8804000 0x1000>; | |
| interrupts = <0x00 0xcf 0x04 0x00 0xdf 0x04>; | |
| qcom,vdd-voltage-level = <0x2d2a80 0x2d2a80>; | |
| interrupt-names = "hc_irq\0pwr_irq"; | |
| bus-width = <0x04>; | |
| interconnect-names = "sdhc-ddr\0cpu-sdhc"; | |
| vdd-io-en-dis-supply = <0x2b3>; | |
| no-mmc; | |
| status = "ok"; | |
| cd-gpios = <0x126 0x65 0x01>; | |
| interconnects = <0x14a 0x34 0x29 0x200 0x25 0x02 0x3d 0x221>; | |
| pinctrl-1 = <0x301>; | |
| dma-coherent; | |
| compatible = "qcom,sdhci-msm-v5"; | |
| pinctrl-names = "default\0sleep"; | |
| qcom,vdd-io-current-level = <0x00 0x55f0>; | |
| operating-points-v2 = <0x14b>; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; | |
| clock-names = "iface\0core"; | |
| phandle = <0x2cd>; | |
| qcom,iommu-dma = "fastmap"; | |
| pinctrl-0 = <0x300>; | |
| iommus = <0x2f 0x140 0x00>; | |
| qcom,iommu-geometry = <0x40000000 0x10000000>; | |
| cd-debounce-delay-ms = <0x5dc>; | |
| qcom,restore-after-cx-collapse; | |
| qos1 { | |
| mask = <0x3f>; | |
| vote = <0x2c>; | |
| }; | |
| qos0 { | |
| mask = <0x03>; | |
| vote = <0x2c>; | |
| }; | |
| }; | |
| qcom,gdsc@19d004 { | |
| regulator-name = "gcc_pcie_1_gdsc"; | |
| reg = <0x19d004 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x31b>; | |
| qcom,retain-regs; | |
| qcom,collapse-vote = <0x18b 0x01>; | |
| }; | |
| qcom,dcvs { | |
| #size-cells = <0x01>; | |
| ranges; | |
| #address-cells = <0x01>; | |
| compatible = "qcom,dcvs"; | |
| phandle = <0x2c8>; | |
| l3 { | |
| qcom,dcvs-hw-type = <0x02>; | |
| qcom,bus-width = <0x20>; | |
| reg-names = "l3-base\0l3tbl-base"; | |
| reg = <0x17d90000 0x4000 0x17d90100 0xa0>; | |
| compatible = "qcom,dcvs-hw"; | |
| phandle = <0x145>; | |
| sp { | |
| qcom,shared-offset = <0x90>; | |
| qcom,dcvs-path-type = <0x00>; | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x146>; | |
| }; | |
| }; | |
| ddrqos { | |
| qcom,dcvs-hw-type = <0x03>; | |
| qcom,bus-width = <0x01>; | |
| qcom,freq-tbl = <0x142>; | |
| compatible = "qcom,dcvs-hw"; | |
| phandle = <0x147>; | |
| sp { | |
| interconnects = <0x25 0x02 0x29 0x200>; | |
| qcom,dcvs-path-type = <0x00>; | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x148>; | |
| }; | |
| }; | |
| ddr { | |
| qcom,dcvs-hw-type = <0x00>; | |
| qcom,bus-width = <0x04>; | |
| qcom,freq-tbl = <0x141>; | |
| compatible = "qcom,dcvs-hw"; | |
| phandle = <0x143>; | |
| sp { | |
| interconnects = <0x25 0x02 0x29 0x200>; | |
| qcom,dcvs-path-type = <0x00>; | |
| compatible = "qcom,dcvs-path"; | |
| phandle = <0x144>; | |
| }; | |
| }; | |
| }; | |
| wsa_spkr_en1_pinctrl { | |
| status = "disabled"; | |
| pinctrl-1 = <0x2f8>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| phandle = <0x47c>; | |
| pinctrl-0 = <0x2f9>; | |
| }; | |
| qcom,msm-pcm-routing { | |
| compatible = "qcom,msm-pcm-routing"; | |
| phandle = <0x37b>; | |
| }; | |
| qcom,rmnet-ipa { | |
| qcom,ipa-platform-type-msm; | |
| qcom,ipa-advertise-sg-support; | |
| qcom,ipa-napi-enable; | |
| compatible = "qcom,rmnet-ipa3"; | |
| qcom,rmnet-ipa-ssr; | |
| }; | |
| cpu-pmu { | |
| interrupts = <0x01 0x07 0x08>; | |
| compatible = "arm,armv8-pmuv3"; | |
| phandle = <0x2ce>; | |
| }; | |
| qcom,gdsc@3d9905c { | |
| qcom,reset-aon-logic; | |
| clocks = <0x24 0x20>; | |
| regulator-name = "gpu_cc_gx_gdsc"; | |
| reg = <0x3d9905c 0x04>; | |
| sw-reset = <0x18f>; | |
| domain-addr = <0x18e>; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "ahb_clk"; | |
| phandle = <0x32>; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| }; | |
| tpdm@10c71000 { | |
| coresight-name = "coresight-tpdm-wpss-cmb"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10c71000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x82>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x7a>; | |
| phandle = <0x7d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10c28000 { | |
| coresight-name = "coresight-tpdm-dlct"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10c28000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x237>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x60>; | |
| phandle = <0xc2>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interconnect@1510000 { | |
| qcom,bcm-voter-names = "hlos"; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x1510000 0xf200>; | |
| compatible = "qcom,ravelin-cnoc3"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x26>; | |
| }; | |
| syscon@3d99358 { | |
| reg = <0x3d99358 0x04>; | |
| compatible = "syscon"; | |
| phandle = <0x328>; | |
| }; | |
| funnel@10042000 { | |
| coresight-name = "coresight-funnel-in1"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10042000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x264>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xf4>; | |
| phandle = <0xf5>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0xf3>; | |
| phandle = <0xdc>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0xf1>; | |
| phandle = <0xe1>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0xf2>; | |
| phandle = <0xc8>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0xf0>; | |
| phandle = <0xaf>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@10801000 { | |
| coresight-name = "coresight-tpdm-modem-1"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x10801000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x43>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x244>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x71>; | |
| phandle = <0xa5>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@10c4b000 { | |
| coresight-name = "coresight-funnel-dl-west"; | |
| clocks = <0x31>; | |
| reg-names = "funnel-base"; | |
| reg = <0x10c4b000 0x1000>; | |
| compatible = "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x25f>; | |
| arm,primecell-periphid = <0xbb908>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xe1>; | |
| phandle = <0xf1>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xe0>; | |
| phandle = <0xdf>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interconnect@16C0000 { | |
| qcom,bcm-voter-names = "hlos"; | |
| clocks = <0x24 0x08 0x24 0x12>; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x16c0000 0x7080>; | |
| compatible = "qcom,ravelin-pcie_anoc"; | |
| qcom,bcm-voters = <0x14e>; | |
| phandle = <0x2c>; | |
| }; | |
| cti@10961000 { | |
| coresight-name = "coresight-cti-gpu_isdb_cti"; | |
| clocks = <0x31>; | |
| reg = <0x10961000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x277>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,msm_fastrpc { | |
| qcom,fastrpc-adsp-sensors-pdr; | |
| qcom,fastrpc-gids = <0xb5c>; | |
| qcom,rpc-latency-us = <0xeb>; | |
| qcom,qos-cores = <0x00 0x01 0x02 0x03 0x04 0x05>; | |
| compatible = "qcom,msm-fastrpc-compute"; | |
| phandle = <0x2d0>; | |
| qcom,fastrpc-adsp-audio-pdr; | |
| qcom,adsp-remoteheap-vmid = <0x16 0x25>; | |
| qcom,msm_fastrpc_compute_cb1 { | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| dma-coherent; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "adsprpc-smd"; | |
| iommus = <0x2f 0x1003 0x00>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb2 { | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| dma-coherent; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "adsprpc-smd"; | |
| iommus = <0x2f 0x1004 0x00>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb3 { | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| dma-coherent; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| shared-cb = <0x04>; | |
| label = "adsprpc-smd"; | |
| iommus = <0x2f 0x1005 0x00>; | |
| }; | |
| }; | |
| cti@12862000 { | |
| coresight-name = "coresight-cti-apss_atb_cti"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x12862000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x289>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| tpdm@10c01000 { | |
| coresight-name = "coresight-tpdm-rdpm-mx"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x10c01000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4f>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x9d>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x6c>; | |
| phandle = <0x99>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@18d078 { | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc"; | |
| reg = <0x18d078 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x321>; | |
| }; | |
| qcom,msm-dai-fe { | |
| compatible = "qcom,msm-dai-fe"; | |
| }; | |
| qcom,msm-compr-dsp { | |
| compatible = "qcom,msm-compr-dsp"; | |
| phandle = <0x37c>; | |
| }; | |
| qcom,cpu-vendor-hooks { | |
| compatible = "qcom,cpu-vendor-hooks"; | |
| phandle = <0x2e1>; | |
| }; | |
| interconnect@1 { | |
| qcom,bcm-voter-names = "hlos\0disp"; | |
| #interconnect-cells = <0x01>; | |
| compatible = "qcom,ravelin-mc_virt"; | |
| qcom,bcm-voters = <0x14e 0x14f>; | |
| phandle = <0x29>; | |
| }; | |
| syscon@17aa0000 { | |
| reg = <0x17aa0000 0x1c>; | |
| compatible = "syscon"; | |
| phandle = <0x136>; | |
| }; | |
| qcom,cpufreq-cdev { | |
| compatible = "qcom,cpufreq-cdev"; | |
| cpu-cluster0 { | |
| qcom,cpus = <0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; | |
| }; | |
| cpu-cluster1 { | |
| qcom,cpus = <0x20 0x21>; | |
| }; | |
| }; | |
| tgu@10b0f000 { | |
| tgu-conditions = <0x04>; | |
| tgu-steps = <0x03>; | |
| coresight-name = "coresight-tgu-spmi0"; | |
| clocks = <0x31>; | |
| reg-names = "tgu-base"; | |
| reg = <0x10b0f000 0x1000>; | |
| compatible = "arm,primecell"; | |
| tgu-regs = <0x09>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x290>; | |
| arm,primecell-periphid = <0xbb999>; | |
| tgu-timer-counters = <0x08>; | |
| }; | |
| qcom,gdsc@adf4004 { | |
| clocks = <0x24 0x0d>; | |
| regulator-name = "cam_cc_camss_top_gdsc"; | |
| reg = <0xadf4004 0x04>; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "ahb_clk"; | |
| phandle = <0x315>; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| }; | |
| tpdm@10c00000 { | |
| coresight-name = "coresight-tpdm-rdpm"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| qcom,cmb-msr-skip; | |
| reg = <0x10c00000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4f>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x9b>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x6b>; | |
| phandle = <0x98>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-tert-auxpcm { | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| qcom,msm-auxpcm-interface = "tertiary"; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| phandle = <0x3c3>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| }; | |
| tpdm@10ac0000 { | |
| coresight-name = "coresight-tpdm-dlct2-dsb"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10ac0000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4f>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x23e>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x67>; | |
| phandle = <0xd6>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| usb_audio_qmi_dev { | |
| qcom,usb-audio-stream-id = <0x0f>; | |
| qcom,usb-audio-intr-num = <0x02>; | |
| compatible = "qcom,usb-audio-qmi-dev"; | |
| qcom,iommu-dma = "disabled"; | |
| iommus = <0x2f 0x100f 0x00>; | |
| }; | |
| cti@10b41000 { | |
| coresight-name = "coresight-cti-lpass_lpi_cti"; | |
| clocks = <0x31>; | |
| reg = <0x10b41000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x27e>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| qcom,trust_ui_vm@e55fc000 { | |
| reg = <0xe55fc000 0x104000>; | |
| shared-buffers = <0x183 0x184>; | |
| phandle = <0x185>; | |
| vm_name = "trustedvm"; | |
| }; | |
| spi@984000 { | |
| dmas = <0x1a1 0x00 0x01 0x01 0x40 0x02 0x1a1 0x01 0x01 0x01 0x40 0x02>; | |
| qcom,wrapper-core = <0x19a>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x40 0x24 0x54 0x24 0x55>; | |
| #size-cells = <0x00>; | |
| reg-names = "se_phys"; | |
| #address-cells = <0x01>; | |
| spi-max-frequency = <0x2faf080>; | |
| reg = <0x984000 0x4000>; | |
| interrupts = <0x00 0x25a 0x04>; | |
| status = "disabled"; | |
| pinctrl-1 = <0x1a9>; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x336>; | |
| pinctrl-0 = <0x1a5 0x1a6 0x1a7 0x1a8>; | |
| }; | |
| hsphy@88e3000 { | |
| vdd-supply = <0x42>; | |
| resets = <0x24 0x0d>; | |
| vdda18-supply = <0x43>; | |
| clocks = <0x45 0x00 0x24 0x19>; | |
| reg-names = "hsusb_phy_base\0eud_enable_reg"; | |
| reg = <0x88e3000 0x11c 0x88e2000 0x04>; | |
| reset-names = "phy_reset"; | |
| qcom,vdd-voltage-level = <0x00 0xd6d80 0xe09c0>; | |
| compatible = "qcom,usb-hsphy-snps-femto"; | |
| clock-names = "ref_clk_src\0ref_clk"; | |
| phandle = <0x3f>; | |
| vdda33-supply = <0x44>; | |
| }; | |
| sdhc2-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x14b>; | |
| opp-100000000 { | |
| opp-hz = <0x00 0x5f5e100>; | |
| opp-peak-kBps = <0x186a00 0x445c0>; | |
| opp-avg-kBps = <0xc350 0x00>; | |
| }; | |
| opp-202000000 { | |
| opp-hz = <0x00 0xc0a4680>; | |
| opp-peak-kBps = <0x557300 0x16e360>; | |
| opp-avg-kBps = <0x19640 0x00>; | |
| }; | |
| }; | |
| qcom,gdsc@187004 { | |
| regulator-name = "gcc_ufs_phy_gdsc"; | |
| reg = <0x187004 0x04>; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x18c>; | |
| qcom,proxy-consumer-enable; | |
| qcom,retain-regs; | |
| parent-supply = <0x124>; | |
| proxy-supply = <0x18c>; | |
| }; | |
| etm4 { | |
| coresight-name = "coresight-etm4"; | |
| clocks = <0x31>; | |
| cpu = <0x1e>; | |
| qcom,skip-power-up; | |
| reg = <0x12440000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x05>; | |
| clock-names = "apb_pclk"; | |
| arm,primecell-periphid = <0xbb95d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x115>; | |
| phandle = <0x11e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-adsp-notify { | |
| status = "ok"; | |
| compatible = "qcom,adsp-notify"; | |
| qcom,rproc-handle = <0x2d4>; | |
| phandle = <0x3c9>; | |
| }; | |
| tpdm@10c70000 { | |
| coresight-name = "coresight-tpdm-wpss-dsb"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10c70000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x80>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x79>; | |
| phandle = <0x7c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@10845000 { | |
| coresight-name = "coresight-cti-lpass_dl_cti"; | |
| clocks = <0x31>; | |
| qcom,extended_cti; | |
| reg = <0x10845000 0x1000>; | |
| compatible = "arm,coresight-cti\0arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x276>; | |
| arm,primecell-periphid = <0xbb922>; | |
| }; | |
| pmic-pon-log { | |
| compatible = "qcom,pmic-pon-log"; | |
| nvmem-names = "pon_log"; | |
| nvmem = <0x401>; | |
| }; | |
| tpdm@10840000 { | |
| coresight-name = "coresight-tpdm-vsense"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x10840000 0x1000>; | |
| status = "disabled"; | |
| compatible = "arm,primecell"; | |
| atid = <0x4e>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x232>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5b>; | |
| phandle = <0xbf>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@109A4000 { | |
| coresight-name = "coresight-tpdm-wcss"; | |
| compatible = "qcom,coresight-dummy"; | |
| qcom,dummy-source; | |
| atid = <0x18>; | |
| phandle = <0x246>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x75>; | |
| phandle = <0xcb>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply_amoled { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| phandle = <0x44c>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-max-voltage = <0x328980>; | |
| qcom,supply-disable-load = <0x00>; | |
| reg = <0x01>; | |
| qcom,supply-name = "vci"; | |
| qcom,supply-post-off-sleep = <0x02>; | |
| qcom,supply-min-voltage = <0x2dc6c0>; | |
| qcom,supply-post-on-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x2710>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-max-voltage = <0x1e8480>; | |
| qcom,supply-disable-load = <0x50>; | |
| reg = <0x00>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-enable-load = <0x30d40>; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| qcom,supply-disable-load = <0x00>; | |
| reg = <0x02>; | |
| qcom,supply-name = "lab"; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| qcom,supply-enable-load = <0x00>; | |
| }; | |
| qcom,panel-supply-entry@3 { | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| qcom,supply-disable-load = <0x00>; | |
| reg = <0x03>; | |
| qcom,supply-name = "ibb"; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-enable-load = <0x00>; | |
| }; | |
| qcom,panel-supply-entry@4 { | |
| qcom,supply-max-voltage = <0x124f80>; | |
| qcom,supply-disable-load = <0x50>; | |
| reg = <0x04>; | |
| qcom,supply-name = "extvdd"; | |
| qcom,supply-post-off-sleep = <0x02>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| qcom,supply-post-on-sleep = <0x00>; | |
| qcom,supply-enable-load = <0xed1c>; | |
| }; | |
| }; | |
| qmi-tmd-devices { | |
| compatible = "qcom,qmi-cooling-devices"; | |
| modem { | |
| qcom,instance-id = <0x00>; | |
| sdr0_lte_dsc { | |
| qcom,qmi-dev-name = "sdr0_lte_dsc"; | |
| phandle = <0x35e>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_nr_sdr0_sub1_dsc { | |
| qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc"; | |
| phandle = <0x368>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_nr_sdr0_scg { | |
| qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; | |
| phandle = <0x36a>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| sdr1_nr_dsc { | |
| qcom,qmi-dev-name = "sdr1_nr_dsc"; | |
| phandle = <0x361>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_nr_scg_dsc { | |
| qcom,qmi-dev-name = "modem_nr_scg_dsc"; | |
| phandle = <0x35c>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_nr_sdr1_dsc { | |
| qcom,qmi-dev-name = "pa_nr_sdr1_dsc"; | |
| phandle = <0x367>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_nr_scg_sub1_dsc { | |
| qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc"; | |
| phandle = <0x35d>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_lte_sdr0_sub1_dsc { | |
| qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc"; | |
| phandle = <0x364>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_nr_dsc { | |
| qcom,qmi-dev-name = "modem_nr_dsc"; | |
| phandle = <0x35a>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_lte_sub1_dsc { | |
| qcom,qmi-dev-name = "modem_lte_sub1_dsc"; | |
| phandle = <0x359>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_nr_sdr0_dsc { | |
| qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; | |
| phandle = <0x366>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_nr_sdr1_scg { | |
| qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc"; | |
| phandle = <0x36b>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_lte_sdr1_sub1_dsc { | |
| qcom,qmi-dev-name = "pa_lte_sdr1_sub1_dsc"; | |
| phandle = <0x365>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_vdd { | |
| qcom,qmi-dev-name = "cpuv_restriction_cold"; | |
| phandle = <0x36d>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| sdr1_lte_dsc { | |
| qcom,qmi-dev-name = "sdr1_lte_dsc"; | |
| phandle = <0x35f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_nr_sub1_dsc { | |
| qcom,qmi-dev-name = "modem_nr_sub1_dsc"; | |
| phandle = <0x35b>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| sdr0_nr_dsc { | |
| qcom,qmi-dev-name = "sdr0_nr_dsc"; | |
| phandle = <0x360>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_lte_sdr0_dsc { | |
| qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; | |
| phandle = <0x362>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_lte_sdr1_dsc { | |
| qcom,qmi-dev-name = "pa_lte_sdr1_dsc"; | |
| phandle = <0x363>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pa_nr_sdr1_sub1_dsc { | |
| qcom,qmi-dev-name = "pa_nr_sdr1_sub1_dsc"; | |
| phandle = <0x369>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_lte_dsc { | |
| qcom,qmi-dev-name = "modem_lte_dsc"; | |
| phandle = <0x358>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| wlan { | |
| qcom,qmi-dev-name = "wlan"; | |
| phandle = <0x36c>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-q6-hdmi { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| phandle = <0x386>; | |
| qcom,msm-dai-q6-dev-id = <0x08>; | |
| }; | |
| qcom,gdsc@18d050 { | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; | |
| reg = <0x18d050 0x04>; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| qcom,no-status-check-on-disable; | |
| phandle = <0x27>; | |
| parent-supply = <0x124>; | |
| }; | |
| tpdm@1000f000 { | |
| coresight-name = "coresight-tpdm-spdm"; | |
| clocks = <0x31>; | |
| reg-names = "tpdm-base"; | |
| reg = <0x1000f000 0x1000>; | |
| compatible = "arm,primecell"; | |
| atid = <0x41>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x23b>; | |
| arm,primecell-periphid = <0xbb968>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x64>; | |
| phandle = <0xe9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ipcc-self-ping-apss { | |
| interrupts-extended = <0x13b 0x08 0x02 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x32f>; | |
| mboxes = <0x13b 0x08 0x02>; | |
| }; | |
| qcom,msm-dai-cdc-dma { | |
| compatible = "qcom,msm-dai-cdc-dma"; | |
| phandle = <0x393>; | |
| qcom,msm-dai-rx-cdc-dma-0-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x39c>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb030>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-1-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a5>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb033>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-6-rx { | |
| qcom,msm-cdc-dma-data-align = <0x01>; | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a2>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb03c>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-7-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a3>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb03e>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-5-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a1>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb03a>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-0-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x394>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb000>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-2-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x39e>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb034>; | |
| }; | |
| qcom,msm-dai-va-cdc-dma-0-tx { | |
| qcom,msm-dai-is-island-supported = <0x01>; | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x399>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb021>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-1-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x396>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb002>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-4-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a8>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb039>; | |
| }; | |
| qcom,msm-dai-va-cdc-dma-1-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x39a>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb023>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-1-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x39d>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb032>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-4-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a0>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb038>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-1-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x397>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb003>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-2-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x398>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb005>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-0-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x395>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb001>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-5-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a9>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb03b>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-3-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a7>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb037>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-3-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x39f>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb036>; | |
| }; | |
| qcom,msm-dai-va-cdc-dma-2-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x39b>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb025>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-2-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a6>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb035>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-0-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| phandle = <0x3a4>; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb031>; | |
| }; | |
| }; | |
| qcom,gdsc@160018 { | |
| regulator-name = "gcc_usb3_phy_gdsc"; | |
| reg = <0x160018 0x04>; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x31e>; | |
| qcom,retain-regs; | |
| }; | |
| syscon@1fc0000 { | |
| reg = <0x1fc0000 0x30000>; | |
| compatible = "syscon"; | |
| phandle = <0x03>; | |
| }; | |
| qcom,mem-buf { | |
| qcom,mem-buf-capabilities = "supplier"; | |
| compatible = "qcom,mem-buf"; | |
| qcom,vmid = <0x03>; | |
| }; | |
| remoteproc-wpss@8a00000 { | |
| firmware-name = "adrastea/wpss.mdt"; | |
| qcom,smem-states = <0x15e 0x00>; | |
| qcom,smem-state-names = "stop"; | |
| qcom,qmp = <0x31>; | |
| interrupts-extended = <0x01 0x00 0x24b 0x01 0x15d 0x00 0x00 0x15d 0x02 0x00 0x15d 0x01 0x00 0x15d 0x03 0x00 0x15d 0x07 0x00>; | |
| clocks = <0x45 0x00>; | |
| reg-names = "cx\0mx"; | |
| reg = <0x8a00000 0x10000>; | |
| mx-supply = <0x125>; | |
| interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack"; | |
| status = "ok"; | |
| compatible = "qcom,ravelin-wpss-pas"; | |
| cx-supply = <0x124>; | |
| memory-region = <0x15c>; | |
| clock-names = "xo"; | |
| phandle = <0x41b>; | |
| cx-uV-uA = <0x180 0x186a0>; | |
| mx-uV-uA = <0x180 0x186a0>; | |
| glink-edge { | |
| qcom,remote-pid = <0x0d>; | |
| interrupts = <0x18 0x00 0x01>; | |
| interrupt-parent = <0x13b>; | |
| mbox-names = "wpss_smem"; | |
| transport = "smem"; | |
| label = "wpss"; | |
| mboxes = <0x13b 0x18 0x00>; | |
| qcom,glink-label = "wpss"; | |
| qcom,wpss_qrtr { | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| }; | |
| }; | |
| qcom,cpu-pause { | |
| compatible = "qcom,thermal-pause"; | |
| cpu4-pause { | |
| qcom,cdev-alias = "thermal-pause-10"; | |
| qcom,cpus = <0x1e>; | |
| phandle = <0x16f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu5 { | |
| qcom,cdev-alias = "pause-cpu5"; | |
| qcom,cpus = <0x1f>; | |
| }; | |
| cpu0-pause { | |
| qcom,cdev-alias = "thermal-pause-1"; | |
| qcom,cpus = <0x1a>; | |
| phandle = <0x167>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu3-pause { | |
| qcom,cdev-alias = "thermal-pause-8"; | |
| qcom,cpus = <0x1d>; | |
| phandle = <0x16d>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu7 { | |
| qcom,cdev-alias = "pause-cpu7"; | |
| qcom,cpus = <0x21>; | |
| }; | |
| pause-cpu3 { | |
| qcom,cdev-alias = "pause-cpu3"; | |
| qcom,cpus = <0x1d>; | |
| }; | |
| cpu6-pause { | |
| qcom,cdev-alias = "thermal-pause-40"; | |
| qcom,cpus = <0x20>; | |
| phandle = <0x173>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu1 { | |
| qcom,cdev-alias = "pause-cpu1"; | |
| qcom,cpus = <0x1b>; | |
| }; | |
| cpu2-pause { | |
| qcom,cdev-alias = "thermal-pause-4"; | |
| qcom,cpus = <0x1c>; | |
| phandle = <0x16b>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu2 { | |
| qcom,cdev-alias = "pause-cpu2"; | |
| qcom,cpus = <0x1c>; | |
| }; | |
| pause-cpu0 { | |
| qcom,cdev-alias = "pause-cpu0"; | |
| qcom,cpus = <0x1a>; | |
| }; | |
| pause-cpu4 { | |
| qcom,cdev-alias = "pause-cpu4"; | |
| qcom,cpus = <0x1e>; | |
| }; | |
| cpu1-pause { | |
| qcom,cdev-alias = "thermal-pause-2"; | |
| qcom,cpus = <0x1b>; | |
| phandle = <0x169>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu-6-7-pause { | |
| qcom,cdev-alias = "thermal-pause-C0"; | |
| qcom,cpus = <0x20 0x21>; | |
| phandle = <0x34e>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| pause-cpu6 { | |
| qcom,cdev-alias = "pause-cpu6"; | |
| qcom,cpus = <0x20>; | |
| }; | |
| cpu5-pause { | |
| qcom,cdev-alias = "thermal-pause-20"; | |
| qcom,cpus = <0x1f>; | |
| phandle = <0x171>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu7-pause { | |
| qcom,cdev-alias = "thermal-pause-80"; | |
| qcom,cpus = <0x21>; | |
| phandle = <0x176>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| cpuss-sleep-stats@17800054 { | |
| reg-names = "seq_lpm_cntr_cfg_cpu0\0seq_lpm_cntr_cfg_cpu1\0seq_lpm_cntr_cfg_cpu2\0seq_lpm_cntr_cfg_cpu3\0seq_lpm_cntr_cfg_cpu4\0seq_lpm_cntr_cfg_cpu5\0seq_lpm_cntr_cfg_cpu6\0seq_lpm_cntr_cfg_cpu7\0l3_seq_lpm_cntr_cfg\0apss_seq_mem_base"; | |
| reg = <0x17800054 0x04 0x17810054 0x04 0x17820054 0x04 0x17830054 0x04 0x17840054 0x04 0x17850054 0x04 0x17860054 0x04 0x17870054 0x04 0x17880098 0x04 0x178c0000 0x10000>; | |
| compatible = "qcom,cpuss-sleep-stats"; | |
| num-cpus = <0x08>; | |
| }; | |
| modem2_etm0 { | |
| qcom,inst-id = <0x0b>; | |
| coresight-name = "coresight-modem2-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| atid = <0x27>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x73>; | |
| phandle = <0xac>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cluster-device { | |
| power-domains = <0x123>; | |
| compatible = "qcom,lpm-cluster-dev"; | |
| }; | |
| qcom,msm-dai-tdm-sen-tx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9151>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9051>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3e0>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-sen-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9051>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3e1>; | |
| }; | |
| }; | |
| i2c@990000 { | |
| dmas = <0x1a1 0x00 0x04 0x03 0x40 0x00 0x1a1 0x01 0x04 0x03 0x40 0x00>; | |
| qcom,wrapper-core = <0x19a>; | |
| dma-names = "tx\0rx"; | |
| clocks = <0x24 0x46 0x24 0x54 0x24 0x55>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| reg = <0x990000 0x4000>; | |
| interrupts = <0x00 0x25d 0x04>; | |
| status = "ok"; | |
| pinctrl-1 = <0x1b7>; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-names = "default\0sleep"; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| phandle = <0x33a>; | |
| pinctrl-0 = <0x1b5 0x1b6>; | |
| htrr@3c { | |
| htr3212r,dv-en2 = <0x126 0x00 0x00>; | |
| reg = <0x3c>; | |
| compatible = "kona,htr3212r"; | |
| }; | |
| }; | |
| funnel@10b44000 { | |
| coresight-name = "coresight-funnel-lpass_lpi"; | |
| compatible = "arm,coresight-static-funnel"; | |
| phandle = <0x24b>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x88>; | |
| phandle = <0xfe>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x87>; | |
| phandle = <0x4b>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x85>; | |
| phandle = <0x4a>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x86>; | |
| phandle = <0x4e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,glinkpkt { | |
| compatible = "qcom,glinkpkt"; | |
| qcom,glinkpkt-data40-cntl { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smdcntl8"; | |
| qcom,glinkpkt-ch-name = "DATA40_CNTL"; | |
| }; | |
| qcom,glinkpkt-at-mdm0 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "at_mdm0"; | |
| qcom,glinkpkt-ch-name = "DS"; | |
| }; | |
| qcom,glinkpkt-data11 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd11"; | |
| qcom,glinkpkt-ch-name = "DATA11"; | |
| }; | |
| qcom,glinkpkt-data1 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd7"; | |
| qcom,glinkpkt-ch-name = "DATA1"; | |
| }; | |
| qcom,glinkpkt-data4 { | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd8"; | |
| qcom,glinkpkt-ch-name = "DATA4"; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-tert-tx { | |
| qcom,msm-cpudai-tdm-group-id = <0x9121>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9021>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| phandle = <0x3d4>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-dai-q6-tdm-tert-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9021>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x3d5>; | |
| }; | |
| }; | |
| qcom,virtio_backend@0 { | |
| qcom,label = <0x11>; | |
| qcom,vm = <0x185>; | |
| compatible = "qcom,virtio_backend"; | |
| }; | |
| }; | |
| sram@17D09100 { | |
| #size-cells = <0x02>; | |
| ranges = <0x00 0x00 0x00 0x17d09100 0x00 0x200>; | |
| #address-cells = <0x02>; | |
| reg = <0x00 0x17d09100 0x00 0x200>; | |
| compatible = "mmio-sram"; | |
| phandle = <0x213>; | |
| scp-shmem@0 { | |
| reg = <0x00 0x00 0x00 0x200>; | |
| compatible = "arm,scp-shmem"; | |
| phandle = <0x12f>; | |
| }; | |
| }; | |
| chosen { | |
| bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat msm_rtb.filter=0x237 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat video=vfb:640x400,bpp=32,memsize=3072000 bootconfig buildvariant=user msm_drm.dsi_display0=qcom,mdss_dsi_g1392_fhd_plus_60_video: rootwait ro init=/init mem=5265948672B memhp_default_state=online movable_node"; | |
| linux,initrd-start = <0x00 0xb74f4000>; | |
| phandle = <0x1fb>; | |
| linux,initrd-end = <0x00 0xb7ffeb18>; | |
| stdout-path = "/soc/qcom,qup_uart@a88000:115200n8"; | |
| kaslr-seed = <0x00 0x00>; | |
| }; | |
| memory { | |
| ddr_device_type = <0x07>; | |
| device_type = "memory"; | |
| reg = <0x00 0x80000000 0x00 0x68e00000 0x00 0xe9500000 0x00 0x00 0x00 0xea700000 0x00 0x15900000 0x08 0x00 0x00 0x3fd00000 0x08 0x40000000 0x00 0x7ba00000 0x08 0xc0000000 0x00 0x40000000>; | |
| }; | |
| ddr-regions { | |
| region1 = <0x08 0x00 0x00 0x40000000 0x00 0x00 0x00 0x04 0x00 0x200>; | |
| region2 = <0x08 0x40000000 0x00 0xc0000000 0x00 0x00 0x00 0x08 0x00 0x200>; | |
| region0 = <0x00 0x80000000 0x00 0x80000000 0x00 0x00 0x00 0x00 0x00 0x200>; | |
| }; | |
| reserved-memory { | |
| #size-cells = <0x02>; | |
| ranges; | |
| #address-cells = <0x02>; | |
| phandle = <0x1fc>; | |
| trust_ui_vm_qrtr@e55f3000 { | |
| no-map; | |
| reg = <0x00 0xe55f3000 0x00 0x9000>; | |
| phandle = <0x182>; | |
| }; | |
| adsp_heap_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0xc00000>; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x14d>; | |
| reusable; | |
| }; | |
| gpu_microcode_region@8941a000 { | |
| no-map; | |
| reg = <0x00 0x8941a000 0x00 0x2000>; | |
| phandle = <0x34>; | |
| }; | |
| non_secure_display_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x5c00000>; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x39>; | |
| reusable; | |
| }; | |
| trust_ui_vm_vblk0_ring@e55fc000 { | |
| no-map; | |
| gunyah-label = <0x11>; | |
| reg = <0x00 0xe55fc000 0x00 0x4000>; | |
| phandle = <0x183>; | |
| }; | |
| ramoops_region { | |
| pmsg-size = <0x200000>; | |
| alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>; | |
| size = <0x00 0x200000>; | |
| compatible = "ramoops"; | |
| phandle = <0x211>; | |
| mem-type = <0x02>; | |
| }; | |
| qseecom_ta_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x1000000>; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x37>; | |
| reusable; | |
| }; | |
| mpss_region@8a000000 { | |
| no-map; | |
| reg = <0x00 0x8a000000 0x00 0xda00000>; | |
| phandle = <0x159>; | |
| }; | |
| audio_cma_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x1c00000>; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x38>; | |
| reusable; | |
| }; | |
| chipinfo_region@808f4000 { | |
| no-map; | |
| reg = <0x00 0x808f4000 0x00 0x1000>; | |
| phandle = <0x206>; | |
| }; | |
| va_md_mem_region { | |
| alloc-ranges = <0x01 0x00 0xfffffffe 0xffffffff>; | |
| size = <0x00 0x1000000>; | |
| compatible = "shared-dma-pool"; | |
| phandle = <0x14c>; | |
| reusable; | |
| }; | |
| trust_ui_vm_swiotlb@e5600000 { | |
| no-map; | |
| gunyah-label = <0x12>; | |
| reg = <0x00 0xe5600000 0x00 0x100000>; | |
| phandle = <0x184>; | |
| }; | |
| aop_image_region@80800000 { | |
| no-map; | |
| reg = <0x00 0x80800000 0x00 0x60000>; | |
| phandle = <0x200>; | |
| }; | |
| tme_crash_dump_region@808a0000 { | |
| no-map; | |
| reg = <0x00 0x808a0000 0x00 0x40000>; | |
| phandle = <0x203>; | |
| }; | |
| wpss_moselle_region@85300000 { | |
| no-map; | |
| reg = <0x00 0x85300000 0x00 0x1900000>; | |
| phandle = <0x15c>; | |
| }; | |
| cnss_wlan_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x2000000>; | |
| status = "disabled"; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x1ea>; | |
| reusable; | |
| }; | |
| smem_region@80900000 { | |
| no-map; | |
| reg = <0x00 0x80900000 0x00 0x200000>; | |
| phandle = <0x139>; | |
| }; | |
| ipa_gsi_region@89410000 { | |
| no-map; | |
| reg = <0x00 0x89410000 0x00 0xa000>; | |
| phandle = <0x15f>; | |
| }; | |
| qseecom_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x1400000>; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x36>; | |
| reusable; | |
| }; | |
| trust_ui_vm_region@e0b00000 { | |
| no-map; | |
| reg = <0x00 0xe0b00000 0x00 0x4af3000>; | |
| phandle = <0x186>; | |
| }; | |
| mem_dump_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0xc00000>; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x122>; | |
| reusable; | |
| }; | |
| camera_region@84b00000 { | |
| no-map; | |
| reg = <0x00 0x84b00000 0x00 0x800000>; | |
| phandle = <0x208>; | |
| }; | |
| adsp_region@87300000 { | |
| no-map; | |
| reg = <0x00 0x87300000 0x00 0x2100000>; | |
| phandle = <0x155>; | |
| }; | |
| tz_stat_region@e8800000 { | |
| no-map; | |
| reg = <0x00 0xe8800000 0x00 0x100000>; | |
| phandle = <0x20d>; | |
| }; | |
| ipa_fw_region@89400000 { | |
| no-map; | |
| reg = <0x00 0x89400000 0x00 0x10000>; | |
| phandle = <0x20a>; | |
| }; | |
| splash_region { | |
| reg = <0x00 0xb8000000 0x00 0x2b00000>; | |
| phandle = <0x46f>; | |
| label = "cont_splash_region"; | |
| }; | |
| uefi_log_region@808e4000 { | |
| no-map; | |
| reg = <0x00 0x808e4000 0x00 0x10000>; | |
| phandle = <0x205>; | |
| }; | |
| aop_config_region@80880000 { | |
| no-map; | |
| reg = <0x00 0x80880000 0x00 0x20000>; | |
| phandle = <0x202>; | |
| }; | |
| hyp_region@80000000 { | |
| no-map; | |
| reg = <0x00 0x80000000 0x00 0x600000>; | |
| phandle = <0x1fd>; | |
| }; | |
| xbl_sc_region@a6e00000 { | |
| no-map; | |
| reg = <0x00 0xa6e00000 0x00 0x40000>; | |
| phandle = <0x20b>; | |
| }; | |
| wlan_msa_mem_region@82a00000 { | |
| no-map; | |
| reg = <0x00 0x82a00000 0x00 0x300000>; | |
| phandle = <0x41c>; | |
| }; | |
| qtee_region@e8f80000 { | |
| no-map; | |
| reg = <0x00 0xe8f80000 0x00 0x500000>; | |
| phandle = <0x20f>; | |
| }; | |
| video_region@86c00000 { | |
| no-map; | |
| reg = <0x00 0x86c00000 0x00 0x700000>; | |
| phandle = <0x209>; | |
| }; | |
| global_sync_region@a6f00000 { | |
| no-map; | |
| reg = <0x00 0xa6f00000 0x00 0x100000>; | |
| phandle = <0x20c>; | |
| }; | |
| tme_log_region@808e0000 { | |
| no-map; | |
| reg = <0x00 0x808e0000 0x00 0x4000>; | |
| phandle = <0x204>; | |
| }; | |
| cpucp_fw_region@80b00000 { | |
| no-map; | |
| reg = <0x00 0x80b00000 0x00 0x100000>; | |
| phandle = <0x207>; | |
| }; | |
| user_contig_region { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x1000000>; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x35>; | |
| reusable; | |
| }; | |
| aop_cmd_db_region@80860000 { | |
| no-map; | |
| reg = <0x00 0x80860000 0x00 0x20000>; | |
| compatible = "qcom,cmd-db"; | |
| phandle = <0x201>; | |
| }; | |
| cpusys_vm_region@e0600000 { | |
| no-map; | |
| reg = <0x00 0xe0600000 0x00 0x400000>; | |
| phandle = <0x187>; | |
| }; | |
| xbl_ramdump_region@80640000 { | |
| no-map; | |
| reg = <0x00 0x80640000 0x00 0x1c0000>; | |
| phandle = <0x1ff>; | |
| }; | |
| xbl_dtlog_region@80600000 { | |
| no-map; | |
| reg = <0x00 0x80600000 0x00 0x40000>; | |
| phandle = <0x1fe>; | |
| }; | |
| trusted_apps_region@e9480000 { | |
| no-map; | |
| reg = <0x00 0xe9480000 0x00 0x1200000>; | |
| phandle = <0x210>; | |
| }; | |
| tags_region@e8900000 { | |
| no-map; | |
| reg = <0x00 0xe8900000 0x00 0x680000>; | |
| phandle = <0x20e>; | |
| }; | |
| linux,cma { | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x2000000>; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x2e>; | |
| linux,cma-default; | |
| reusable; | |
| }; | |
| }; | |
| }; |
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