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Trunkol/aula03-demux.vhdl

Created August 31, 2018 14:43
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aula03-demux.vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY demultiplexador IS
PORT (
x : IN std_logic;
s : IN std_logic_vector(3 DOWNTO 0);
y : OUT std_logic_vector(15 DOWNTO 0)
);
END demultiplexador;
ARCHITECTURE demux OF demultiplexador IS
BEGIN
PROCESS (x, s)
BEGIN
CASE s IS
WHEN "0000" =>
y(0) <= x;
WHEN "0001" =>
y(1) <= x;
WHEN "0010" =>
y(2) <= x;
WHEN "0011" =>
y(3) <= x;
WHEN "0100" =>
y(4) <= x;
WHEN "0101" =>
y(5) <= x;
WHEN "0110" =>
y(6) <= x;
WHEN "0111" =>
y(7) <= x;
WHEN "1000" =>
y(8) <= x;
WHEN "1001" =>
y(9) <= x;
WHEN "1010" =>
y(10) <= x;
WHEN "1011" =>
y(11) <= x;
WHEN "1100" =>
y(12) <= x;
WHEN "1101" =>
y(13) <= x;
WHEN "1110" =>
y(14) <= x;
WHEN OTHERS =>
y(15) <= x;
END CASE;
END PROCESS;
END demux;
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