bit-hack’s gists

bit-hack / gatekeeper.py

Created April 7, 2025 18:57

gatekeeper

	#!/usr/bin/python

	from tkinter import *


	PWD_LENGTH = 16


	tokens = ''.join((
	'abcdefghijklmnopqrstuvwxyz',

bit-hack / cover.h

Last active February 2, 2023 15:52

cover_test

	#pragma once

	#define ENABLE_COVERAGE 1
	#if ENABLE_COVERAGE

	#define COVER_LOCATION printf("%s:%u ", __FILE__, __LINE__)
	#define COVER_TOKEN printf(" // COVERED\n")

	#define COVER_ONCE(TEXT) \
	{ \

bit-hack / camera.cpp

Created October 1, 2022 21:51

OpenGL camera class

	#include <cstdint>
	#include <cmath>

	#include <GLFW/glfw3.h>

	#include "camera.h"


	const float pi = 3.14159265359f;

bit-hack / permutations.c

Created August 24, 2022 17:39

Generate all permutations of an array


	#include <stdio.h>
	#include <stdint.h>

	void swap(uint8_t *a, uint8_t i, uint8_t j) {
	uint8_t t = a[i];
	a[i] = a[j];
	a[j] = t;
	}

bit-hack / blaster.txt

Created June 28, 2022 22:03

blaster.txt


	----------------------------------------------------------------
	PORTS
	----------------------------------------------------------------

	PORT_DSP_RESET = PORT_BASE + 0x6, // wo

	PORT_DSP_READ_DATA = PORT_BASE + 0xA, // ro
	// returns 0xAA after reset

bit-hack / main.cpp

Last active May 23, 2022 18:26

VCD file writer

	#include "vcd.h"

	#include <cstdlib>

	int main(int argc, char **args) {

	vcd::vcd_t vcd;
	if (!vcd.begin("test.vcd", 1, vcd::timescale_ps)) {
	return 1;
	}

bit-hack / spiSlave.v

Last active April 28, 2022 20:37

spi slave device


	module spiSlave(
	input iClk, // master clock
	input iSck, // spi clock (sample posedge)
	input iCs, // spi chip select (active low)
	input iMosi, // master out slave in
	input [7:0] iData, // data transmit
	output oMiso, // master in slave out
	output [7:0] oData, // data received
	output oAvail // data received strobe

bit-hack / blender.md

Last active March 4, 2023 15:42

Blender-cheat-sheet

General:

g                 - Move
r                 - Rotate
s                 - Scale

Tab               - Toggle between Object and Edit mode
Shift + Tab       - Toggle Snap
Shift + a         - Add Menu

bit-hack / verilog_debounce.v

Created October 6, 2021 17:20

A simple verilog debouncer circuit

	module debounce(
	input clk,
	input iKey,
	output oOut,
	);
	reg [3:0] state;
	assign oOut = state[3];
	always @(posedge clk) begin
	if (iKey) begin
	state <= (state == 4'hf) ? 4'hf : (state + 1);

bit-hack / env2.v

Last active August 30, 2021 21:32

second revision of the envelope

	`default_nettype none
	`timescale 1us/1ns

	module sid_env_imp(
	input CLK,
	input CLKen,
	input GATE,
	input [3:0] ATT,
	input [3:0] DEC,
	input [3:0] SUS,

Aidan Dodds bit-hack