csrohit · January 9, 2023 17:23
diff --git a/ahb2-div.c b/ahb2-div.c
 RCC->CFGR	  |= RCC_CFGR_PPRE1_2;
 RCC->CFGR 	|= RCC_CFGR_PLLXTPRE_HSE;
diff --git a/clock-configuration.c b/clock-configuration.c
 // comments only
diff --git a/clock-pll.c b/clock-pll.c
 RCC->CFGR 	|= RCC_CFGR_SW_PLL;
 while (!(RCC->CFGR & RCC_CFGR_SWS_PLL))
 		;
 // clock is ready @72MHZ
diff --git a/hse-on.c b/hse-on.c
 RCC->CR 	|= RCC_CR_HSEON;
 while (!(RCC->CR & RCC_CR_HSERDY))
 	;
 // hse ready
diff --git a/latency.c b/latency.c
 FLASH->ACR	|= FLASH_ACR_LATENCY_2;
diff --git a/pll-ready.c b/pll-ready.c
 RCC->CFGR 	|= RCC_CFGR_PLLSRC;
 RCC->CFGR 	|= RCC_CFGR_PLLMULL9;
 RCC->CR     |= RCC_CR_PLLON;
 while (!(RCC->CR & RCC_CR_PLLRDY))
 	;
 // PLL is ready
	RCC->CFGR \|= RCC_CFGR_PPRE1_2;
	RCC->CFGR \|= RCC_CFGR_PLLXTPRE_HSE;
	RCC->CFGR \|= RCC_CFGR_SW_PLL;
	while (!(RCC->CFGR & RCC_CFGR_SWS_PLL))
	;
	// clock is ready @72MHZ