sim

This time using Schmitt-input flip flop with comparator (output blue), which seems to produce a very reliable transition (yellow) right when clock (green) goes up.
Screencast_20251202_154421.webm

The hysteresis is good cause sometimes the transition injects glitches into the analog input signal (red)

Add 10mohm feedback for output and apply a notch filter, so green final output has much less of the oscillation frequency:

almost imperceptible latency:

adding a notch-filter for the oscillation combined with a lowpass:

This gives a pretty good reconstruction:

The filters add just a tad of delay.

Here is 0.1V(peak) 20khz sine (yellow) being reconstructed w/ notch (green):

my notch filter may be suffering from breadboard parasitics.

There is some glitch that happens when use input that is just DC with some offset away from the midpoint, which causes the output reconstruction to alternate between hitting each rail every second or so. By moving offset back to midpoint and adding an actual sine input, that glitch goes away:

For instance, here the input (yellow) is just a DC value that I'm changing every few seconds:

But if I get too close to the negative rail, then that triggers the output to enter an oscillatory state of decaying closer to the midpoint and then jumping to the opposite rail, which keeps repeating.

at it seems to be the 2nd integral signal that does this oscillation...the first integration signal stays around mid voltage:

It seems the second integral signal isn't properly integrating cause its top or bottom gets clipped:

the signals when changing from one rail to the other:

So it seems once its has decayed enough so that the top of the 2nd-integral signal no longer clips, then that triggers the resumption of proper integration...but what happens is the decay keeps on happening and actually over shoots and hits the other rail.

To lessen likelihood of entering this situation, should always DC block the input signal.

zoomed out a bit:

If instead did two RC low pass filters in series, then I'd think at least the "integration" would always remain around the middle voltage, so wouldn't have this rail hitting issue. The capacitors would always be keeping the proper voltage. Would still need an opamp afterwards to amplify the signal so it is the same amplitude range as the input signal.

but if try two RC integrations, then get not so great frequency spectrum:

There is a 3rd harmonic. So the question I need to investigate is can I get rid of that harmonic with RC and just deal with RC-only, without having to even involve opamp? Or is the issue something else that can be avoided in some other manner?

the pwm seems to be close to 50% during rail transitions:

ADC 2nd integration (yellow) also hits the rails