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@lashtear
Created November 11, 2025 11:33
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debugging mos-sim via old code
\ Adapted from http://forum.6502.org/viewtopic.php?f=2&t=2263
\ also cf. http://forum.6502.org/viewtopic.php?f=2&t=5931
include 816w2.fs
hex flush
: output-filename s" detect-sim.bin" ;
#-514 constant no-such-file
0fff5 constant SIM_CIN
0fff6 constant SIM_EOF
0fff7 constant SIM_ABORT
0fff8 constant SIM_EXIT
0fff9 constant SIM_COUT
output-filename delete-file ?dup [if]
dup no-such-file <> [if]
throw [then]
drop
[then]
use detect-sim.bin
forth also 816asm
set-emulation
0 tdp !
2000 4 - origin! \ nonsense origin for building the file
there constant loadaddr-cell \ tell sim to load at $2000
2000 t,
there constant length-cell
0 t, ( figure it out later )
there constant entry \ $2000 entry/origin
\ detect via the Chromatix method, cf.
\ http://forum.6502.org/viewtopic.php?f=2&t=5931
0 lda:#m 84 sta:d 85 sta:d
1d lda:#m 83 sta:d
6b lda:#m 1d sta:d
4e lda:#m
\ Now we have zeropage set up like
\ 1d: 6b
\ 83: 1d
\ 84: 00
\ 85: 00
\ with 4e in the accumulator
83 eor:dil ( aka 83 rmb4 cmos) \ execute $47 $83, then
83 eor:d \ survey the wreckage
\ type | NMOS 6502 | WDC 65c816 | Rockwell 65c02
\ raw | 47 83 | 47 83 | 47 83
\ trad | SRE ($83) | EOR [$83] | RMB4 ($83)
\ ours | 83 sre:d | 83 eor:dil | 83 rmb4:d
\ NMOS - SRE-direct seems to be roughly:
\ SRE {adr} = LSR {adr}; EOR {adr}
\ A contains 'N'
\ 65SC02 sees 47 83 as two nops
\ A contains 'S'
\ 65C816 EOR [$83]:
\ a ^= mem[direct(83) | direct(84)<<8 | direct(85)<<16]
\ A contains '8'
\ 65C02 RMB4 ($83):
\ mem[83] &= !(1<<4)
\ A contains 'C'
'N' cmp:#m eq/ if, \ Quacks like NMOS so far
cli:. sed:. \ Check for broken decimal
90 lda:#m 10 adc:#m
cld:. sei:. cs/ if,
'N' lda:#m \ Decimal works
rol:. ror:. \ Check for broken ROR
cc/ if,
'O' lda:#m \ ROR broken!
then,
else,
'd' lda:#m \ Decimal missing like 2A03
then,
then,
'S' cmp:#m \ Looks like a sc-test but
there 6 + dup bne:r bra:r \ branch on fail and always
'n' lda:#m \ Anything reaching here past
\ the BNE+BRA is probably a
\ bad NMOS simulator doing
\ NOPs for undoc insns
'C' cmp:#m eq/ if, \ Smells CMOSsy
1 ldy:#x 1 cpy:#x \ Setup y=$01, z=1
( 8 REP aka CLY,PHP aka 8 CPZ )
8 rep:# \ Try 8 rep.#; on an 816 this
\ is just cld:..
eq/ if, \ But z should still be set
0 cpy:#x eq/ if, \ If y is zero, we ran CLY,PHP
ply:. \ so fix up the stack
'H' lda:#m \ and report Hudson
then,
else,
'E' lda:#m \ We ran 8 CPZ instead, so
then, \ we seem to be a 65CE02
then,
'8' cmp:#m eq/ if, \ Definitely an 816 so turn
sec:. xce:. cc/ if, \ on 6502, but native before?
ply:. \ Yes, so fix the stack
then,
then,
\ accumulator now contains ASCII:
\ O - old NMOS 6502 (faulty ROR)
\ N - real NMOS 6502
\ n - NMOS simulator with 1-byte NOPs
\ d - NMOS without Decimal mode (eg. Ricoh 2A03)
\ S - 65SC02
\ C - 65C02
\ E - 65CE02
\ H - HuC6280
\ 8 - 65C816 or 65C802
SIM_COUT sta:a
0a lda:#m
SIM_COUT sta:a
00 lda:#m
SIM_EXIT sta:a
0 brk:#
\ fixup block load size now that we know it
there entry - length-cell t!
\ append a vector block so it knows where to start
0fffa t,
6 t,
2000 t, \ NMI
2000 t, \ Reset
0fff7 t, \ IRQ/BRK
cr
flush
variable fileid
output-filename r/w open-file throw fileid !
there loadaddr-cell - 0 fileid @ resize-file throw
fileid @ close-file throw
bye
@lashtear
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$ mos-sim --trace ~/src/816asm/detect-sim.bin 
2000 a:00 x:00 y:00 s: fd st:20 insn:a9 00 85
2002 a:00 x:00 y:00 s: fd st:22 insn:85 84 85
2004 a:00 x:00 y:00 s: fd st:22 insn:85 85 a9
2006 a:00 x:00 y:00 s: fd st:22 insn:a9 1d 85
2008 a:1d x:00 y:00 s: fd st:20 insn:85 83 a9
200a a:1d x:00 y:00 s: fd st:20 insn:a9 6b 85
200c a:6b x:00 y:00 s: fd st:20 insn:85 1d a9
200e a:6b x:00 y:00 s: fd st:20 insn:a9 4e 47
2010 a:4e x:00 y:00 s: fd st:20 insn:47 83 45
2012 a:40 x:00 y:00 s: fd st:21 insn:45 83 c9
2014 a:4e x:00 y:00 s: fd st:21 insn:c9 4e d0
2016 a:4e x:00 y:00 s: fd st:23 insn:d0 17 58
2018 a:4e x:00 y:00 s: fd st:23 insn:58 f8 a9
2019 a:4e x:00 y:00 s: fd st:23 insn:f8 a9 90
201a a:4e x:00 y:00 s: fd st:2b insn:a9 90 69
201c a:90 x:00 y:00 s: fd st:a9 insn:69 10 d8
201e a:01 x:00 y:00 s: fd st:a9 insn:d8 78 90
201f a:01 x:00 y:00 s: fd st:a1 insn:78 90 0b
2020 a:01 x:00 y:00 s: fd st:a5 insn:90 0b a9
2022 a:01 x:00 y:00 s: fd st:a5 insn:a9 4e 2a
2024 a:4e x:00 y:00 s: fd st:25 insn:2a 6a b0
2025 a:9d x:00 y:00 s: fd st:a4 insn:6a b0 02
2026 a:4e x:00 y:00 s: fd st:25 insn:b0 02 a9
202a a:4e x:00 y:00 s: fd st:25 insn:18 90 02
202b a:4e x:00 y:00 s: fd st:24 insn:90 02 a9
202f a:4e x:00 y:00 s: fd st:24 insn:c9 53 d0
2031 a:4e x:00 y:00 s: fd st:a4 insn:d0 04 80
2037 a:4e x:00 y:00 s: fd st:a4 insn:c9 43 d0
2039 a:4e x:00 y:00 s: fd st:25 insn:d0 14 a0
204f a:4e x:00 y:00 s: fd st:25 insn:c9 38 d0
2051 a:4e x:00 y:00 s: fd st:25 insn:d0 05 38
2058 a:4e x:00 y:00 s: fd st:25 insn:8d f9 ff
205b a:4e x:00 y:00 s: fd st:25 insn:a9 0a 8d
205d a:0a x:00 y:00 s: fd st:25 insn:8d f9 ff
N
2060 a:0a x:00 y:00 s: fd st:25 insn:a9 00 8d
2062 a:00 x:00 y:00 s: fd st:27 insn:8d f8 ff

so, yay, now that's working

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