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mgronhol/flapflap.v

Created May 23, 2017 19:29
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Flip-flop in verilog
Raw
flapflap.v
module flapflap(d,clk,q,qn);
input d,clk;
output q,qn;
reg q,qn;
initial
begin
q=0;
qn=1;
end
always @(posedge clk)
begin
q <= d;
qn <= !d;
end
endmodule
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