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November 10, 2024 22:53
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| # 0 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts" | |
| # 0 "<built-in>" | |
| # 0 "<command-line>" | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts" | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi" 1 | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi" 1 | |
| /dts-v1/; | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/gpio/gpio.h" 1 | |
| # 6 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi" 2 | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/input/input.h" 1 | |
| # 13 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/input/input.h" | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/input/linux-event-codes.h" 1 | |
| # 14 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/input/input.h" 2 | |
| # 7 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi" 2 | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/leds/common.h" 1 | |
| # 8 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi" 2 | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385.dtsi" 1 | |
| # 12 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385.dtsi" | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-38x.dtsi" 1 | |
| # 12 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-38x.dtsi" | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/interrupt-controller/arm-gic.h" 1 | |
| # 9 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/interrupt-controller/arm-gic.h" | |
| # 1 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/interrupt-controller/irq.h" 1 | |
| # 10 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/include/dt-bindings/interrupt-controller/arm-gic.h" 2 | |
| # 13 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-38x.dtsi" 2 | |
| / { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| model = "Marvell Armada 38x family SoC"; | |
| compatible = "marvell,armada380"; | |
| aliases { | |
| gpio0 = &gpio0; | |
| gpio1 = &gpio1; | |
| serial0 = &uart0; | |
| serial1 = &uart1; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a9-pmu"; | |
| interrupts-extended = <&mpic 3>; | |
| }; | |
| soc { | |
| compatible = "marvell,armada380-mbus", "simple-bus"; | |
| #address-cells = <2>; | |
| #size-cells = <1>; | |
| controller = <&mbusc>; | |
| interrupt-parent = <&gic>; | |
| pcie-mem-aperture = <0xe0000000 0x8000000>; | |
| pcie-io-aperture = <0xe8000000 0x100000>; | |
| bootrom { | |
| compatible = "marvell,bootrom"; | |
| reg = <(((0x01) << 24) | ((0x1d) << 16)) 0 0x200000>; | |
| }; | |
| devbus_bootcs: devbus-bootcs { | |
| compatible = "marvell,mvebu-devbus"; | |
| reg = <(((0xf0) << 24) | ((0x01) << 16)) 0x10400 0x8>; | |
| ranges = <0 (((0x01) << 24) | ((0x2f) << 16)) 0 0xffffffff>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| devbus_cs0: devbus-cs0 { | |
| compatible = "marvell,mvebu-devbus"; | |
| reg = <(((0xf0) << 24) | ((0x01) << 16)) 0x10408 0x8>; | |
| ranges = <0 (((0x01) << 24) | ((0x3e) << 16)) 0 0xffffffff>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| devbus_cs1: devbus-cs1 { | |
| compatible = "marvell,mvebu-devbus"; | |
| reg = <(((0xf0) << 24) | ((0x01) << 16)) 0x10410 0x8>; | |
| ranges = <0 (((0x01) << 24) | ((0x3d) << 16)) 0 0xffffffff>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| devbus_cs2: devbus-cs2 { | |
| compatible = "marvell,mvebu-devbus"; | |
| reg = <(((0xf0) << 24) | ((0x01) << 16)) 0x10418 0x8>; | |
| ranges = <0 (((0x01) << 24) | ((0x3b) << 16)) 0 0xffffffff>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| devbus_cs3: devbus-cs3 { | |
| compatible = "marvell,mvebu-devbus"; | |
| reg = <(((0xf0) << 24) | ((0x01) << 16)) 0x10420 0x8>; | |
| ranges = <0 (((0x01) << 24) | ((0x37) << 16)) 0 0xffffffff>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| internal-regs { | |
| compatible = "simple-bus"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0 (((0xf0) << 24) | ((0x01) << 16)) 0 0x100000>; | |
| sdramc: sdramc@1400 { | |
| compatible = "marvell,armada-xp-sdram-controller"; | |
| reg = <0x1400 0x500>; | |
| }; | |
| L2: cache-controller@8000 { | |
| compatible = "arm,pl310-cache"; | |
| reg = <0x8000 0x1000>; | |
| cache-unified; | |
| cache-level = <2>; | |
| arm,double-linefill-incr = <0>; | |
| arm,double-linefill-wrap = <0>; | |
| arm,double-linefill = <0>; | |
| prefetch-data = <1>; | |
| }; | |
| scu@c000 { | |
| compatible = "arm,cortex-a9-scu"; | |
| reg = <0xc000 0x58>; | |
| }; | |
| timer@c200 { | |
| compatible = "arm,cortex-a9-global-timer"; | |
| reg = <0xc200 0x20>; | |
| interrupts = <1 11 (1 | (((1 << (2)) - 1) << 8))>; | |
| clocks = <&coreclk 2>; | |
| }; | |
| timer@c600 { | |
| compatible = "arm,cortex-a9-twd-timer"; | |
| reg = <0xc600 0x20>; | |
| interrupts = <1 13 (1 | (((1 << (2)) - 1) << 8))>; | |
| clocks = <&coreclk 2>; | |
| }; | |
| gic: interrupt-controller@d000 { | |
| compatible = "arm,cortex-a9-gic"; | |
| #interrupt-cells = <3>; | |
| #size-cells = <0>; | |
| interrupt-controller; | |
| reg = <0xd000 0x1000>, | |
| <0xc100 0x100>; | |
| }; | |
| i2c0: i2c@11000 { | |
| compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; | |
| reg = <0x11000 0x20>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| interrupts = <0 2 4>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| i2c1: i2c@11100 { | |
| compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; | |
| reg = <0x11100 0x20>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| interrupts = <0 3 4>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| uart0: serial@12000 { | |
| compatible = "marvell,armada-38x-uart", "ns16550a"; | |
| reg = <0x12000 0x100>; | |
| reg-shift = <2>; | |
| interrupts = <0 12 4>; | |
| reg-io-width = <1>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| uart1: serial@12100 { | |
| compatible = "marvell,armada-38x-uart", "ns16550a"; | |
| reg = <0x12100 0x100>; | |
| reg-shift = <2>; | |
| interrupts = <0 13 4>; | |
| reg-io-width = <1>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| pinctrl: pinctrl@18000 { | |
| reg = <0x18000 0x20>; | |
| ge0_rgmii_pins: ge-rgmii-pins-0 { | |
| marvell,pins = "mpp6", "mpp7", "mpp8", | |
| "mpp9", "mpp10", "mpp11", | |
| "mpp12", "mpp13", "mpp14", | |
| "mpp15", "mpp16", "mpp17"; | |
| marvell,function = "ge0"; | |
| }; | |
| ge1_rgmii_pins: ge-rgmii-pins-1 { | |
| marvell,pins = "mpp21", "mpp27", "mpp28", | |
| "mpp29", "mpp30", "mpp31", | |
| "mpp32", "mpp37", "mpp38", | |
| "mpp39", "mpp40", "mpp41"; | |
| marvell,function = "ge1"; | |
| }; | |
| i2c0_pins: i2c-pins-0 { | |
| marvell,pins = "mpp2", "mpp3"; | |
| marvell,function = "i2c0"; | |
| }; | |
| mdio_pins: mdio-pins { | |
| marvell,pins = "mpp4", "mpp5"; | |
| marvell,function = "ge"; | |
| }; | |
| ref_clk0_pins: ref-clk-pins-0 { | |
| marvell,pins = "mpp45"; | |
| marvell,function = "ref"; | |
| }; | |
| ref_clk1_pins: ref-clk-pins-1 { | |
| marvell,pins = "mpp46"; | |
| marvell,function = "ref"; | |
| }; | |
| spi0_pins: spi-pins-0 { | |
| marvell,pins = "mpp22", "mpp23", "mpp24", | |
| "mpp25"; | |
| marvell,function = "spi0"; | |
| }; | |
| spi1_pins: spi-pins-1 { | |
| marvell,pins = "mpp56", "mpp57", "mpp58", | |
| "mpp59"; | |
| marvell,function = "spi1"; | |
| }; | |
| nand_pins: nand-pins { | |
| marvell,pins = "mpp22", "mpp34", "mpp23", | |
| "mpp33", "mpp38", "mpp28", | |
| "mpp40", "mpp42", "mpp35", | |
| "mpp36", "mpp25", "mpp30", | |
| "mpp32"; | |
| marvell,function = "dev"; | |
| }; | |
| nand_rb: nand-rb { | |
| marvell,pins = "mpp41"; | |
| marvell,function = "nand"; | |
| }; | |
| uart0_pins: uart-pins-0 { | |
| marvell,pins = "mpp0", "mpp1"; | |
| marvell,function = "ua0"; | |
| }; | |
| uart1_pins: uart-pins-1 { | |
| marvell,pins = "mpp19", "mpp20"; | |
| marvell,function = "ua1"; | |
| }; | |
| sdhci_pins: sdhci-pins { | |
| marvell,pins = "mpp48", "mpp49", "mpp50", | |
| "mpp52", "mpp53", "mpp54", | |
| "mpp55", "mpp57", "mpp58", | |
| "mpp59"; | |
| marvell,function = "sd0"; | |
| }; | |
| sata0_pins: sata-pins-0 { | |
| marvell,pins = "mpp20"; | |
| marvell,function = "sata0"; | |
| }; | |
| sata1_pins: sata-pins-1 { | |
| marvell,pins = "mpp19"; | |
| marvell,function = "sata1"; | |
| }; | |
| sata2_pins: sata-pins-2 { | |
| marvell,pins = "mpp47"; | |
| marvell,function = "sata2"; | |
| }; | |
| sata3_pins: sata-pins-3 { | |
| marvell,pins = "mpp44"; | |
| marvell,function = "sata3"; | |
| }; | |
| i2s_pins: i2s-pins { | |
| marvell,pins = "mpp48", "mpp49", | |
| "mpp50", "mpp51", | |
| "mpp52", "mpp53"; | |
| marvell,function = "audio"; | |
| }; | |
| spdif_pins: spdif-pins { | |
| marvell,pins = "mpp51"; | |
| marvell,function = "audio"; | |
| }; | |
| }; | |
| gpio0: gpio@18100 { | |
| compatible = "marvell,armada-370-gpio", | |
| "marvell,orion-gpio"; | |
| reg = <0x18100 0x40>, <0x181c0 0x08>; | |
| reg-names = "gpio", "pwm"; | |
| ngpios = <32>; | |
| gpio-controller; | |
| gpio-ranges = <&pinctrl 0 0 32>; | |
| #gpio-cells = <2>; | |
| #pwm-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupts = <0 53 4>, | |
| <0 54 4>, | |
| <0 55 4>, | |
| <0 56 4>; | |
| clocks = <&coreclk 0>; | |
| }; | |
| gpio1: gpio@18140 { | |
| compatible = "marvell,armada-370-gpio", | |
| "marvell,orion-gpio"; | |
| reg = <0x18140 0x40>, <0x181c8 0x08>; | |
| reg-names = "gpio", "pwm"; | |
| ngpios = <28>; | |
| gpio-controller; | |
| gpio-ranges = <&pinctrl 0 32 28>; | |
| #gpio-cells = <2>; | |
| #pwm-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupts = <0 58 4>, | |
| <0 59 4>, | |
| <0 60 4>, | |
| <0 61 4>; | |
| clocks = <&coreclk 0>; | |
| }; | |
| systemc: system-controller@18200 { | |
| compatible = "marvell,armada-380-system-controller", | |
| "marvell,armada-370-xp-system-controller"; | |
| reg = <0x18200 0x100>; | |
| }; | |
| gateclk: clock-gating-control@18220 { | |
| compatible = "marvell,armada-380-gating-clock"; | |
| reg = <0x18220 0x4>; | |
| clocks = <&coreclk 0>; | |
| #clock-cells = <1>; | |
| }; | |
| comphy: phy@18300 { | |
| compatible = "marvell,armada-380-comphy"; | |
| reg-names = "comphy", "conf"; | |
| reg = <0x18300 0x100>, <0x18460 4>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| comphy0: phy@0 { | |
| reg = <0>; | |
| #phy-cells = <1>; | |
| }; | |
| comphy1: phy@1 { | |
| reg = <1>; | |
| #phy-cells = <1>; | |
| }; | |
| comphy2: phy@2 { | |
| reg = <2>; | |
| #phy-cells = <1>; | |
| }; | |
| comphy3: phy@3 { | |
| reg = <3>; | |
| #phy-cells = <1>; | |
| }; | |
| comphy4: phy@4 { | |
| reg = <4>; | |
| #phy-cells = <1>; | |
| }; | |
| comphy5: phy@5 { | |
| reg = <5>; | |
| #phy-cells = <1>; | |
| }; | |
| }; | |
| coreclk: mvebu-sar@18600 { | |
| compatible = "marvell,armada-380-core-clock"; | |
| reg = <0x18600 0x04>; | |
| #clock-cells = <1>; | |
| }; | |
| mbusc: mbus-controller@20000 { | |
| compatible = "marvell,mbus-controller"; | |
| reg = <0x20000 0x100>, <0x20180 0x20>, | |
| <0x20250 0x8>; | |
| }; | |
| mpic: interrupt-controller@20a00 { | |
| compatible = "marvell,mpic"; | |
| reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
| #interrupt-cells = <1>; | |
| #size-cells = <1>; | |
| interrupt-controller; | |
| msi-controller; | |
| interrupts = <1 15 4>; | |
| }; | |
| timer: timer@20300 { | |
| compatible = "marvell,armada-380-timer", | |
| "marvell,armada-xp-timer"; | |
| reg = <0x20300 0x30>, <0x21040 0x30>; | |
| interrupts-extended = <&gic 0 8 4>, | |
| <&gic 0 9 4>, | |
| <&gic 0 10 4>, | |
| <&gic 0 11 4>, | |
| <&mpic 5>, | |
| <&mpic 6>; | |
| clocks = <&coreclk 2>, <&refclk>; | |
| clock-names = "nbclk", "fixed"; | |
| }; | |
| watchdog: watchdog@20300 { | |
| compatible = "marvell,armada-380-wdt"; | |
| reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; | |
| clocks = <&coreclk 2>, <&refclk>; | |
| clock-names = "nbclk", "fixed"; | |
| interrupts-extended = <&gic 0 64 4>, | |
| <&gic 0 9 4>; | |
| }; | |
| cpurst: cpurst@20800 { | |
| compatible = "marvell,armada-370-cpu-reset"; | |
| reg = <0x20800 0x10>; | |
| }; | |
| mpcore-soc-ctrl@20d20 { | |
| compatible = "marvell,armada-380-mpcore-soc-ctrl"; | |
| reg = <0x20d20 0x6c>; | |
| }; | |
| coherencyfab: coherency-fabric@21010 { | |
| compatible = "marvell,armada-380-coherency-fabric"; | |
| reg = <0x21010 0x1c>; | |
| }; | |
| pmsu: pmsu@22000 { | |
| compatible = "marvell,armada-380-pmsu"; | |
| reg = <0x22000 0x1000>; | |
| }; | |
| # 472 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-38x.dtsi" | |
| eth0: ethernet@70000 { | |
| compatible = "marvell,armada-370-neta"; | |
| reg = <0x70000 0x4000>; | |
| interrupts-extended = <&mpic 8>; | |
| clocks = <&gateclk 4>; | |
| tx-csum-limit = <9800>; | |
| status = "disabled"; | |
| }; | |
| eth1: ethernet@30000 { | |
| compatible = "marvell,armada-370-neta"; | |
| reg = <0x30000 0x4000>; | |
| interrupts-extended = <&mpic 10>; | |
| clocks = <&gateclk 3>; | |
| status = "disabled"; | |
| }; | |
| eth2: ethernet@34000 { | |
| compatible = "marvell,armada-370-neta"; | |
| reg = <0x34000 0x4000>; | |
| interrupts-extended = <&mpic 12>; | |
| clocks = <&gateclk 2>; | |
| status = "disabled"; | |
| }; | |
| usb0: usb@58000 { | |
| compatible = "marvell,orion-ehci"; | |
| reg = <0x58000 0x500>; | |
| interrupts = <0 18 4>; | |
| clocks = <&gateclk 18>; | |
| status = "disabled"; | |
| }; | |
| xor0: xor@60800 { | |
| compatible = "marvell,armada-380-xor", "marvell,orion-xor"; | |
| reg = <0x60800 0x100 | |
| 0x60a00 0x100>; | |
| clocks = <&gateclk 22>; | |
| status = "okay"; | |
| xor00 { | |
| interrupts = <0 22 4>; | |
| dmacap,memcpy; | |
| dmacap,xor; | |
| }; | |
| xor01 { | |
| interrupts = <0 23 4>; | |
| dmacap,memcpy; | |
| dmacap,xor; | |
| dmacap,memset; | |
| }; | |
| }; | |
| xor1: xor@60900 { | |
| compatible = "marvell,armada-380-xor", "marvell,orion-xor"; | |
| reg = <0x60900 0x100 | |
| 0x60b00 0x100>; | |
| clocks = <&gateclk 28>; | |
| status = "okay"; | |
| xor10 { | |
| interrupts = <0 65 4>; | |
| dmacap,memcpy; | |
| dmacap,xor; | |
| }; | |
| xor11 { | |
| interrupts = <0 66 4>; | |
| dmacap,memcpy; | |
| dmacap,xor; | |
| dmacap,memset; | |
| }; | |
| }; | |
| mdio: mdio@72004 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "marvell,orion-mdio"; | |
| reg = <0x72004 0x4>; | |
| clocks = <&gateclk 4>; | |
| }; | |
| cesa: crypto@90000 { | |
| compatible = "marvell,armada-38x-crypto"; | |
| reg = <0x90000 0x10000>; | |
| reg-names = "regs"; | |
| interrupts = <0 19 4>, | |
| <0 20 4>; | |
| clocks = <&gateclk 23>, <&gateclk 21>, | |
| <&gateclk 14>, <&gateclk 16>; | |
| clock-names = "cesa0", "cesa1", | |
| "cesaz0", "cesaz1"; | |
| marvell,crypto-srams = <&crypto_sram0>, | |
| <&crypto_sram1>; | |
| marvell,crypto-sram-size = <0x800>; | |
| }; | |
| rtc: rtc@a3800 { | |
| compatible = "marvell,armada-380-rtc"; | |
| reg = <0xa3800 0x20>, <0x184a0 0x0c>; | |
| reg-names = "rtc", "rtc-soc"; | |
| interrupts = <0 21 4>; | |
| }; | |
| ahci0: sata@a8000 { | |
| compatible = "marvell,armada-380-ahci"; | |
| reg = <0xa8000 0x2000>; | |
| interrupts = <0 26 4>; | |
| clocks = <&gateclk 15>; | |
| status = "disabled"; | |
| }; | |
| bm: bm@c8000 { | |
| compatible = "marvell,armada-380-neta-bm"; | |
| reg = <0xc8000 0xac>; | |
| clocks = <&gateclk 13>; | |
| internal-mem = <&bm_bppi>; | |
| status = "disabled"; | |
| }; | |
| ahci1: sata@e0000 { | |
| compatible = "marvell,armada-380-ahci"; | |
| reg = <0xe0000 0x2000>; | |
| interrupts = <0 28 4>; | |
| clocks = <&gateclk 30>; | |
| status = "disabled"; | |
| }; | |
| coredivclk: clock@e4250 { | |
| compatible = "marvell,armada-380-corediv-clock"; | |
| reg = <0xe4250 0xc>; | |
| #clock-cells = <1>; | |
| clocks = <&mainpll>; | |
| clock-output-names = "nand"; | |
| }; | |
| thermal: thermal@e8078 { | |
| compatible = "marvell,armada380-thermal"; | |
| reg = <0xe4078 0x4>, <0xe4070 0x8>; | |
| status = "okay"; | |
| }; | |
| nand_controller: nand-controller@d0000 { | |
| compatible = "marvell,armada370-nand-controller"; | |
| reg = <0xd0000 0x54>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| interrupts = <0 84 4>; | |
| clocks = <&coredivclk 0>; | |
| status = "disabled"; | |
| }; | |
| sdhci: sdhci@d8000 { | |
| compatible = "marvell,armada-380-sdhci"; | |
| reg-names = "sdhci", "mbus", "conf-sdio3"; | |
| reg = <0xd8000 0x1000>, | |
| <0xdc000 0x100>, | |
| <0x18454 0x4>; | |
| interrupts = <0 25 4>; | |
| clocks = <&gateclk 17>; | |
| mrvl,clk-delay-cycles = <0x1F>; | |
| status = "disabled"; | |
| }; | |
| audio_controller: audio-controller@e8000 { | |
| #sound-dai-cells = <1>; | |
| compatible = "marvell,armada-380-audio"; | |
| reg = <0xe8000 0x4000>, <0x18410 0xc>, | |
| <0x18204 0x4>; | |
| reg-names = "i2s_regs", "pll_regs", "soc_ctrl"; | |
| interrupts = <0 75 4>; | |
| clocks = <&gateclk 0>; | |
| clock-names = "internal"; | |
| status = "disabled"; | |
| }; | |
| usb3_0: usb3@f0000 { | |
| compatible = "marvell,armada-380-xhci"; | |
| reg = <0xf0000 0x4000>,<0xf4000 0x4000>; | |
| interrupts = <0 16 4>; | |
| clocks = <&gateclk 9>; | |
| status = "disabled"; | |
| }; | |
| usb3_1: usb3@f8000 { | |
| compatible = "marvell,armada-380-xhci"; | |
| reg = <0xf8000 0x4000>,<0xfc000 0x4000>; | |
| interrupts = <0 17 4>; | |
| clocks = <&gateclk 10>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| crypto_sram0: sa-sram0 { | |
| compatible = "mmio-sram"; | |
| reg = <(((0x09) << 24) | ((0x19) << 16)) 0 0x800>; | |
| clocks = <&gateclk 23>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0 (((0x09) << 24) | ((0x19) << 16)) 0 0x800>; | |
| }; | |
| crypto_sram1: sa-sram1 { | |
| compatible = "mmio-sram"; | |
| reg = <(((0x09) << 24) | ((0x15) << 16)) 0 0x800>; | |
| clocks = <&gateclk 21>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0 (((0x09) << 24) | ((0x15) << 16)) 0 0x800>; | |
| }; | |
| bm_bppi: bm-bppi { | |
| compatible = "mmio-sram"; | |
| reg = <(((0x0c) << 24) | ((0x04) << 16)) 0 0x100000>; | |
| ranges = <0 (((0x0c) << 24) | ((0x04) << 16)) 0 0x100000>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| clocks = <&gateclk 13>; | |
| no-memory-wc; | |
| status = "disabled"; | |
| }; | |
| spi0: spi@10600 { | |
| compatible = "marvell,armada-380-spi", | |
| "marvell,orion-spi"; | |
| reg = <(((0xf0) << 24) | ((0x01) << 16)) 0x10600 0x50>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| cell-index = <0>; | |
| interrupts = <0 1 4>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| spi1: spi@10680 { | |
| compatible = "marvell,armada-380-spi", | |
| "marvell,orion-spi"; | |
| reg = <(((0xf0) << 24) | ((0x01) << 16)) 0x10680 0x50>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| cell-index = <1>; | |
| interrupts = <0 63 4>; | |
| clocks = <&coreclk 0>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| clocks { | |
| mainpll: mainpll { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <1000000000>; | |
| }; | |
| refclk: oscillator { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <25000000>; | |
| }; | |
| }; | |
| }; | |
| # 13 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385.dtsi" 2 | |
| / { | |
| model = "Marvell Armada 385 family SoC"; | |
| compatible = "marvell,armada385", "marvell,armada380"; | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| enable-method = "marvell,armada-380-smp"; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9"; | |
| reg = <0>; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9"; | |
| reg = <1>; | |
| }; | |
| }; | |
| soc { | |
| pciec: pcie { | |
| compatible = "marvell,armada-370-pcie"; | |
| status = "disabled"; | |
| device_type = "pci"; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| msi-parent = <&mpic>; | |
| bus-range = <0x00 0xff>; | |
| ranges = | |
| <0x82000000 0 0x80000 (((0xf0) << 24) | ((0x01) << 16)) 0x80000 0 0x00002000 | |
| 0x82000000 0 0x40000 (((0xf0) << 24) | ((0x01) << 16)) 0x40000 0 0x00002000 | |
| 0x82000000 0 0x44000 (((0xf0) << 24) | ((0x01) << 16)) 0x44000 0 0x00002000 | |
| 0x82000000 0 0x48000 (((0xf0) << 24) | ((0x01) << 16)) 0x48000 0 0x00002000 | |
| 0x82000000 0x1 0 (((0x08) << 24) | ((0xe8) << 16)) 0 1 0 | |
| 0x81000000 0x1 0 (((0x08) << 24) | ((0xe0) << 16)) 0 1 0 | |
| 0x82000000 0x2 0 (((0x04) << 24) | ((0xe8) << 16)) 0 1 0 | |
| 0x81000000 0x2 0 (((0x04) << 24) | ((0xe0) << 16)) 0 1 0 | |
| 0x82000000 0x3 0 (((0x04) << 24) | ((0xd8) << 16)) 0 1 0 | |
| 0x81000000 0x3 0 (((0x04) << 24) | ((0xd0) << 16)) 0 1 0 | |
| 0x82000000 0x4 0 (((0x04) << 24) | ((0xb8) << 16)) 0 1 0 | |
| 0x81000000 0x4 0 (((0x04) << 24) | ((0xb0) << 16)) 0 1 0 >; | |
| pcie1: pcie@1,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | |
| reg = <0x0800 0 0 0 0>; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| interrupt-names = "intx"; | |
| interrupts-extended = <&gic 0 29 4>; | |
| #interrupt-cells = <1>; | |
| ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
| 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
| bus-range = <0x00 0xff>; | |
| interrupt-map-mask = <0 0 0 7>; | |
| interrupt-map = <0 0 0 1 &pcie1_intc 0>, | |
| <0 0 0 2 &pcie1_intc 1>, | |
| <0 0 0 3 &pcie1_intc 2>, | |
| <0 0 0 4 &pcie1_intc 3>; | |
| marvell,pcie-port = <0>; | |
| marvell,pcie-lane = <0>; | |
| clocks = <&gateclk 8>; | |
| status = "disabled"; | |
| pcie1_intc: interrupt-controller { | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| }; | |
| }; | |
| pcie2: pcie@2,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; | |
| reg = <0x1000 0 0 0 0>; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| interrupt-names = "intx"; | |
| interrupts-extended = <&gic 0 33 4>; | |
| #interrupt-cells = <1>; | |
| ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
| 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
| bus-range = <0x00 0xff>; | |
| interrupt-map-mask = <0 0 0 7>; | |
| interrupt-map = <0 0 0 1 &pcie2_intc 0>, | |
| <0 0 0 2 &pcie2_intc 1>, | |
| <0 0 0 3 &pcie2_intc 2>, | |
| <0 0 0 4 &pcie2_intc 3>; | |
| marvell,pcie-port = <1>; | |
| marvell,pcie-lane = <0>; | |
| clocks = <&gateclk 5>; | |
| status = "disabled"; | |
| pcie2_intc: interrupt-controller { | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| }; | |
| }; | |
| pcie3: pcie@3,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; | |
| reg = <0x1800 0 0 0 0>; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| interrupt-names = "intx"; | |
| interrupts-extended = <&gic 0 70 4>; | |
| #interrupt-cells = <1>; | |
| ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | |
| 0x81000000 0 0 0x81000000 0x3 0 1 0>; | |
| bus-range = <0x00 0xff>; | |
| interrupt-map-mask = <0 0 0 7>; | |
| interrupt-map = <0 0 0 1 &pcie3_intc 0>, | |
| <0 0 0 2 &pcie3_intc 1>, | |
| <0 0 0 3 &pcie3_intc 2>, | |
| <0 0 0 4 &pcie3_intc 3>; | |
| marvell,pcie-port = <2>; | |
| marvell,pcie-lane = <0>; | |
| clocks = <&gateclk 6>; | |
| status = "disabled"; | |
| pcie3_intc: interrupt-controller { | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| }; | |
| }; | |
| pcie4: pcie@4,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; | |
| reg = <0x2000 0 0 0 0>; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| interrupt-names = "intx"; | |
| interrupts-extended = <&gic 0 71 4>; | |
| #interrupt-cells = <1>; | |
| ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | |
| 0x81000000 0 0 0x81000000 0x4 0 1 0>; | |
| bus-range = <0x00 0xff>; | |
| interrupt-map-mask = <0 0 0 7>; | |
| interrupt-map = <0 0 0 1 &pcie4_intc 0>, | |
| <0 0 0 2 &pcie4_intc 1>, | |
| <0 0 0 3 &pcie4_intc 2>, | |
| <0 0 0 4 &pcie4_intc 3>; | |
| marvell,pcie-port = <3>; | |
| marvell,pcie-lane = <0>; | |
| clocks = <&gateclk 7>; | |
| status = "disabled"; | |
| pcie4_intc: interrupt-controller { | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| &pinctrl { | |
| compatible = "marvell,mv88f6820-pinctrl"; | |
| }; | |
| # 9 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi" 2 | |
| / { | |
| aliases { | |
| led-boot = &led_status_green; | |
| led-failsafe = &led_status_red; | |
| led-running = &led_status_green; | |
| led-upgrade = &led_status_green; | |
| label-mac-device = ð0; | |
| }; | |
| chosen { | |
| stdout-path = "serial0:9600n8"; | |
| }; | |
| soc { | |
| ranges = <(((0xf0) << 24) | ((0x01) << 16)) 0 0xf1000000 0x100000 | |
| (((0x01) << 24) | ((0x1d) << 16)) 0 0xfff00000 0x100000 | |
| (((0x09) << 24) | ((0x19) << 16)) 0 0xf1100000 0x10000 | |
| (((0x09) << 24) | ((0x15) << 16)) 0 0xf1110000 0x10000 | |
| (((0x0c) << 24) | ((0x04) << 16)) 0 0xf1200000 0x100000>; | |
| }; | |
| gpio-keys { | |
| compatible = "gpio-keys"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pmx_gpio_keys_pins>; | |
| reset { | |
| label = "reset"; | |
| linux,code = <0x198>; | |
| gpios = <&gpio1 22 1>; | |
| }; | |
| }; | |
| gpio_leds: gpio-leds { | |
| compatible = "gpio-leds"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pmx_gpio_leds_pins>; | |
| led-0 { | |
| gpios = <&gpio0 30 1>; | |
| color = <1>; | |
| function = "alarm"; | |
| }; | |
| led-1 { | |
| gpios = <&gpio1 0 1>; | |
| color = <1>; | |
| function = "ha"; | |
| }; | |
| led_status_green: led-2 { | |
| gpios = <&gpio1 1 1>; | |
| color = <2>; | |
| function = "status"; | |
| }; | |
| led-3 { | |
| gpios = <&gpio1 3 1>; | |
| color = <2>; | |
| function = "ha"; | |
| }; | |
| led-4 { | |
| gpios = <&gpio1 13 1>; | |
| color = <4>; | |
| function = "alarm"; | |
| }; | |
| led_status_red: led-5 { | |
| gpios = <&gpio1 15 1>; | |
| color = <1>; | |
| function = "status"; | |
| }; | |
| led-6 { | |
| gpios = <&gpio2 4 1>; | |
| color = <2>; | |
| function = "speed-lan"; | |
| function-enumerator = <4>; | |
| linux,default-trigger = "mv88e6xxx-0:01:1Gbps"; | |
| }; | |
| led-7 { | |
| gpios = <&gpio2 5 1>; | |
| color = <4>; | |
| function = "speed-lan"; | |
| function-enumerator = <4>; | |
| linux,default-trigger = "mv88e6xxx-0:01:100Mbps"; | |
| }; | |
| led-8 { | |
| gpios = <&gpio2 6 1>; | |
| color = <4>; | |
| function = "speed-lan"; | |
| function-enumerator = <3>; | |
| linux,default-trigger = "mv88e6xxx-0:02:100Mbps"; | |
| }; | |
| led-9 { | |
| gpios = <&gpio2 7 1>; | |
| color = <2>; | |
| function = "speed-lan"; | |
| function-enumerator = <3>; | |
| linux,default-trigger = "mv88e6xxx-0:02:1Gbps"; | |
| }; | |
| led-10 { | |
| gpios = <&gpio2 12 1>; | |
| color = <2>; | |
| function = "speed-lan"; | |
| function-enumerator = <1>; | |
| linux,default-trigger = "mv88e6xxx-0:04:1Gbps"; | |
| }; | |
| led-11 { | |
| gpios = <&gpio2 13 1>; | |
| color = <4>; | |
| function = "speed-lan"; | |
| function-enumerator = <1>; | |
| linux,default-trigger = "mv88e6xxx-0:04:100Mbps"; | |
| }; | |
| led-12 { | |
| gpios = <&gpio2 14 1>; | |
| color = <2>; | |
| function = "speed-lan"; | |
| function-enumerator = <2>; | |
| linux,default-trigger = "mv88e6xxx-0:03:1Gbps"; | |
| }; | |
| led-13 { | |
| gpios = <&gpio2 15 1>; | |
| color = <4>; | |
| function = "speed-lan"; | |
| function-enumerator = <2>; | |
| linux,default-trigger = "mv88e6xxx-0:03:100Mbps"; | |
| }; | |
| }; | |
| reg_usb_vbus: regulator-usb-vbus { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "usb-vbus"; | |
| regulator-min-microvolt = <5000000>; | |
| regulator-max-microvolt = <5000000>; | |
| gpios = <&gpio1 21 1>; | |
| regulator-always-on; | |
| }; | |
| }; | |
| &i2c0 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&i2c0_pins>; | |
| status = "okay"; | |
| gpio2: gpio@24 { | |
| compatible = "nxp,pca9555"; | |
| reg = <0x24>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| }; | |
| hwmon@28 { | |
| compatible = "nuvoton,nct7802"; | |
| reg = <0x28>; | |
| }; | |
| }; | |
| &uart0 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&uart0_pins>; | |
| status = "okay"; | |
| }; | |
| &pinctrl { | |
| pmx_gpio_leds_pins: gpio-leds-pins { | |
| marvell,pins = "mpp30", "mpp32", "mpp33", "mpp35", | |
| "mpp45", "mpp47"; | |
| marvell,function = "gpio"; | |
| }; | |
| pmx_usb_pins: usb-pins { | |
| marvell,pins = "mpp53"; | |
| marvell,function = "gpio"; | |
| }; | |
| pmx_gpio_keys_pins: gpio-keys-pins { | |
| marvell,pins = "mpp54"; | |
| marvell,function = "gpio"; | |
| }; | |
| }; | |
| &bm { | |
| status = "okay"; | |
| }; | |
| &bm_bppi { | |
| status = "okay"; | |
| }; | |
| ð0 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&ge0_rgmii_pins>; | |
| status = "okay"; | |
| phy-connection-type = "rgmii-id"; | |
| buffer-manager = <&bm>; | |
| bm,pool-long = <0>; | |
| bm,pool-short = <1>; | |
| nvmem-cells = <&macaddr_bdinfo_d880 0>; | |
| nvmem-cell-names = "mac-address"; | |
| fixed-link { | |
| speed = <1000>; | |
| full-duplex; | |
| }; | |
| }; | |
| &usb3_0 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pmx_usb_pins>; | |
| status = "okay"; | |
| vbus-supply = <®_usb_vbus>; | |
| }; | |
| &spi1 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&spi1_pins>; | |
| status = "okay"; | |
| flash@0 { | |
| compatible = "jedec,spi-nor"; | |
| reg = <0>; | |
| spi-max-frequency = <50000000>; | |
| partitions { | |
| compatible = "fixed-partitions"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| partition@0 { | |
| reg = <0x0 0x1c0000>; | |
| label = "u-boot"; | |
| read-only; | |
| }; | |
| partition@1c0000 { | |
| reg = <0x1c0000 0x10000>; | |
| label = "firmware-info"; | |
| # 273 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi" | |
| }; | |
| partition@1d0000 { | |
| reg = <0x1d0000 0x10000>; | |
| label = "dtb"; | |
| read-only; | |
| }; | |
| partition@1e0000 { | |
| reg = <0x1e0000 0x10000>; | |
| label = "u-boot-env"; | |
| read-only; | |
| }; | |
| partition@1f0000 { | |
| reg = <0x1f0000 0x10000>; | |
| label = "board-info"; | |
| read-only; | |
| nvmem-layout { | |
| compatible = "fixed-layout"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| macaddr_bdinfo_d880: macaddr@d880 { | |
| compatible = "mac-base"; | |
| reg = <0xd880 0x6>; | |
| #nvmem-cell-cells = <1>; | |
| }; | |
| }; | |
| }; | |
| partition@200000 { | |
| reg = <0x200000 0x600000>; | |
| label = "kernel"; | |
| }; | |
| partition@800000 { | |
| reg = <0x800000 0x1800000>; | |
| label = "rootfs"; | |
| }; | |
| partition@2000000 { | |
| reg = <0x2000000 0x600000>; | |
| label = "kn2"; | |
| read-only; | |
| }; | |
| partition@2600000 { | |
| reg = <0x2600000 0x1800000>; | |
| label = "rfs2"; | |
| read-only; | |
| }; | |
| partition@3e00000 { | |
| reg = <0x3e00000 0x1200000>; | |
| label = "part1"; | |
| read-only; | |
| }; | |
| partition@5000000 { | |
| reg = <0x5000000 0x1200000>; | |
| label = "part2"; | |
| read-only; | |
| }; | |
| partition@6200000 { | |
| reg = <0x6200000 0x1e00000>; | |
| label = "config"; | |
| read-only; | |
| }; | |
| }; | |
| }; | |
| }; | |
| # 4 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi" 2 | |
| / { | |
| memory@0 { | |
| device_type = "memory"; | |
| reg = <0x00000000 0x80000000>; | |
| }; | |
| }; | |
| &gpio_leds { | |
| led-14 { | |
| gpios = <&gpio2 0 0>; | |
| color = <2>; | |
| function = "speed-wan"; | |
| function-enumerator = <1>; | |
| linux,default-trigger = "f1072004.mdio-mii:00:1Gbps"; | |
| }; | |
| led-15 { | |
| gpios = <&gpio2 1 0>; | |
| color = <2>; | |
| function = "speed-wan"; | |
| function-enumerator = <2>; | |
| linux,default-trigger = "f1072004.mdio-mii:01:1Gbps"; | |
| }; | |
| led-16 { | |
| gpios = <&gpio2 2 0>; | |
| color = <4>; | |
| function = "speed-lan"; | |
| function-enumerator = <5>; | |
| linux,default-trigger = "mv88e6xxx-0:00:100Mbps"; | |
| }; | |
| led-17 { | |
| gpios = <&gpio2 3 0>; | |
| color = <2>; | |
| function = "speed-lan"; | |
| function-enumerator = <5>; | |
| linux,default-trigger = "mv88e6xxx-0:00:1Gbps"; | |
| }; | |
| }; | |
| &pinctrl { | |
| pmx_phy_switch_pins: phy-switch-pins { | |
| marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41"; | |
| marvell,function = "gpio"; | |
| }; | |
| }; | |
| ð1 { | |
| status = "okay"; | |
| phy-handle = <ðphy0>; | |
| phy-connection-type = "sgmii"; | |
| buffer-manager = <&bm>; | |
| bm,pool-long = <2>; | |
| nvmem-cells = <&macaddr_bdinfo_d880 1>; | |
| nvmem-cell-names = "mac-address"; | |
| }; | |
| ð2 { | |
| status = "okay"; | |
| phy-handle = <ðphy1>; | |
| phy-connection-type = "sgmii"; | |
| buffer-manager = <&bm>; | |
| bm,pool-long = <3>; | |
| nvmem-cells = <&macaddr_bdinfo_d880 2>; | |
| nvmem-cell-names = "mac-address"; | |
| }; | |
| &mdio { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>; | |
| ethphy0: ethernet-phy@0 { | |
| compatible = "ethernet-phy-id0141,0dd1", | |
| "ethernet-phy-ieee802.3-c22"; | |
| reg = <0x0>; | |
| interrupt-parent = <&gpio0>; | |
| interrupts = <20 8>; | |
| reset-gpios = <&gpio0 23 1>; | |
| reset-assert-us = <10000>; | |
| reset-deassert-us = <10000>; | |
| marvell,reg-init = <3 16 0 0x71>, | |
| <3 17 0 0x4>; | |
| }; | |
| ethphy1: ethernet-phy@1 { | |
| compatible = "ethernet-phy-id0141,0dd1", | |
| "ethernet-phy-ieee802.3-c22"; | |
| reg = <0x1>; | |
| interrupt-parent = <&gpio1>; | |
| interrupts = <9 8>; | |
| reset-gpios = <&gpio1 2 1>; | |
| reset-assert-us = <10000>; | |
| reset-deassert-us = <10000>; | |
| marvell,reg-init = <3 16 0 0x71>, | |
| <3 17 0 0x4>; | |
| }; | |
| switch@2 { | |
| compatible = "marvell,mv88e6085"; | |
| reg = <0x2>; | |
| reset-gpios = <&gpio0 19 1>; | |
| ports { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| port@0 { | |
| reg = <0>; | |
| label = "lan5"; | |
| nvmem-cells = <&macaddr_bdinfo_d880 7>; | |
| nvmem-cell-names = "mac-address"; | |
| }; | |
| port@1 { | |
| reg = <1>; | |
| label = "lan4"; | |
| nvmem-cells = <&macaddr_bdinfo_d880 6>; | |
| nvmem-cell-names = "mac-address"; | |
| }; | |
| port@2 { | |
| reg = <2>; | |
| label = "lan3"; | |
| nvmem-cells = <&macaddr_bdinfo_d880 5>; | |
| nvmem-cell-names = "mac-address"; | |
| }; | |
| port@3 { | |
| reg = <3>; | |
| label = "lan2"; | |
| nvmem-cells = <&macaddr_bdinfo_d880 4>; | |
| nvmem-cell-names = "mac-address"; | |
| }; | |
| port@4 { | |
| reg = <4>; | |
| label = "lan1"; | |
| nvmem-cells = <&macaddr_bdinfo_d880 3>; | |
| nvmem-cell-names = "mac-address"; | |
| }; | |
| port@6 { | |
| reg = <6>; | |
| ethernet = <ð0>; | |
| phy-connection-type = "rgmii-id"; | |
| fixed-link { | |
| speed = <1000>; | |
| full-duplex; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| # 4 "/home/miminashi/src/openwrt/build_dir/target-arm_cortex-a9+vfpv3-d16_musl_eabi/linux-mvebu_cortexa9/linux-6.6.60/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts" 2 | |
| / { | |
| model = "Fortinet FortiGate 50E"; | |
| compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380"; | |
| }; |
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