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Raw
Example
$ verilator targets_InstanceChoiceProbe_Platform_ASIC.svh ref_InstanceChoiceProbe.sv InstanceChoiceProbe.sv ASICDeep.sv ASICMiddle.sv ASICTarget.sv --lint-only -top InstanceChoiceProbe
- V e r i l a t i o n R e p o r t: Verilator 5.044 2026-01-01 rev v5.044
- Verilator: Built from 0.119 MB sources in 6 modules, into 0.003 MB in 3 C++ files needing 0.000 MB
- Verilator: Walltime 0.006 s (elab=0.000, cvt=0.001, bld=0.000); cpu 0.004 s on 1 threads; alloced 25.148 MB
$ verilator targets_InstanceChoiceProbe_Platform_FPGA.svh ref_InstanceChoiceProbe.sv InstanceChoiceProbe.sv ASICDeep.sv ASICMiddle.sv ASICTarget.sv --lint-only -top InstanceChoiceProbe
- V e r i l a t i o n R e p o r t: Verilator 5.044 2026-01-01 rev v5.044
- Verilator: Built from 0.104 MB sources in 7 modules, into 0.003 MB in 3 C++ files needing 0.000 MB
- Verilator: Walltime 0.004 s (elab=0.000, cvt=0.001, bld=0.000); cpu 0.004 s on 1 threads; alloced 25.148 MB
$ verilator targets_InstanceChoiceProbe_Platform_ASIC.svh targets_InstanceChoiceProbe_Platform_FPGA.svh ref_InstanceChoiceProbe.sv InstanceChoiceProbe.sv ASICDeep.sv ASICMiddle.sv ASICTarget.sv --lint-only -top InstanceChoiceProbe
%Error: targets_InstanceChoiceProbe_Platform_FPGA.svh:7:3: Define or directive not defined: '`_ERROR___target_Platform_InstanceChoiceProbe_inst__must__not__be__set'
7 | `_ERROR___target_Platform_InstanceChoiceProbe_inst__must__not__be__set
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=5.044 for more assistance.
%Error: Exiting due to 1 error(s)
Raw
hw.mlir
module {
sv.macro.decl @__target_Platform_InstanceChoiceProbe_inst
sv.macro.decl @__option__Platform_ASIC
sv.macro.decl @__option__Platform_FPGA
sv.macro.decl @ref_InstanceChoiceProbe_inst_probe
hw.module private @DefaultTarget(in %clk : !seq.clock, out data : i8) {
%c0_i8 = hw.constant 0 : i8
%r_probe = hw.wire %c0_i8 sym @sym : i8
hw.output %r_probe : i8
}
hw.module private @FPGAInner() {
%c1_i8 = hw.constant 1 : i8
%r_probe = hw.wire %c1_i8 sym @sym : i8
hw.output
}
hw.module private @FPGATarget(in %clk : !seq.clock, out data : i8) {
%c1_i8 = hw.constant 1 : i8
hw.instance "inner" sym @sym @FPGAInner() -> ()
hw.output %c1_i8 : i8
}
hw.module private @ASICDeep() {
%c2_i8 = hw.constant 2 : i8
%r_probe = hw.wire %c2_i8 sym @sym : i8
hw.output
}
hw.module private @ASICMiddle() {
hw.instance "deep" sym @sym @ASICDeep() -> ()
hw.output
}
hw.module private @ASICTarget(in %clk : !seq.clock, out data : i8) {
%c2_i8 = hw.constant 2 : i8
hw.instance "middle" sym @sym @ASICMiddle() -> ()
hw.output %c2_i8 : i8
}
emit.file "ref_InstanceChoiceProbe.sv" {
sv.verbatim "`ifdef __option__Platform_FPGA\0A `define ref_InstanceChoiceProbe_inst_probe `__target_Platform_InstanceChoiceProbe_inst.inner.r_probe\0A`elsif __option__Platform_ASIC\0A `define ref_InstanceChoiceProbe_inst_probe `__target_Platform_InstanceChoiceProbe_inst.middle.deep.r_probe\0A`else\0A `define ref_InstanceChoiceProbe_inst_probe `__target_Platform_InstanceChoiceProbe_inst.r_probe\0A`endif"
}
hw.module @InstanceChoiceProbe(in %clk : !seq.clock, out data : i8, out out : i8) {
%inst.data = sv.wire : !hw.inout<i8>
%0 = sv.read_inout %inst.data : !hw.inout<i8>
sv.ifdef @__target_Platform_InstanceChoiceProbe_inst {
} else {
sv.macro.def @__target_Platform_InstanceChoiceProbe_inst "{{0}}"([#hw.innerNameRef<@InstanceChoiceProbe::@sym>])
}
sv.ifdef @__option__Platform_FPGA {
%inst.data_0 = hw.instance "inst" sym @sym_0 @FPGATarget(clk: %clk: !seq.clock) -> (data: i8)
sv.assign %inst.data, %inst.data_0 : i8
} else {
sv.ifdef @__option__Platform_ASIC {
%inst.data_0 = hw.instance "inst" sym @sym_1 @ASICTarget(clk: %clk: !seq.clock) -> (data: i8)
sv.assign %inst.data, %inst.data_0 : i8
} else {
%inst.data_0 = hw.instance "inst" sym @sym @DefaultTarget(clk: %clk: !seq.clock) -> (data: i8)
sv.assign %inst.data, %inst.data_0 : i8
}
}
%ref_InstanceChoiceProbe_inst_probe = sv.verbatim.expr.se "`ref_InstanceChoiceProbe_inst_probe" : () -> !hw.inout<i8>
%1 = sv.read_inout %ref_InstanceChoiceProbe_inst_probe : !hw.inout<i8>
hw.output %0, %1 : i8, i8
}
om.class @InstanceChoiceProbe_Class(%basepath: !om.basepath) {
om.class.fields
}
emit.file "targets_InstanceChoiceProbe_Platform_FPGA.svh" sym @targets_InstanceChoiceProbe_Platform_FPGA.svh {
emit.verbatim "// Specialization file for module: InstanceChoiceProbe\0A// Option: Platform, Case: FPGA\0A"
sv.ifdef @__option__Platform_FPGA {
} else {
sv.macro.def @__option__Platform_FPGA ""
}
sv.ifdef @__target_Platform_InstanceChoiceProbe_inst {
sv.macro.error "__target_Platform_InstanceChoiceProbe_inst__must__not__be__set"
} else {
sv.macro.def @__target_Platform_InstanceChoiceProbe_inst "{{0}}"([#hw.innerNameRef<@InstanceChoiceProbe::@sym_0>])
}
} {output_file = #hw.output_file<"targets_InstanceChoiceProbe_Platform_FPGA.svh", excludeFromFileList>}
emit.file "targets_InstanceChoiceProbe_Platform_ASIC.svh" sym @targets_InstanceChoiceProbe_Platform_ASIC.svh {
emit.verbatim "// Specialization file for module: InstanceChoiceProbe\0A// Option: Platform, Case: ASIC\0A"
sv.ifdef @__option__Platform_ASIC {
} else {
sv.macro.def @__option__Platform_ASIC ""
}
sv.ifdef @__target_Platform_InstanceChoiceProbe_inst {
sv.macro.error "__target_Platform_InstanceChoiceProbe_inst__must__not__be__set"
} else {
sv.macro.def @__target_Platform_InstanceChoiceProbe_inst "{{0}}"([#hw.innerNameRef<@InstanceChoiceProbe::@sym_1>])
}
} {output_file = #hw.output_file<"targets_InstanceChoiceProbe_Platform_ASIC.svh", excludeFromFileList>}
}
Raw
input.fir
FIRRTL version 5.1.0
circuit InstanceChoiceProbe :
option Platform : @[test_instance_choice_xmr.mlir 2:3]
FPGA @[test_instance_choice_xmr.mlir 3:5]
ASIC @[test_instance_choice_xmr.mlir 4:5]
module DefaultTarget : @[test_instance_choice_xmr.mlir 8:3]
input clk : Clock @[test_instance_choice_xmr.mlir 8:43]
output data : UInt<8> @[test_instance_choice_xmr.mlir 8:68]
output probe : Probe<UInt<8>> @[test_instance_choice_xmr.mlir 8:96]
reg r : UInt<8>, clk @[test_instance_choice_xmr.mlir 9:10]
connect r, UInt<8>(0) @[test_instance_choice_xmr.mlir 11:5]
connect data, r @[test_instance_choice_xmr.mlir 12:5]
define probe = probe(r) @[test_instance_choice_xmr.mlir 14:5]
module FPGAInner : @[test_instance_choice_xmr.mlir 18:3]
input clk : Clock @[test_instance_choice_xmr.mlir 18:39]
output data : UInt<8> @[test_instance_choice_xmr.mlir 18:64]
output probe : Probe<UInt<8>> @[test_instance_choice_xmr.mlir 18:92]
reg r : UInt<8>, clk @[test_instance_choice_xmr.mlir 19:10]
connect r, UInt<8>(1) @[test_instance_choice_xmr.mlir 21:5]
connect data, r @[test_instance_choice_xmr.mlir 22:5]
define probe = probe(r) @[test_instance_choice_xmr.mlir 24:5]
module FPGATarget : @[test_instance_choice_xmr.mlir 28:3]
input clk : Clock @[test_instance_choice_xmr.mlir 28:40]
output data : UInt<8> @[test_instance_choice_xmr.mlir 28:65]
output probe : Probe<UInt<8>> @[test_instance_choice_xmr.mlir 28:93]
inst inner of FPGAInner @[test_instance_choice_xmr.mlir 29:45]
connect inner.clk, clk @[test_instance_choice_xmr.mlir 30:5]
connect data, inner.data @[test_instance_choice_xmr.mlir 31:5]
define probe = inner.probe @[test_instance_choice_xmr.mlir 32:5]
module ASICDeep : @[test_instance_choice_xmr.mlir 36:3]
input clk : Clock @[test_instance_choice_xmr.mlir 36:38]
output data : UInt<8> @[test_instance_choice_xmr.mlir 36:63]
output probe : Probe<UInt<8>> @[test_instance_choice_xmr.mlir 36:91]
reg r : UInt<8>, clk @[test_instance_choice_xmr.mlir 37:10]
connect r, UInt<8>(2) @[test_instance_choice_xmr.mlir 39:5]
connect data, r @[test_instance_choice_xmr.mlir 40:5]
define probe = probe(r) @[test_instance_choice_xmr.mlir 42:5]
module ASICMiddle : @[test_instance_choice_xmr.mlir 46:3]
input clk : Clock @[test_instance_choice_xmr.mlir 46:40]
output data : UInt<8> @[test_instance_choice_xmr.mlir 46:65]
output probe : Probe<UInt<8>> @[test_instance_choice_xmr.mlir 46:93]
inst deep of ASICDeep @[test_instance_choice_xmr.mlir 47:42]
connect deep.clk, clk @[test_instance_choice_xmr.mlir 48:5]
connect data, deep.data @[test_instance_choice_xmr.mlir 49:5]
define probe = deep.probe @[test_instance_choice_xmr.mlir 50:5]
module ASICTarget : @[test_instance_choice_xmr.mlir 54:3]
input clk : Clock @[test_instance_choice_xmr.mlir 54:40]
output data : UInt<8> @[test_instance_choice_xmr.mlir 54:65]
output probe : Probe<UInt<8>> @[test_instance_choice_xmr.mlir 54:93]
inst middle of ASICMiddle @[test_instance_choice_xmr.mlir 55:48]
connect middle.clk, clk @[test_instance_choice_xmr.mlir 56:5]
connect data, middle.data @[test_instance_choice_xmr.mlir 57:5]
define probe = middle.probe @[test_instance_choice_xmr.mlir 58:5]
public module InstanceChoiceProbe : @[test_instance_choice_xmr.mlir 62:3]
input clk : Clock @[test_instance_choice_xmr.mlir 62:41]
output data : UInt<8> @[test_instance_choice_xmr.mlir 62:66]
output out : UInt<8> @[test_instance_choice_xmr.mlir 62:94]
instchoice inst of DefaultTarget, Platform : @[test_instance_choice_xmr.mlir 63:42]
FPGA => FPGATarget
ASIC => ASICTarget
connect inst.clk, clk @[test_instance_choice_xmr.mlir 68:5]
connect data, inst.data @[test_instance_choice_xmr.mlir 69:5]
connect out, read(inst.probe) @[test_instance_choice_xmr.mlir 72:5]
Raw
result.sv
// Generated by CIRCT unknown git version
module DefaultTarget( // test_instance_choice_xmr.mlir:8:3
input clk, // test_instance_choice_xmr.mlir:8:43
output [7:0] data // test_instance_choice_xmr.mlir:8:68
);
wire [7:0] r_probe = 8'h0; // test_instance_choice_xmr.mlir:10:11
assign data = r_probe; // test_instance_choice_xmr.mlir:8:3, :10:11
endmodule
module FPGAInner(); // test_instance_choice_xmr.mlir:18:3
wire [7:0] r_probe = 8'h1; // test_instance_choice_xmr.mlir:20:11
endmodule
module FPGATarget( // test_instance_choice_xmr.mlir:28:3
input clk, // test_instance_choice_xmr.mlir:28:40
output [7:0] data // test_instance_choice_xmr.mlir:28:65
);
FPGAInner inner (); // test_instance_choice_xmr.mlir:29:45
assign data = 8'h1; // test_instance_choice_xmr.mlir:28:3, :29:45
endmodule
module ASICDeep(); // test_instance_choice_xmr.mlir:36:3
wire [7:0] r_probe = 8'h2; // test_instance_choice_xmr.mlir:38:11
endmodule
module ASICMiddle(); // test_instance_choice_xmr.mlir:46:3
ASICDeep deep (); // test_instance_choice_xmr.mlir:47:42
endmodule
module ASICTarget( // test_instance_choice_xmr.mlir:54:3
input clk, // test_instance_choice_xmr.mlir:54:40
output [7:0] data // test_instance_choice_xmr.mlir:54:65
);
ASICMiddle middle (); // test_instance_choice_xmr.mlir:55:48
assign data = 8'h2; // test_instance_choice_xmr.mlir:54:3, :55:48
endmodule
module InstanceChoiceProbe( // test_instance_choice_xmr.mlir:62:3
input clk, // test_instance_choice_xmr.mlir:62:41
output [7:0] data, // test_instance_choice_xmr.mlir:62:66
out // test_instance_choice_xmr.mlir:62:94
);
wire [7:0] inst_data; // test_instance_choice_xmr.mlir:63:42
`ifndef __target_Platform_InstanceChoiceProbe_inst // test_instance_choice_xmr.mlir:63:42
`define __target_Platform_InstanceChoiceProbe_inst inst_1
`endif // not def __target_Platform_InstanceChoiceProbe_inst
`ifdef __option__Platform_FPGA // test_instance_choice_xmr.mlir:63:42
FPGATarget inst ( // test_instance_choice_xmr.mlir:63:42
.clk (clk),
.data (inst_data)
); // test_instance_choice_xmr.mlir:63:42
`else // __option__Platform_FPGA
`ifdef __option__Platform_ASIC // test_instance_choice_xmr.mlir:63:42
ASICTarget inst_0 ( // test_instance_choice_xmr.mlir:63:42
.clk (clk),
.data (inst_data)
); // test_instance_choice_xmr.mlir:63:42
`else // __option__Platform_ASIC
DefaultTarget inst_1 ( // test_instance_choice_xmr.mlir:63:42
.clk (clk),
.data (inst_data)
); // test_instance_choice_xmr.mlir:63:42
`endif // __option__Platform_ASIC
`endif // __option__Platform_FPGA
assign data = inst_data; // test_instance_choice_xmr.mlir:62:3
assign out = `ref_InstanceChoiceProbe_inst_probe; // test_instance_choice_xmr.mlir:62:3, :71:17
endmodule
// ----- 8< ----- FILE "ref_InstanceChoiceProbe.sv" ----- 8< -----
// Generated by CIRCT unknown git version
`ifdef __option__Platform_FPGA
`define ref_InstanceChoiceProbe_inst_probe `__target_Platform_InstanceChoiceProbe_inst.inner.r_probe
`elsif __option__Platform_ASIC
`define ref_InstanceChoiceProbe_inst_probe `__target_Platform_InstanceChoiceProbe_inst.middle.deep.r_probe
`else
`define ref_InstanceChoiceProbe_inst_probe `__target_Platform_InstanceChoiceProbe_inst.r_probe
`endif // test_instance_choice_xmr.mlir:63:42
// ----- 8< ----- FILE "targets_InstanceChoiceProbe_Platform_FPGA.svh" ----- 8< -----
// Specialization file for module: InstanceChoiceProbe
// Option: Platform, Case: FPGA // test_instance_choice_xmr.mlir:1:1
`ifndef __option__Platform_FPGA // test_instance_choice_xmr.mlir:1:1
`define __option__Platform_FPGA
`endif // not def __option__Platform_FPGA
`ifdef __target_Platform_InstanceChoiceProbe_inst // test_instance_choice_xmr.mlir:1:1
`_ERROR___target_Platform_InstanceChoiceProbe_inst__must__not__be__set
`else // __target_Platform_InstanceChoiceProbe_inst
`define __target_Platform_InstanceChoiceProbe_inst inst
`endif // __target_Platform_InstanceChoiceProbe_inst
// ----- 8< ----- FILE "targets_InstanceChoiceProbe_Platform_ASIC.svh" ----- 8< -----
// Specialization file for module: InstanceChoiceProbe
// Option: Platform, Case: ASIC // test_instance_choice_xmr.mlir:1:1
`ifndef __option__Platform_ASIC // test_instance_choice_xmr.mlir:1:1
`define __option__Platform_ASIC
`endif // not def __option__Platform_ASIC
`ifdef __target_Platform_InstanceChoiceProbe_inst // test_instance_choice_xmr.mlir:1:1
`_ERROR___target_Platform_InstanceChoiceProbe_inst__must__not__be__set
`else // __target_Platform_InstanceChoiceProbe_inst
`define __target_Platform_InstanceChoiceProbe_inst inst_0
`endif // __target_Platform_InstanceChoiceProbe_inst
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