wayne1029jihad
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| module LFSR (CLK, RESET_n, out); | |
| input CLK, RESET_n; | |
| output wire out; | |
| always @(`CLK)begin | |
| if(RESET) | |
| dff[4:0] <= 5'b00001; | |
| else | |
| dff[4:0] <= {exdff[3:0],exdff[1] ^ exdff[4]}; |