Last active
September 25, 2018 07:31
-
-
Save xiangzhai/7acd99e6ef8fb8ae32f937d8323a5eed to your computer and use it in GitHub Desktop.
Backport refactory loongson march and LoongISA to binutils-2.30
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Author: Leslie Zhai <[email protected]> | |
| Date: Tue Sep 25 15:29:31 2018 +0800 | |
| Backport refactory loongson march and LoongISA to binutils-2.30 | |
| diff --git a/bfd/archures.c b/bfd/archures.c | |
| index e83c57a..8e65a3d 100644 | |
| --- a/bfd/archures.c | |
| +++ b/bfd/archures.c | |
| @@ -193,7 +193,9 @@ DESCRIPTION | |
| .#define bfd_mach_mips5 5 | |
| .#define bfd_mach_mips_loongson_2e 3001 | |
| .#define bfd_mach_mips_loongson_2f 3002 | |
| -.#define bfd_mach_mips_loongson_3a 3003 | |
| +.#define bfd_mach_mips_gs464 3003 | |
| +.#define bfd_mach_mips_gs464e 3004 | |
| +.#define bfd_mach_mips_gs264e 3005 | |
| .#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01. *} | |
| .#define bfd_mach_mips_octeon 6501 | |
| .#define bfd_mach_mips_octeonp 6601 | |
| diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h | |
| index f4b3720..95078d1 100644 | |
| --- a/bfd/bfd-in2.h | |
| +++ b/bfd/bfd-in2.h | |
| @@ -2054,7 +2054,9 @@ enum bfd_architecture | |
| #define bfd_mach_mips5 5 | |
| #define bfd_mach_mips_loongson_2e 3001 | |
| #define bfd_mach_mips_loongson_2f 3002 | |
| -#define bfd_mach_mips_loongson_3a 3003 | |
| +#define bfd_mach_mips_gs464 3003 | |
| +#define bfd_mach_mips_gs464e 3004 | |
| +#define bfd_mach_mips_gs264e 3005 | |
| #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01. */ | |
| #define bfd_mach_mips_octeon 6501 | |
| #define bfd_mach_mips_octeonp 6601 | |
| diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c | |
| index cb50c64..339b111 100644 | |
| --- a/bfd/cpu-mips.c | |
| +++ b/bfd/cpu-mips.c | |
| @@ -98,7 +98,9 @@ enum | |
| I_sb1, | |
| I_loongson_2e, | |
| I_loongson_2f, | |
| - I_loongson_3a, | |
| + I_gs464, | |
| + I_gs464e, | |
| + I_gs264e, | |
| I_mipsocteon, | |
| I_mipsocteonp, | |
| I_mipsocteon2, | |
| @@ -150,7 +152,9 @@ static const bfd_arch_info_type arch_info_struct[] = | |
| N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)), | |
| N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)), | |
| N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)), | |
| - N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)), | |
| + N (64, 64, bfd_mach_mips_gs464, "mips:gs464", FALSE, NN(I_gs464)), | |
| + N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e", FALSE, NN(I_gs464e)), | |
| + N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e", FALSE, NN(I_gs264e)), | |
| N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)), | |
| N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)), | |
| N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)), | |
| diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c | |
| index b237957..556560f 100644 | |
| --- a/bfd/elfxx-mips.c | |
| +++ b/bfd/elfxx-mips.c | |
| @@ -6815,8 +6815,14 @@ _bfd_elf_mips_mach (flagword flags) | |
| case E_MIPS_MACH_LS2F: | |
| return bfd_mach_mips_loongson_2f; | |
| - case E_MIPS_MACH_LS3A: | |
| - return bfd_mach_mips_loongson_3a; | |
| + case E_MIPS_MACH_GS464: | |
| + return bfd_mach_mips_gs464; | |
| + | |
| + case E_MIPS_MACH_GS464E: | |
| + return bfd_mach_mips_gs464e; | |
| + | |
| + case E_MIPS_MACH_GS264E: | |
| + return bfd_mach_mips_gs264e; | |
| case E_MIPS_MACH_OCTEON3: | |
| return bfd_mach_mips_octeon3; | |
| @@ -11888,8 +11894,8 @@ mips_set_isa_flags (bfd *abfd) | |
| switch (bfd_get_mach (abfd)) | |
| { | |
| default: | |
| - case bfd_mach_mips_loongson_3a: | |
| - val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_LS3A; | |
| + case bfd_mach_mips_gs464: | |
| + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464; | |
| break; | |
| case bfd_mach_mips3000: | |
| @@ -11973,6 +11979,14 @@ mips_set_isa_flags (bfd *abfd) | |
| val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1; | |
| break; | |
| + case bfd_mach_mips_gs464e: | |
| + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E; | |
| + break; | |
| + | |
| + case bfd_mach_mips_gs264e: | |
| + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS264E; | |
| + break; | |
| + | |
| case bfd_mach_mips_octeon: | |
| case bfd_mach_mips_octeonp: | |
| val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON; | |
| @@ -13962,7 +13976,9 @@ static const struct mips_mach_extension mips_mach_extensions[] = | |
| { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp }, | |
| { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, | |
| { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, | |
| - { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 }, | |
| + { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e }, | |
| + { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 }, | |
| + { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 }, | |
| /* MIPS64 extensions. */ | |
| { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, | |
| @@ -14074,7 +14090,6 @@ bfd_mips_isa_ext_mach (unsigned int isa_ext) | |
| case AFL_EXT_10000: return bfd_mach_mips10000; | |
| case AFL_EXT_LOONGSON_2E: return bfd_mach_mips_loongson_2e; | |
| case AFL_EXT_LOONGSON_2F: return bfd_mach_mips_loongson_2f; | |
| - case AFL_EXT_LOONGSON_3A: return bfd_mach_mips_loongson_3a; | |
| case AFL_EXT_SB1: return bfd_mach_mips_sb1; | |
| case AFL_EXT_OCTEON: return bfd_mach_mips_octeon; | |
| case AFL_EXT_OCTEONP: return bfd_mach_mips_octeonp; | |
| @@ -14103,7 +14118,6 @@ bfd_mips_isa_ext (bfd *abfd) | |
| case bfd_mach_mips10000: return AFL_EXT_10000; | |
| case bfd_mach_mips_loongson_2e: return AFL_EXT_LOONGSON_2E; | |
| case bfd_mach_mips_loongson_2f: return AFL_EXT_LOONGSON_2F; | |
| - case bfd_mach_mips_loongson_3a: return AFL_EXT_LOONGSON_3A; | |
| case bfd_mach_mips_sb1: return AFL_EXT_SB1; | |
| case bfd_mach_mips_octeon: return AFL_EXT_OCTEON; | |
| case bfd_mach_mips_octeonp: return AFL_EXT_OCTEONP; | |
| @@ -14219,7 +14233,7 @@ infer_mips_abiflags (bfd *abfd, Elf_Internal_ABIFlags_v0* abiflags) | |
| && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_SOFT | |
| && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_64A | |
| && abiflags->isa_level >= 32 | |
| - && abiflags->isa_ext != AFL_EXT_LOONGSON_3A) | |
| + && abiflags->ases != AFL_ASE_LOONGSON_EXT) | |
| abiflags->flags1 |= AFL_FLAGS1_ODDSPREG; | |
| } | |
| @@ -15644,6 +15658,14 @@ print_mips_ases (FILE *file, unsigned int mask) | |
| fputs ("\n\tXPA ASE", file); | |
| if (mask & AFL_ASE_MIPS16E2) | |
| fputs ("\n\tMIPS16e2 ASE", file); | |
| + if (mask & AFL_ASE_LOONGSON_MMI) | |
| + fputs ("\n\tLoongson MMI ASE", file); | |
| + if (mask & AFL_ASE_LOONGSON_CAM) | |
| + fputs ("\n\tLoongson CAM ASE", file); | |
| + if (mask & AFL_ASE_LOONGSON_EXT) | |
| + fputs ("\n\tLoongson EXT ASE", file); | |
| + if (mask & AFL_ASE_LOONGSON_EXT2) | |
| + fputs ("\n\tLoongson EXT2 ASE", file); | |
| if (mask == 0) | |
| fprintf (file, "\n\t%s", _("None")); | |
| else if ((mask & ~AFL_ASE_MASK) != 0) | |
| @@ -15670,9 +15692,6 @@ print_mips_isa_ext (FILE *file, unsigned int isa_ext) | |
| case AFL_EXT_OCTEONP: | |
| fputs ("Cavium Networks OcteonP", file); | |
| break; | |
| - case AFL_EXT_LOONGSON_3A: | |
| - fputs ("Loongson 3A", file); | |
| - break; | |
| case AFL_EXT_OCTEON: | |
| fputs ("Cavium Networks Octeon", file); | |
| break; | |
| diff --git a/binutils/MAINTAINERS b/binutils/MAINTAINERS | |
| index 3bb542d..92c7b74 100644 | |
| --- a/binutils/MAINTAINERS | |
| +++ b/binutils/MAINTAINERS | |
| @@ -104,6 +104,7 @@ responsibility among the other maintainers. | |
| MEP Dave Brolley <[email protected]> | |
| METAG Markos Chandras <[email protected]> | |
| MICROBLAZE Michael Eager <[email protected]> | |
| + MIPS Chenghua Xu <[email protected]> | |
| MIPS Maciej W. Rozycki <[email protected]> | |
| MMIX Hans-Peter Nilsson <[email protected]> | |
| MN10300 Alexandre Oliva <[email protected]> | |
| diff --git a/binutils/readelf.c b/binutils/readelf.c | |
| index 761c8d5..ee193f5 100644 | |
| --- a/binutils/readelf.c | |
| +++ b/binutils/readelf.c | |
| @@ -3366,7 +3366,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) | |
| case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break; | |
| case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break; | |
| case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break; | |
| - case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break; | |
| + case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break; | |
| + case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break; | |
| + case E_MIPS_MACH_GS264E: strcat (buf, ", gs264e"); break; | |
| case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break; | |
| case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; | |
| case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; | |
| @@ -15455,6 +15457,14 @@ print_mips_ases (unsigned int mask) | |
| fputs ("\n\tXPA ASE", stdout); | |
| if (mask & AFL_ASE_MIPS16E2) | |
| fputs ("\n\tMIPS16e2 ASE", stdout); | |
| + if (mask & AFL_ASE_LOONGSON_MMI) | |
| + fputs ("\n\tLoongson MMI ASE", stdout); | |
| + if (mask & AFL_ASE_LOONGSON_CAM) | |
| + fputs ("\n\tLoongson CAM ASE", stdout); | |
| + if (mask & AFL_ASE_LOONGSON_EXT) | |
| + fputs ("\n\tLoongson EXT ASE", stdout); | |
| + if (mask & AFL_ASE_LOONGSON_EXT2) | |
| + fputs ("\n\tLoongson EXT2 ASE", stdout); | |
| if (mask == 0) | |
| fprintf (stdout, "\n\t%s", _("None")); | |
| else if ((mask & ~AFL_ASE_MASK) != 0) | |
| @@ -15481,9 +15491,6 @@ print_mips_isa_ext (unsigned int isa_ext) | |
| case AFL_EXT_OCTEONP: | |
| fputs ("Cavium Networks OcteonP", stdout); | |
| break; | |
| - case AFL_EXT_LOONGSON_3A: | |
| - fputs ("Loongson 3A", stdout); | |
| - break; | |
| case AFL_EXT_OCTEON: | |
| fputs ("Cavium Networks Octeon", stdout); | |
| break; | |
| diff --git a/elfcpp/mips.h b/elfcpp/mips.h | |
| index cac8592..c724fd0 100644 | |
| --- a/elfcpp/mips.h | |
| +++ b/elfcpp/mips.h | |
| @@ -235,7 +235,9 @@ enum | |
| E_MIPS_MACH_9000 = 0x00990000, | |
| E_MIPS_MACH_LS2E = 0x00A00000, | |
| E_MIPS_MACH_LS2F = 0x00A10000, | |
| - E_MIPS_MACH_LS3A = 0x00A20000, | |
| + E_MIPS_MACH_GS464 = 0x00A20000, | |
| + E_MIPS_MACH_GS464E = 0x00A30000, | |
| + E_MIPS_MACH_GS264E = 0x00A40000, | |
| }; | |
| // MIPS architecture | |
| @@ -308,7 +310,9 @@ enum | |
| // MICROMIPS ASE. | |
| AFL_ASE_MICROMIPS = 0x00000800, | |
| // XPA ASE. | |
| - AFL_ASE_XPA = 0x00001000 | |
| + AFL_ASE_XPA = 0x00001000, | |
| + // Loongson EXT ASE. | |
| + AFL_ASE_LOONGSON_EXT = 0x00002000 | |
| }; | |
| // Values for the isa_ext word of an ABI flags structure. | |
| diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c | |
| index 8c0cda9..a221800 100644 | |
| --- a/gas/config/tc-mips.c | |
| +++ b/gas/config/tc-mips.c | |
| @@ -422,7 +422,9 @@ static int mips_32bitmode = 0; | |
| || (ISA) == ISA_MIPS64R5 \ | |
| || (ISA) == ISA_MIPS64R6 \ | |
| || (CPU) == CPU_R5900) \ | |
| - && (CPU) != CPU_LOONGSON_3A) | |
| + && ((CPU) != CPU_GS464 \ | |
| + || (CPU) != CPU_GS464E \ | |
| + || (CPU) != CPU_GS264E)) | |
| /* Return true if ISA supports move to/from high part of a 64-bit | |
| floating-point register. */ | |
| @@ -1540,6 +1542,14 @@ enum options | |
| OPTION_NAN, | |
| OPTION_ODD_SPREG, | |
| OPTION_NO_ODD_SPREG, | |
| + OPTION_LOONGSON_MMI, | |
| + OPTION_NO_LOONGSON_MMI, | |
| + OPTION_LOONGSON_CAM, | |
| + OPTION_NO_LOONGSON_CAM, | |
| + OPTION_LOONGSON_EXT, | |
| + OPTION_NO_LOONGSON_EXT, | |
| + OPTION_LOONGSON_EXT2, | |
| + OPTION_NO_LOONGSON_EXT2, | |
| OPTION_END_OF_ENUM | |
| }; | |
| @@ -1596,6 +1606,14 @@ struct option md_longopts[] = | |
| {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
| {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, | |
| {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
| + {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI}, | |
| + {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI}, | |
| + {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM}, | |
| + {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM}, | |
| + {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT}, | |
| + {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT}, | |
| + {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2}, | |
| + {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2}, | |
| /* Old-style architecture options. Don't add more of these. */ | |
| {"m4650", no_argument, NULL, OPTION_M4650}, | |
| @@ -1787,6 +1805,26 @@ static const struct mips_ase mips_ases[] = { | |
| OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
| 2, 2, -1, -1, | |
| 6 }, | |
| + | |
| + { "loongson-mmi", ASE_LOONGSON_MMI, 0, | |
| + OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI, | |
| + 0, 0, -1, -1, | |
| + -1 }, | |
| + | |
| + { "loongson-cam", ASE_LOONGSON_CAM, 0, | |
| + OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM, | |
| + 0, 0, -1, -1, | |
| + -1 }, | |
| + | |
| + { "loongson-ext", ASE_LOONGSON_EXT, 0, | |
| + OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT, | |
| + 0, 0, -1, -1, | |
| + -1 }, | |
| + | |
| + { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0, | |
| + OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2, | |
| + 0, 0, -1, -1, | |
| + -1 }, | |
| }; | |
| /* The set of ASEs that require -mfp64. */ | |
| @@ -1794,7 +1832,8 @@ static const struct mips_ase mips_ases[] = { | |
| /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
| static const unsigned int mips_ase_groups[] = { | |
| - ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | |
| + ASE_DSP | ASE_DSPR2 | ASE_DSPR3, | |
| + ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2 | |
| }; | |
| /* Pseudo-op table. | |
| @@ -19114,6 +19153,14 @@ mips_convert_ase_flags (int ase) | |
| ext_ases |= AFL_ASE_XPA; | |
| if (ase & ASE_MIPS16E2) | |
| ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
| + if (ase & ASE_LOONGSON_MMI) | |
| + ext_ases |= AFL_ASE_LOONGSON_MMI; | |
| + if (ase & ASE_LOONGSON_CAM) | |
| + ext_ases |= AFL_ASE_LOONGSON_CAM; | |
| + if (ase & ASE_LOONGSON_EXT) | |
| + ext_ases |= AFL_ASE_LOONGSON_EXT; | |
| + if (ase & ASE_LOONGSON_EXT2) | |
| + ext_ases |= AFL_ASE_LOONGSON_EXT2; | |
| return ext_ases; | |
| } | |
| @@ -19760,7 +19807,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = | |
| { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
| /* ST Microelectronics Loongson 2E and 2F cores */ | |
| { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
| - { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
| + { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F }, | |
| /* MIPS IV */ | |
| { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, | |
| @@ -19859,9 +19906,17 @@ static const struct mips_cpu_info mips_cpu_info_table[] = | |
| /* Broadcom SB-1A CPU core */ | |
| { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, | |
| - { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, | |
| - | |
| /* MIPS 64 Release 2 */ | |
| + /* Loongson CPU core */ | |
| + /* -march=loongson3a is an alias of -march=gs464 for compatibility */ | |
| + { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
| + ISA_MIPS64R2, CPU_GS464 }, | |
| + { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
| + ISA_MIPS64R2, CPU_GS464 }, | |
| + { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT | |
| + | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, | |
| + { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT | |
| + | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E }, | |
| /* Cavium Networks Octeon CPU core */ | |
| { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, | |
| @@ -20125,6 +20180,18 @@ MIPS options:\n\ | |
| -mvirt generate Virtualization instructions\n\ | |
| -mno-virt do not generate Virtualization instructions\n")); | |
| fprintf (stream, _("\ | |
| +-mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\ | |
| +-mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n")); | |
| + fprintf (stream, _("\ | |
| +-mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\ | |
| +-mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n")); | |
| + fprintf (stream, _("\ | |
| +-mloongson-ext generate Loongson EXTensions (EXT) instructions\n\ | |
| +-mno-loongson-ext do not generate Loongson EXTensions Instructions\n")); | |
| + fprintf (stream, _("\ | |
| +-mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\ | |
| +-mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n")); | |
| + fprintf (stream, _("\ | |
| -minsn32 only generate 32-bit microMIPS instructions\n\ | |
| -mno-insn32 generate all microMIPS instructions\n")); | |
| fprintf (stream, _("\ | |
| diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi | |
| index 650d886..3d4c93e 100644 | |
| --- a/gas/doc/c-mips.texi | |
| +++ b/gas/doc/c-mips.texi | |
| @@ -234,6 +234,34 @@ Generate code for the Virtualization Application Specific Extension. | |
| This tells the assembler to accept Virtualization instructions. | |
| @samp{-mno-virt} turns off this option. | |
| +@item -mloongson-mmi | |
| +@itemx -mno-loongson-mmi | |
| +Generate code for the Loongson MultiMedia extensions Instructions (MMI) | |
| +Application Specific Extension. This tells the assembler to accept MMI | |
| +instructions. | |
| +@samp{-mno-loongson-mmi} turns off this option. | |
| + | |
| +@item -mloongson-cam | |
| +@itemx -mno-loongson-cam | |
| +Generate code for the Loongson Content Address Memory (CAM) | |
| +Application Specific Extension. This tells the assembler to accept CAM | |
| +instructions. | |
| +@samp{-mno-loongson-cam} turns off this option. | |
| + | |
| +@item -mloongson-ext | |
| +@itemx -mno-loongson-ext | |
| +Generate code for the Loongson EXTensions (EXT) instructions | |
| +Application Specific Extension. This tells the assembler to accept EXT | |
| +instructions. | |
| +@samp{-mno-loongson-ext} turns off this option. | |
| + | |
| +@item -mloongson-ext2 | |
| +@itemx -mno-loongson-ext2 | |
| +Generate code for the Loongson EXTensions R2 (EXT2) instructions | |
| +Application Specific Extension. This tells the assembler to accept EXT2 | |
| +instructions. | |
| +@samp{-mno-loongson-ext2} turns off this option. | |
| + | |
| @item -minsn32 | |
| @itemx -mno-insn32 | |
| Only use 32-bit instruction encodings when generating code for the | |
| @@ -397,7 +425,9 @@ i6400, | |
| p6600, | |
| loongson2e, | |
| loongson2f, | |
| -loongson3a, | |
| +gs464, | |
| +gs464e, | |
| +gs264e, | |
| octeon, | |
| octeon+, | |
| octeon2, | |
| @@ -1134,6 +1164,39 @@ float-point operations. These directives always override the default | |
| (that double-precision operations are accepted) or the command-line | |
| options (@samp{-msingle-float} and @samp{-mdouble-float}). | |
| +@cindex Loongson MultiMedia extensions Instructions (MMI) generation override | |
| +@kindex @code{.set loongson-mmi} | |
| +@kindex @code{.set noloongson-mmi} | |
| +The directive @code{.set loongson-mmi} makes the assembler accept | |
| +instructions from the MMI Extension from that point on in the assembly. | |
| +The @code{.set noloongson-mmi} directive prevents MMI instructions from | |
| +being accepted. | |
| + | |
| +@cindex Loongson Content Address Memory (CAM) generation override | |
| +@kindex @code{.set loongson-cam} | |
| +@kindex @code{.set noloongson-cam} | |
| +The directive @code{.set loongson-cam} makes the assembler accept | |
| +instructions from the Loongson CAM from that point on in the assembly. | |
| +The @code{.set noloongson-cam} directive prevents Loongson CAM instructions | |
| +from being accepted. | |
| + | |
| +@cindex Loongson EXTensions (EXT) instructions generation override | |
| +@kindex @code{.set loongson-ext} | |
| +@kindex @code{.set noloongson-ext} | |
| +The directive @code{.set loongson-ext} makes the assembler accept | |
| +instructions from the Loongson EXT from that point on in the assembly. | |
| +The @code{.set noloongson-ext} directive prevents Loongson EXT instructions | |
| +from being accepted. | |
| + | |
| +@cindex Loongson EXTensions R2 (EXT2) instructions generation override | |
| +@kindex @code{.set loongson-ext2} | |
| +@kindex @code{.set noloongson-ext2} | |
| +The directive @code{.set loongson-ext2} makes the assembler accept | |
| +instructions from the Loongson EXT2 from that point on in the assembly. | |
| +This directive implies @code{.set loognson-ext}. | |
| +The @code{.set noloongson-ext2} directive prevents Loongson EXT2 instructions | |
| +from being accepted. | |
| + | |
| Traditional MIPS assemblers do not support these directives. | |
| @node MIPS Syntax | |
| diff --git a/gas/testsuite/gas/mips/loongson-2f-mmi.d b/gas/testsuite/gas/mips/loongson-2f-mmi.d | |
| new file mode 100644 | |
| index 0000000..84224f9 | |
| --- /dev/null | |
| +++ b/gas/testsuite/gas/mips/loongson-2f-mmi.d | |
| @@ -0,0 +1,106 @@ | |
| +#as: -march=loongson2f -mabi=o64 | |
| +#objdump: -M reg-names=numeric -dp | |
| +#name: Loongson-2F MMI tests | |
| + | |
| +.*: file format .* | |
| + | |
| +private flags = .* | |
| + | |
| +MIPS ABI Flags Version: 0 | |
| +ISA: .* | |
| +GPR size: .* | |
| +CPR1 size: .* | |
| +CPR2 size: .* | |
| +FP ABI: .* | |
| +ISA Extension: ST Microelectronics Loongson 2F | |
| +ASEs: | |
| + Loongson MMI ASE | |
| +FLAGS 1: .* | |
| +FLAGS 2: .* | |
| + | |
| +Disassembly of section .text: | |
| + | |
| +[0-9a-f]+ <simd_insns>: | |
| +.*: 4b420802 packsshb \$f0,\$f1,\$f2 | |
| +.*: 4b2520c2 packsswh \$f3,\$f4,\$f5 | |
| +.*: 4b683982 packushb \$f6,\$f7,\$f8 | |
| +.*: 4bcb5240 paddb \$f9,\$f10,\$f11 | |
| +.*: 4b4e6b00 paddh \$f12,\$f13,\$f14 | |
| +.*: 4b7183c0 paddw \$f15,\$f16,\$f17 | |
| +.*: 4bf49c80 paddd \$f18,\$f19,\$f20 | |
| +.*: 4b97b540 paddsb \$f21,\$f22,\$f23 | |
| +.*: 4b1ace00 paddsh \$f24,\$f25,\$f26 | |
| +.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29 | |
| +.*: 4b220800 paddush \$f0,\$f1,\$f2 | |
| +.*: 4be520c2 pandn \$f3,\$f4,\$f5 | |
| +.*: 4b283988 pavgb \$f6,\$f7,\$f8 | |
| +.*: 4b0b5248 pavgh \$f9,\$f10,\$f11 | |
| +.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14 | |
| +.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17 | |
| +.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20 | |
| +.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23 | |
| +.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26 | |
| +.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29 | |
| +.*: 4b42080e pextrh \$f0,\$f1,\$f2 | |
| +.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5 | |
| +.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8 | |
| +.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11 | |
| +.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14 | |
| +.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17 | |
| +.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20 | |
| +.*: 4b97b548 pmaxub \$f21,\$f22,\$f23 | |
| +.*: 4b7ace08 pminsh \$f24,\$f25,\$f26 | |
| +.*: 4bbde6c8 pminub \$f27,\$f28,\$f29 | |
| +.*: 4ba0080f pmovmskb \$f0,\$f1 | |
| +.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4 | |
| +.*: 4b67314a pmulhh \$f5,\$f6,\$f7 | |
| +.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10 | |
| +.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13 | |
| +.*: 4b307b8d pasubub \$f14,\$f15,\$f16 | |
| +.*: 4b80944f biadd \$f17,\$f18 | |
| +.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21 | |
| +.*: 4b38bd8a psllh \$f22,\$f23,\$f24 | |
| +.*: 4b1bd64a psllw \$f25,\$f26,\$f27 | |
| +.*: 4b7eef0b psrah \$f28,\$f29,\$f30 | |
| +.*: 4b42080b psraw \$f0,\$f1,\$f2 | |
| +.*: 4b2520cb psrlh \$f3,\$f4,\$f5 | |
| +.*: 4b08398b psrlw \$f6,\$f7,\$f8 | |
| +.*: 4bcb5241 psubb \$f9,\$f10,\$f11 | |
| +.*: 4b4e6b01 psubh \$f12,\$f13,\$f14 | |
| +.*: 4b7183c1 psubw \$f15,\$f16,\$f17 | |
| +.*: 4bf49c81 psubd \$f18,\$f19,\$f20 | |
| +.*: 4b97b541 psubsb \$f21,\$f22,\$f23 | |
| +.*: 4b1ace01 psubsh \$f24,\$f25,\$f26 | |
| +.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29 | |
| +.*: 4b220801 psubush \$f0,\$f1,\$f2 | |
| +.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5 | |
| +.*: 4b283983 punpckhhw \$f6,\$f7,\$f8 | |
| +.*: 4bab524b punpckhwd \$f9,\$f10,\$f11 | |
| +.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14 | |
| +.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17 | |
| +.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20 | |
| + | |
| +[0-9a-f]+ <fixed_point_insns>: | |
| +.*: 4b42080c add \$f0,\$f1,\$f2 | |
| +.*: 4b0520cc addu \$f3,\$f4,\$f5 | |
| +.*: 4b68398c dadd \$f6,\$f7,\$f8 | |
| +.*: 4b4b524d sub \$f9,\$f10,\$f11 | |
| +.*: 4b0e6b0d subu \$f12,\$f13,\$f14 | |
| +.*: 4b7183cd dsub \$f15,\$f16,\$f17 | |
| +.*: 4b349c8c or \$f18,\$f19,\$f20 | |
| +.*: 4b17b54e sll \$f21,\$f22,\$f23 | |
| +.*: 4b3ace0e dsll \$f24,\$f25,\$f26 | |
| +.*: 4b9de6c2 xor \$f27,\$f28,\$f29 | |
| +.*: 4ba20802 nor \$f0,\$f1,\$f2 | |
| +.*: 4bc520c2 and \$f3,\$f4,\$f5 | |
| +.*: 4b08398f srl \$f6,\$f7,\$f8 | |
| +.*: 4b2b524f dsrl \$f9,\$f10,\$f11 | |
| +.*: 4b4e6b0f sra \$f12,\$f13,\$f14 | |
| +.*: 4b7183cf dsra \$f15,\$f16,\$f17 | |
| +.*: 4b93900c sequ \$f18,\$f19 | |
| +.*: 4b95a00d sltu \$f20,\$f21 | |
| +.*: 4b97b00e sleu \$f22,\$f23 | |
| +.*: 4bb9c00c seq \$f24,\$f25 | |
| +.*: 4bbbd00d slt \$f26,\$f27 | |
| +.*: 4bbde00e sle \$f28,\$f29 | |
| +#pass | |
| diff --git a/gas/testsuite/gas/mips/loongson-2f-mmi.s b/gas/testsuite/gas/mips/loongson-2f-mmi.s | |
| new file mode 100644 | |
| index 0000000..e87d66e | |
| --- /dev/null | |
| +++ b/gas/testsuite/gas/mips/loongson-2f-mmi.s | |
| @@ -0,0 +1,86 @@ | |
| + .text | |
| + .set noreorder | |
| + | |
| +simd_insns: | |
| + packsshb $f0, $f1, $f2 | |
| + packsswh $f3, $f4, $f5 | |
| + packushb $f6, $f7, $f8 | |
| + paddb $f9, $f10, $f11 | |
| + paddh $f12, $f13, $f14 | |
| + paddw $f15, $f16, $f17 | |
| + paddd $f18, $f19, $f20 | |
| + paddsb $f21, $f22, $f23 | |
| + paddsh $f24, $f25, $f26 | |
| + paddusb $f27, $f28, $f29 | |
| + paddush $f0, $f1, $f2 | |
| + pandn $f3, $f4, $f5 | |
| + pavgb $f6, $f7, $f8 | |
| + pavgh $f9, $f10, $f11 | |
| + pcmpeqb $f12, $f13, $f14 | |
| + pcmpeqh $f15, $f16, $f17 | |
| + pcmpeqw $f18, $f19, $f20 | |
| + pcmpgtb $f21, $f22, $f23 | |
| + pcmpgth $f24, $f25, $f26 | |
| + pcmpgtw $f27, $f28, $f29 | |
| + pextrh $f0, $f1, $f2 | |
| + pinsrh_0 $f3, $f4, $f5 | |
| + pinsrh_1 $f6, $f7, $f8 | |
| + pinsrh_2 $f9, $f10, $f11 | |
| + pinsrh_3 $f12, $f13, $f14 | |
| + pmaddhw $f15, $f16, $f17 | |
| + pmaxsh $f18, $f19, $f20 | |
| + pmaxub $f21, $f22, $f23 | |
| + pminsh $f24, $f25, $f26 | |
| + pminub $f27, $f28, $f29 | |
| + pmovmskb $f0, $f1 | |
| + pmulhuh $f2, $f3, $f4 | |
| + pmulhh $f5, $f6, $f7 | |
| + pmullh $f8, $f9, $f10 | |
| + pmuluw $f11, $f12, $f13 | |
| + pasubub $f14, $f15, $f16 | |
| + biadd $f17, $f18 | |
| + pshufh $f19, $f20, $f21 | |
| + psllh $f22, $f23, $f24 | |
| + psllw $f25, $f26, $f27 | |
| + psrah $f28, $f29, $f30 | |
| + psraw $f0, $f1, $f2 | |
| + psrlh $f3, $f4, $f5 | |
| + psrlw $f6, $f7, $f8 | |
| + psubb $f9, $f10, $f11 | |
| + psubh $f12, $f13, $f14 | |
| + psubw $f15, $f16, $f17 | |
| + psubd $f18, $f19, $f20 | |
| + psubsb $f21, $f22, $f23 | |
| + psubsh $f24, $f25, $f26 | |
| + psubusb $f27, $f28, $f29 | |
| + psubush $f0, $f1, $f2 | |
| + punpckhbh $f3, $f4, $f5 | |
| + punpckhhw $f6, $f7, $f8 | |
| + punpckhwd $f9, $f10, $f11 | |
| + punpcklbh $f12, $f13, $f14 | |
| + punpcklhw $f15, $f16, $f17 | |
| + punpcklwd $f18, $f19, $f20 | |
| + | |
| +fixed_point_insns: | |
| + add $f0, $f1, $f2 | |
| + addu $f3, $f4, $f5 | |
| + dadd $f6, $f7, $f8 | |
| + sub $f9, $f10, $f11 | |
| + subu $f12, $f13, $f14 | |
| + dsub $f15, $f16, $f17 | |
| + or $f18, $f19, $f20 | |
| + sll $f21, $f22, $f23 | |
| + dsll $f24, $f25, $f26 | |
| + xor $f27, $f28, $f29 | |
| + nor $f0, $f1, $f2 | |
| + and $f3, $f4, $f5 | |
| + srl $f6, $f7, $f8 | |
| + dsrl $f9, $f10, $f11 | |
| + sra $f12, $f13, $f14 | |
| + dsra $f15, $f16, $f17 | |
| + sequ $f18, $f19 | |
| + sltu $f20, $f21 | |
| + sleu $f22, $f23 | |
| + seq $f24, $f25 | |
| + slt $f26, $f27 | |
| + sle $f28, $f29 | |
| diff --git a/gas/testsuite/gas/mips/loongson-2f.d b/gas/testsuite/gas/mips/loongson-2f.d | |
| index 8d1d8f7..4bd8f15 100644 | |
| --- a/gas/testsuite/gas/mips/loongson-2f.d | |
| +++ b/gas/testsuite/gas/mips/loongson-2f.d | |
| @@ -39,91 +39,7 @@ Disassembly of section .text: | |
| .*: 7222081b nmsub.d \$f0,\$f1,\$f2 | |
| .*: 72c520db nmsub.ps \$f3,\$f4,\$f5 | |
| -[0-9a-f]+ <simd_insns>: | |
| -.*: 4b420802 packsshb \$f0,\$f1,\$f2 | |
| -.*: 4b2520c2 packsswh \$f3,\$f4,\$f5 | |
| -.*: 4b683982 packushb \$f6,\$f7,\$f8 | |
| -.*: 4bcb5240 paddb \$f9,\$f10,\$f11 | |
| -.*: 4b4e6b00 paddh \$f12,\$f13,\$f14 | |
| -.*: 4b7183c0 paddw \$f15,\$f16,\$f17 | |
| -.*: 4bf49c80 paddd \$f18,\$f19,\$f20 | |
| -.*: 4b97b540 paddsb \$f21,\$f22,\$f23 | |
| -.*: 4b1ace00 paddsh \$f24,\$f25,\$f26 | |
| -.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29 | |
| -.*: 4b220800 paddush \$f0,\$f1,\$f2 | |
| -.*: 4be520c2 pandn \$f3,\$f4,\$f5 | |
| -.*: 4b283988 pavgb \$f6,\$f7,\$f8 | |
| -.*: 4b0b5248 pavgh \$f9,\$f10,\$f11 | |
| -.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14 | |
| -.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17 | |
| -.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20 | |
| -.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23 | |
| -.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26 | |
| -.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29 | |
| -.*: 4b42080e pextrh \$f0,\$f1,\$f2 | |
| -.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5 | |
| -.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8 | |
| -.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11 | |
| -.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14 | |
| -.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17 | |
| -.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20 | |
| -.*: 4b97b548 pmaxub \$f21,\$f22,\$f23 | |
| -.*: 4b7ace08 pminsh \$f24,\$f25,\$f26 | |
| -.*: 4bbde6c8 pminub \$f27,\$f28,\$f29 | |
| -.*: 4ba0080f pmovmskb \$f0,\$f1 | |
| -.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4 | |
| -.*: 4b67314a pmulhh \$f5,\$f6,\$f7 | |
| -.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10 | |
| -.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13 | |
| -.*: 4b307b8d pasubub \$f14,\$f15,\$f16 | |
| -.*: 4b80944f biadd \$f17,\$f18 | |
| -.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21 | |
| -.*: 4b38bd8a psllh \$f22,\$f23,\$f24 | |
| -.*: 4b1bd64a psllw \$f25,\$f26,\$f27 | |
| -.*: 4b7eef0b psrah \$f28,\$f29,\$f30 | |
| -.*: 4b42080b psraw \$f0,\$f1,\$f2 | |
| -.*: 4b2520cb psrlh \$f3,\$f4,\$f5 | |
| -.*: 4b08398b psrlw \$f6,\$f7,\$f8 | |
| -.*: 4bcb5241 psubb \$f9,\$f10,\$f11 | |
| -.*: 4b4e6b01 psubh \$f12,\$f13,\$f14 | |
| -.*: 4b7183c1 psubw \$f15,\$f16,\$f17 | |
| -.*: 4bf49c81 psubd \$f18,\$f19,\$f20 | |
| -.*: 4b97b541 psubsb \$f21,\$f22,\$f23 | |
| -.*: 4b1ace01 psubsh \$f24,\$f25,\$f26 | |
| -.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29 | |
| -.*: 4b220801 psubush \$f0,\$f1,\$f2 | |
| -.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5 | |
| -.*: 4b283983 punpckhhw \$f6,\$f7,\$f8 | |
| -.*: 4bab524b punpckhwd \$f9,\$f10,\$f11 | |
| -.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14 | |
| -.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17 | |
| -.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20 | |
| - | |
| -[0-9a-f]+ <fixed_point_insns>: | |
| -.*: 4b42080c add \$f0,\$f1,\$f2 | |
| -.*: 4b0520cc addu \$f3,\$f4,\$f5 | |
| -.*: 4b68398c dadd \$f6,\$f7,\$f8 | |
| -.*: 4b4b524d sub \$f9,\$f10,\$f11 | |
| -.*: 4b0e6b0d subu \$f12,\$f13,\$f14 | |
| -.*: 4b7183cd dsub \$f15,\$f16,\$f17 | |
| -.*: 4b349c8c or \$f18,\$f19,\$f20 | |
| -.*: 4b17b54e sll \$f21,\$f22,\$f23 | |
| -.*: 4b3ace0e dsll \$f24,\$f25,\$f26 | |
| -.*: 4b9de6c2 xor \$f27,\$f28,\$f29 | |
| -.*: 4ba20802 nor \$f0,\$f1,\$f2 | |
| -.*: 4bc520c2 and \$f3,\$f4,\$f5 | |
| -.*: 4b08398f srl \$f6,\$f7,\$f8 | |
| -.*: 4b2b524f dsrl \$f9,\$f10,\$f11 | |
| -.*: 4b4e6b0f sra \$f12,\$f13,\$f14 | |
| -.*: 4b7183cf dsra \$f15,\$f16,\$f17 | |
| -.*: 4b93900c sequ \$f18,\$f19 | |
| -.*: 4b95a00d sltu \$f20,\$f21 | |
| -.*: 4b97b00e sleu \$f22,\$f23 | |
| -.*: 4bb9c00c seq \$f24,\$f25 | |
| -.*: 4bbbd00d slt \$f26,\$f27 | |
| -.*: 4bbde00e sle \$f28,\$f29 | |
| - | |
| -000001ac <mips5_ps_insns>: | |
| +[0-9a-f]+ <mips5_ps_insns>: | |
| .*: 46c01005 abs.ps \$f0,\$f2 | |
| .*: 46c62080 add.ps \$f2,\$f4,\$f6 | |
| .*: 46ca4032 c.eq.ps \$f8,\$f10 | |
| diff --git a/gas/testsuite/gas/mips/loongson-2f.s b/gas/testsuite/gas/mips/loongson-2f.s | |
| index 4b47a99..412b139 100644 | |
| --- a/gas/testsuite/gas/mips/loongson-2f.s | |
| +++ b/gas/testsuite/gas/mips/loongson-2f.s | |
| @@ -34,90 +34,6 @@ fpu_insns: | |
| nmsub.d $f0, $f1, $f2 | |
| nmsub.ps $f3, $f4, $f5 | |
| -simd_insns: | |
| - packsshb $f0, $f1, $f2 | |
| - packsswh $f3, $f4, $f5 | |
| - packushb $f6, $f7, $f8 | |
| - paddb $f9, $f10, $f11 | |
| - paddh $f12, $f13, $f14 | |
| - paddw $f15, $f16, $f17 | |
| - paddd $f18, $f19, $f20 | |
| - paddsb $f21, $f22, $f23 | |
| - paddsh $f24, $f25, $f26 | |
| - paddusb $f27, $f28, $f29 | |
| - paddush $f0, $f1, $f2 | |
| - pandn $f3, $f4, $f5 | |
| - pavgb $f6, $f7, $f8 | |
| - pavgh $f9, $f10, $f11 | |
| - pcmpeqb $f12, $f13, $f14 | |
| - pcmpeqh $f15, $f16, $f17 | |
| - pcmpeqw $f18, $f19, $f20 | |
| - pcmpgtb $f21, $f22, $f23 | |
| - pcmpgth $f24, $f25, $f26 | |
| - pcmpgtw $f27, $f28, $f29 | |
| - pextrh $f0, $f1, $f2 | |
| - pinsrh_0 $f3, $f4, $f5 | |
| - pinsrh_1 $f6, $f7, $f8 | |
| - pinsrh_2 $f9, $f10, $f11 | |
| - pinsrh_3 $f12, $f13, $f14 | |
| - pmaddhw $f15, $f16, $f17 | |
| - pmaxsh $f18, $f19, $f20 | |
| - pmaxub $f21, $f22, $f23 | |
| - pminsh $f24, $f25, $f26 | |
| - pminub $f27, $f28, $f29 | |
| - pmovmskb $f0, $f1 | |
| - pmulhuh $f2, $f3, $f4 | |
| - pmulhh $f5, $f6, $f7 | |
| - pmullh $f8, $f9, $f10 | |
| - pmuluw $f11, $f12, $f13 | |
| - pasubub $f14, $f15, $f16 | |
| - biadd $f17, $f18 | |
| - pshufh $f19, $f20, $f21 | |
| - psllh $f22, $f23, $f24 | |
| - psllw $f25, $f26, $f27 | |
| - psrah $f28, $f29, $f30 | |
| - psraw $f0, $f1, $f2 | |
| - psrlh $f3, $f4, $f5 | |
| - psrlw $f6, $f7, $f8 | |
| - psubb $f9, $f10, $f11 | |
| - psubh $f12, $f13, $f14 | |
| - psubw $f15, $f16, $f17 | |
| - psubd $f18, $f19, $f20 | |
| - psubsb $f21, $f22, $f23 | |
| - psubsh $f24, $f25, $f26 | |
| - psubusb $f27, $f28, $f29 | |
| - psubush $f0, $f1, $f2 | |
| - punpckhbh $f3, $f4, $f5 | |
| - punpckhhw $f6, $f7, $f8 | |
| - punpckhwd $f9, $f10, $f11 | |
| - punpcklbh $f12, $f13, $f14 | |
| - punpcklhw $f15, $f16, $f17 | |
| - punpcklwd $f18, $f19, $f20 | |
| - | |
| -fixed_point_insns: | |
| - add $f0, $f1, $f2 | |
| - addu $f3, $f4, $f5 | |
| - dadd $f6, $f7, $f8 | |
| - sub $f9, $f10, $f11 | |
| - subu $f12, $f13, $f14 | |
| - dsub $f15, $f16, $f17 | |
| - or $f18, $f19, $f20 | |
| - sll $f21, $f22, $f23 | |
| - dsll $f24, $f25, $f26 | |
| - xor $f27, $f28, $f29 | |
| - nor $f0, $f1, $f2 | |
| - and $f3, $f4, $f5 | |
| - srl $f6, $f7, $f8 | |
| - dsrl $f9, $f10, $f11 | |
| - sra $f12, $f13, $f14 | |
| - dsra $f15, $f16, $f17 | |
| - sequ $f18, $f19 | |
| - sltu $f20, $f21 | |
| - sleu $f22, $f23 | |
| - seq $f24, $f25 | |
| - slt $f26, $f27 | |
| - sle $f28, $f29 | |
| - | |
| mips5_ps_insns: | |
| abs.ps $f0, $f2 | |
| add.ps $f2, $f4, $f6 | |
| diff --git a/gas/testsuite/gas/mips/loongson-3a-2.d b/gas/testsuite/gas/mips/loongson-3a-2.d | |
| index 32fea2e..e80b98b 100644 | |
| --- a/gas/testsuite/gas/mips/loongson-3a-2.d | |
| +++ b/gas/testsuite/gas/mips/loongson-3a-2.d | |
| @@ -7,10 +7,6 @@ | |
| Disassembly of section .text: | |
| [0-9a-f]+ <.text>: | |
| -.*: 70601075 campi \$2,\$3 | |
| -.*: 70a02035 campv \$4,\$5 | |
| -.*: 70e830b5 camwi \$6,\$7,\$8 | |
| -.*: 714048f5 ramri \$9,\$10 | |
| .*: 716c0026 gsle \$11,\$12 | |
| .*: 71ae0027 gsgt \$13,\$14 | |
| .*: c8622010 gslble \$2,\$3,\$4 | |
| diff --git a/gas/testsuite/gas/mips/loongson-3a-2.s b/gas/testsuite/gas/mips/loongson-3a-2.s | |
| index c296b06..85df10a 100644 | |
| --- a/gas/testsuite/gas/mips/loongson-3a-2.s | |
| +++ b/gas/testsuite/gas/mips/loongson-3a-2.s | |
| @@ -1,11 +1,6 @@ | |
| .text | |
| .set noreorder | |
| - campi $2,$3 | |
| - campv $4,$5 | |
| - camwi $6,$7,$8 | |
| - ramri $9,$10 | |
| - | |
| gsle $11,$12 | |
| gsgt $13,$14 | |
| diff --git a/gas/testsuite/gas/mips/loongson-3a-mmi.d b/gas/testsuite/gas/mips/loongson-3a-mmi.d | |
| new file mode 100644 | |
| index 0000000..3a52c5a | |
| --- /dev/null | |
| +++ b/gas/testsuite/gas/mips/loongson-3a-mmi.d | |
| @@ -0,0 +1,108 @@ | |
| +#as: -march=loongson3a -mabi=o64 | |
| +#objdump: -M reg-names=numeric -dp | |
| +#name: Loongson-3A MMI tests | |
| + | |
| +.*: file format .* | |
| + | |
| +private flags = .* | |
| + | |
| +MIPS ABI Flags Version: 0 | |
| +ISA: .* | |
| +GPR size: .* | |
| +CPR1 size: .* | |
| +CPR2 size: .* | |
| +FP ABI: .* | |
| +ISA Extension: None | |
| +ASEs: | |
| + Loongson MMI ASE | |
| + Loongson CAM ASE | |
| + Loongson EXT ASE | |
| +FLAGS 1: .* | |
| +FLAGS 2: .* | |
| + | |
| +Disassembly of section .text: | |
| + | |
| +[0-9a-f]+ <simd_insns>: | |
| +.*: 4b420802 packsshb \$f0,\$f1,\$f2 | |
| +.*: 4b2520c2 packsswh \$f3,\$f4,\$f5 | |
| +.*: 4b683982 packushb \$f6,\$f7,\$f8 | |
| +.*: 4bcb5240 paddb \$f9,\$f10,\$f11 | |
| +.*: 4b4e6b00 paddh \$f12,\$f13,\$f14 | |
| +.*: 4b7183c0 paddw \$f15,\$f16,\$f17 | |
| +.*: 4bf49c80 paddd \$f18,\$f19,\$f20 | |
| +.*: 4b97b540 paddsb \$f21,\$f22,\$f23 | |
| +.*: 4b1ace00 paddsh \$f24,\$f25,\$f26 | |
| +.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29 | |
| +.*: 4b220800 paddush \$f0,\$f1,\$f2 | |
| +.*: 4be520c2 pandn \$f3,\$f4,\$f5 | |
| +.*: 4b283988 pavgb \$f6,\$f7,\$f8 | |
| +.*: 4b0b5248 pavgh \$f9,\$f10,\$f11 | |
| +.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14 | |
| +.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17 | |
| +.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20 | |
| +.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23 | |
| +.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26 | |
| +.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29 | |
| +.*: 4b42080e pextrh \$f0,\$f1,\$f2 | |
| +.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5 | |
| +.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8 | |
| +.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11 | |
| +.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14 | |
| +.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17 | |
| +.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20 | |
| +.*: 4b97b548 pmaxub \$f21,\$f22,\$f23 | |
| +.*: 4b7ace08 pminsh \$f24,\$f25,\$f26 | |
| +.*: 4bbde6c8 pminub \$f27,\$f28,\$f29 | |
| +.*: 4ba0080f pmovmskb \$f0,\$f1 | |
| +.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4 | |
| +.*: 4b67314a pmulhh \$f5,\$f6,\$f7 | |
| +.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10 | |
| +.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13 | |
| +.*: 4b307b8d pasubub \$f14,\$f15,\$f16 | |
| +.*: 4b80944f biadd \$f17,\$f18 | |
| +.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21 | |
| +.*: 4b38bd8a psllh \$f22,\$f23,\$f24 | |
| +.*: 4b1bd64a psllw \$f25,\$f26,\$f27 | |
| +.*: 4b7eef0b psrah \$f28,\$f29,\$f30 | |
| +.*: 4b42080b psraw \$f0,\$f1,\$f2 | |
| +.*: 4b2520cb psrlh \$f3,\$f4,\$f5 | |
| +.*: 4b08398b psrlw \$f6,\$f7,\$f8 | |
| +.*: 4bcb5241 psubb \$f9,\$f10,\$f11 | |
| +.*: 4b4e6b01 psubh \$f12,\$f13,\$f14 | |
| +.*: 4b7183c1 psubw \$f15,\$f16,\$f17 | |
| +.*: 4bf49c81 psubd \$f18,\$f19,\$f20 | |
| +.*: 4b97b541 psubsb \$f21,\$f22,\$f23 | |
| +.*: 4b1ace01 psubsh \$f24,\$f25,\$f26 | |
| +.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29 | |
| +.*: 4b220801 psubush \$f0,\$f1,\$f2 | |
| +.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5 | |
| +.*: 4b283983 punpckhhw \$f6,\$f7,\$f8 | |
| +.*: 4bab524b punpckhwd \$f9,\$f10,\$f11 | |
| +.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14 | |
| +.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17 | |
| +.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20 | |
| + | |
| +[0-9a-f]+ <fixed_point_insns>: | |
| +.*: 4b42080c add \$f0,\$f1,\$f2 | |
| +.*: 4b0520cc addu \$f3,\$f4,\$f5 | |
| +.*: 4b68398c dadd \$f6,\$f7,\$f8 | |
| +.*: 4b4b524d sub \$f9,\$f10,\$f11 | |
| +.*: 4b0e6b0d subu \$f12,\$f13,\$f14 | |
| +.*: 4b7183cd dsub \$f15,\$f16,\$f17 | |
| +.*: 4b349c8c or \$f18,\$f19,\$f20 | |
| +.*: 4b17b54e sll \$f21,\$f22,\$f23 | |
| +.*: 4b3ace0e dsll \$f24,\$f25,\$f26 | |
| +.*: 4b9de6c2 xor \$f27,\$f28,\$f29 | |
| +.*: 4ba20802 nor \$f0,\$f1,\$f2 | |
| +.*: 4bc520c2 and \$f3,\$f4,\$f5 | |
| +.*: 4b08398f srl \$f6,\$f7,\$f8 | |
| +.*: 4b2b524f dsrl \$f9,\$f10,\$f11 | |
| +.*: 4b4e6b0f sra \$f12,\$f13,\$f14 | |
| +.*: 4b7183cf dsra \$f15,\$f16,\$f17 | |
| +.*: 4b93900c sequ \$f18,\$f19 | |
| +.*: 4b95a00d sltu \$f20,\$f21 | |
| +.*: 4b97b00e sleu \$f22,\$f23 | |
| +.*: 4bb9c00c seq \$f24,\$f25 | |
| +.*: 4bbbd00d slt \$f26,\$f27 | |
| +.*: 4bbde00e sle \$f28,\$f29 | |
| +#pass | |
| diff --git a/gas/testsuite/gas/mips/loongson-3a-mmi.s b/gas/testsuite/gas/mips/loongson-3a-mmi.s | |
| new file mode 100644 | |
| index 0000000..e87d66e | |
| --- /dev/null | |
| +++ b/gas/testsuite/gas/mips/loongson-3a-mmi.s | |
| @@ -0,0 +1,86 @@ | |
| + .text | |
| + .set noreorder | |
| + | |
| +simd_insns: | |
| + packsshb $f0, $f1, $f2 | |
| + packsswh $f3, $f4, $f5 | |
| + packushb $f6, $f7, $f8 | |
| + paddb $f9, $f10, $f11 | |
| + paddh $f12, $f13, $f14 | |
| + paddw $f15, $f16, $f17 | |
| + paddd $f18, $f19, $f20 | |
| + paddsb $f21, $f22, $f23 | |
| + paddsh $f24, $f25, $f26 | |
| + paddusb $f27, $f28, $f29 | |
| + paddush $f0, $f1, $f2 | |
| + pandn $f3, $f4, $f5 | |
| + pavgb $f6, $f7, $f8 | |
| + pavgh $f9, $f10, $f11 | |
| + pcmpeqb $f12, $f13, $f14 | |
| + pcmpeqh $f15, $f16, $f17 | |
| + pcmpeqw $f18, $f19, $f20 | |
| + pcmpgtb $f21, $f22, $f23 | |
| + pcmpgth $f24, $f25, $f26 | |
| + pcmpgtw $f27, $f28, $f29 | |
| + pextrh $f0, $f1, $f2 | |
| + pinsrh_0 $f3, $f4, $f5 | |
| + pinsrh_1 $f6, $f7, $f8 | |
| + pinsrh_2 $f9, $f10, $f11 | |
| + pinsrh_3 $f12, $f13, $f14 | |
| + pmaddhw $f15, $f16, $f17 | |
| + pmaxsh $f18, $f19, $f20 | |
| + pmaxub $f21, $f22, $f23 | |
| + pminsh $f24, $f25, $f26 | |
| + pminub $f27, $f28, $f29 | |
| + pmovmskb $f0, $f1 | |
| + pmulhuh $f2, $f3, $f4 | |
| + pmulhh $f5, $f6, $f7 | |
| + pmullh $f8, $f9, $f10 | |
| + pmuluw $f11, $f12, $f13 | |
| + pasubub $f14, $f15, $f16 | |
| + biadd $f17, $f18 | |
| + pshufh $f19, $f20, $f21 | |
| + psllh $f22, $f23, $f24 | |
| + psllw $f25, $f26, $f27 | |
| + psrah $f28, $f29, $f30 | |
| + psraw $f0, $f1, $f2 | |
| + psrlh $f3, $f4, $f5 | |
| + psrlw $f6, $f7, $f8 | |
| + psubb $f9, $f10, $f11 | |
| + psubh $f12, $f13, $f14 | |
| + psubw $f15, $f16, $f17 | |
| + psubd $f18, $f19, $f20 | |
| + psubsb $f21, $f22, $f23 | |
| + psubsh $f24, $f25, $f26 | |
| + psubusb $f27, $f28, $f29 | |
| + psubush $f0, $f1, $f2 | |
| + punpckhbh $f3, $f4, $f5 | |
| + punpckhhw $f6, $f7, $f8 | |
| + punpckhwd $f9, $f10, $f11 | |
| + punpcklbh $f12, $f13, $f14 | |
| + punpcklhw $f15, $f16, $f17 | |
| + punpcklwd $f18, $f19, $f20 | |
| + | |
| +fixed_point_insns: | |
| + add $f0, $f1, $f2 | |
| + addu $f3, $f4, $f5 | |
| + dadd $f6, $f7, $f8 | |
| + sub $f9, $f10, $f11 | |
| + subu $f12, $f13, $f14 | |
| + dsub $f15, $f16, $f17 | |
| + or $f18, $f19, $f20 | |
| + sll $f21, $f22, $f23 | |
| + dsll $f24, $f25, $f26 | |
| + xor $f27, $f28, $f29 | |
| + nor $f0, $f1, $f2 | |
| + and $f3, $f4, $f5 | |
| + srl $f6, $f7, $f8 | |
| + dsrl $f9, $f10, $f11 | |
| + sra $f12, $f13, $f14 | |
| + dsra $f15, $f16, $f17 | |
| + sequ $f18, $f19 | |
| + sltu $f20, $f21 | |
| + sleu $f22, $f23 | |
| + seq $f24, $f25 | |
| + slt $f26, $f27 | |
| + sle $f28, $f29 | |
| diff --git a/gas/testsuite/gas/mips/loongson-3a.d b/gas/testsuite/gas/mips/loongson-3a.d | |
| index f0eb0e3..4a4b853 100644 | |
| --- a/gas/testsuite/gas/mips/loongson-3a.d | |
| +++ b/gas/testsuite/gas/mips/loongson-3a.d | |
| @@ -22,90 +22,6 @@ Disassembly of section .text: | |
| .*: 73dfe81e gsmodu \$29,\$30,\$31 | |
| .*: 7064101d gsdmod \$2,\$3,\$4 | |
| .*: 70c7281f gsdmodu \$5,\$6,\$7 | |
| - | |
| -[0-9a-f]+ <simd_insns>: | |
| -.*: 4b420802 packsshb \$f0,\$f1,\$f2 | |
| -.*: 4b2520c2 packsswh \$f3,\$f4,\$f5 | |
| -.*: 4b683982 packushb \$f6,\$f7,\$f8 | |
| -.*: 4bcb5240 paddb \$f9,\$f10,\$f11 | |
| -.*: 4b4e6b00 paddh \$f12,\$f13,\$f14 | |
| -.*: 4b7183c0 paddw \$f15,\$f16,\$f17 | |
| -.*: 4bf49c80 paddd \$f18,\$f19,\$f20 | |
| -.*: 4b97b540 paddsb \$f21,\$f22,\$f23 | |
| -.*: 4b1ace00 paddsh \$f24,\$f25,\$f26 | |
| -.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29 | |
| -.*: 4b220800 paddush \$f0,\$f1,\$f2 | |
| -.*: 4be520c2 pandn \$f3,\$f4,\$f5 | |
| -.*: 4b283988 pavgb \$f6,\$f7,\$f8 | |
| -.*: 4b0b5248 pavgh \$f9,\$f10,\$f11 | |
| -.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14 | |
| -.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17 | |
| -.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20 | |
| -.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23 | |
| -.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26 | |
| -.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29 | |
| -.*: 4b42080e pextrh \$f0,\$f1,\$f2 | |
| -.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5 | |
| -.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8 | |
| -.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11 | |
| -.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14 | |
| -.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17 | |
| -.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20 | |
| -.*: 4b97b548 pmaxub \$f21,\$f22,\$f23 | |
| -.*: 4b7ace08 pminsh \$f24,\$f25,\$f26 | |
| -.*: 4bbde6c8 pminub \$f27,\$f28,\$f29 | |
| -.*: 4ba0080f pmovmskb \$f0,\$f1 | |
| -.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4 | |
| -.*: 4b67314a pmulhh \$f5,\$f6,\$f7 | |
| -.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10 | |
| -.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13 | |
| -.*: 4b307b8d pasubub \$f14,\$f15,\$f16 | |
| -.*: 4b80944f biadd \$f17,\$f18 | |
| -.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21 | |
| -.*: 4b38bd8a psllh \$f22,\$f23,\$f24 | |
| -.*: 4b1bd64a psllw \$f25,\$f26,\$f27 | |
| -.*: 4b7eef0b psrah \$f28,\$f29,\$f30 | |
| -.*: 4b42080b psraw \$f0,\$f1,\$f2 | |
| -.*: 4b2520cb psrlh \$f3,\$f4,\$f5 | |
| -.*: 4b08398b psrlw \$f6,\$f7,\$f8 | |
| -.*: 4bcb5241 psubb \$f9,\$f10,\$f11 | |
| -.*: 4b4e6b01 psubh \$f12,\$f13,\$f14 | |
| -.*: 4b7183c1 psubw \$f15,\$f16,\$f17 | |
| -.*: 4bf49c81 psubd \$f18,\$f19,\$f20 | |
| -.*: 4b97b541 psubsb \$f21,\$f22,\$f23 | |
| -.*: 4b1ace01 psubsh \$f24,\$f25,\$f26 | |
| -.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29 | |
| -.*: 4b220801 psubush \$f0,\$f1,\$f2 | |
| -.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5 | |
| -.*: 4b283983 punpckhhw \$f6,\$f7,\$f8 | |
| -.*: 4bab524b punpckhwd \$f9,\$f10,\$f11 | |
| -.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14 | |
| -.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17 | |
| -.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20 | |
| - | |
| -[0-9a-f]+ <fixed_point_insns>: | |
| -.*: 4b42080c add \$f0,\$f1,\$f2 | |
| -.*: 4b0520cc addu \$f3,\$f4,\$f5 | |
| -.*: 4b68398c dadd \$f6,\$f7,\$f8 | |
| -.*: 4b4b524d sub \$f9,\$f10,\$f11 | |
| -.*: 4b0e6b0d subu \$f12,\$f13,\$f14 | |
| -.*: 4b7183cd dsub \$f15,\$f16,\$f17 | |
| -.*: 4b349c8c or \$f18,\$f19,\$f20 | |
| -.*: 4b17b54e sll \$f21,\$f22,\$f23 | |
| -.*: 4b3ace0e dsll \$f24,\$f25,\$f26 | |
| -.*: 4b9de6c2 xor \$f27,\$f28,\$f29 | |
| -.*: 4ba20802 nor \$f0,\$f1,\$f2 | |
| -.*: 4bc520c2 and \$f3,\$f4,\$f5 | |
| -.*: 4b08398f srl \$f6,\$f7,\$f8 | |
| -.*: 4b2b524f dsrl \$f9,\$f10,\$f11 | |
| -.*: 4b4e6b0f sra \$f12,\$f13,\$f14 | |
| -.*: 4b7183cf dsra \$f15,\$f16,\$f17 | |
| -.*: 4b93900c sequ \$f18,\$f19 | |
| -.*: 4b95a00d sltu \$f20,\$f21 | |
| -.*: 4b97b00e sleu \$f22,\$f23 | |
| -.*: 4bb9c00c seq \$f24,\$f25 | |
| -.*: 4bbbd00d slt \$f26,\$f27 | |
| -.*: 4bbde00e sle \$f28,\$f29 | |
| #pass | |
| diff --git a/gas/testsuite/gas/mips/loongson-3a.s b/gas/testsuite/gas/mips/loongson-3a.s | |
| index 73c00c0..45bc90f 100644 | |
| --- a/gas/testsuite/gas/mips/loongson-3a.s | |
| +++ b/gas/testsuite/gas/mips/loongson-3a.s | |
| @@ -18,88 +18,4 @@ integer_insns: | |
| gsdmod $2, $3, $4 | |
| gsdmodu $5, $6, $7 | |
| -simd_insns: | |
| - packsshb $f0, $f1, $f2 | |
| - packsswh $f3, $f4, $f5 | |
| - packushb $f6, $f7, $f8 | |
| - paddb $f9, $f10, $f11 | |
| - paddh $f12, $f13, $f14 | |
| - paddw $f15, $f16, $f17 | |
| - paddd $f18, $f19, $f20 | |
| - paddsb $f21, $f22, $f23 | |
| - paddsh $f24, $f25, $f26 | |
| - paddusb $f27, $f28, $f29 | |
| - paddush $f0, $f1, $f2 | |
| - pandn $f3, $f4, $f5 | |
| - pavgb $f6, $f7, $f8 | |
| - pavgh $f9, $f10, $f11 | |
| - pcmpeqb $f12, $f13, $f14 | |
| - pcmpeqh $f15, $f16, $f17 | |
| - pcmpeqw $f18, $f19, $f20 | |
| - pcmpgtb $f21, $f22, $f23 | |
| - pcmpgth $f24, $f25, $f26 | |
| - pcmpgtw $f27, $f28, $f29 | |
| - pextrh $f0, $f1, $f2 | |
| - pinsrh_0 $f3, $f4, $f5 | |
| - pinsrh_1 $f6, $f7, $f8 | |
| - pinsrh_2 $f9, $f10, $f11 | |
| - pinsrh_3 $f12, $f13, $f14 | |
| - pmaddhw $f15, $f16, $f17 | |
| - pmaxsh $f18, $f19, $f20 | |
| - pmaxub $f21, $f22, $f23 | |
| - pminsh $f24, $f25, $f26 | |
| - pminub $f27, $f28, $f29 | |
| - pmovmskb $f0, $f1 | |
| - pmulhuh $f2, $f3, $f4 | |
| - pmulhh $f5, $f6, $f7 | |
| - pmullh $f8, $f9, $f10 | |
| - pmuluw $f11, $f12, $f13 | |
| - pasubub $f14, $f15, $f16 | |
| - biadd $f17, $f18 | |
| - pshufh $f19, $f20, $f21 | |
| - psllh $f22, $f23, $f24 | |
| - psllw $f25, $f26, $f27 | |
| - psrah $f28, $f29, $f30 | |
| - psraw $f0, $f1, $f2 | |
| - psrlh $f3, $f4, $f5 | |
| - psrlw $f6, $f7, $f8 | |
| - psubb $f9, $f10, $f11 | |
| - psubh $f12, $f13, $f14 | |
| - psubw $f15, $f16, $f17 | |
| - psubd $f18, $f19, $f20 | |
| - psubsb $f21, $f22, $f23 | |
| - psubsh $f24, $f25, $f26 | |
| - psubusb $f27, $f28, $f29 | |
| - psubush $f0, $f1, $f2 | |
| - punpckhbh $f3, $f4, $f5 | |
| - punpckhhw $f6, $f7, $f8 | |
| - punpckhwd $f9, $f10, $f11 | |
| - punpcklbh $f12, $f13, $f14 | |
| - punpcklhw $f15, $f16, $f17 | |
| - punpcklwd $f18, $f19, $f20 | |
| - | |
| -fixed_point_insns: | |
| - add $f0, $f1, $f2 | |
| - addu $f3, $f4, $f5 | |
| - dadd $f6, $f7, $f8 | |
| - sub $f9, $f10, $f11 | |
| - subu $f12, $f13, $f14 | |
| - dsub $f15, $f16, $f17 | |
| - or $f18, $f19, $f20 | |
| - sll $f21, $f22, $f23 | |
| - dsll $f24, $f25, $f26 | |
| - xor $f27, $f28, $f29 | |
| - nor $f0, $f1, $f2 | |
| - and $f3, $f4, $f5 | |
| - srl $f6, $f7, $f8 | |
| - dsrl $f9, $f10, $f11 | |
| - sra $f12, $f13, $f14 | |
| - dsra $f15, $f16, $f17 | |
| - sequ $f18, $f19 | |
| - sltu $f20, $f21 | |
| - sleu $f22, $f23 | |
| - seq $f24, $f25 | |
| - slt $f26, $f27 | |
| - sle $f28, $f29 | |
| - | |
| diff --git a/gas/testsuite/gas/mips/loongson-cam.d b/gas/testsuite/gas/mips/loongson-cam.d | |
| new file mode 100644 | |
| index 0000000..ae973ea | |
| --- /dev/null | |
| +++ b/gas/testsuite/gas/mips/loongson-cam.d | |
| @@ -0,0 +1,27 @@ | |
| +#as: -mloongson-cam -mabi=64 | |
| +#objdump: -M reg-names=numeric -M loongson-cam -dp | |
| +#name: Loongson CAM tests | |
| + | |
| +.*: file format .* | |
| + | |
| +private flags = .* | |
| + | |
| +MIPS ABI Flags Version: 0 | |
| +ISA: .* | |
| +GPR size: .* | |
| +CPR1 size: .* | |
| +CPR2 size: .* | |
| +FP ABI: .* | |
| +ISA Extension: None | |
| +ASEs: | |
| + Loongson CAM ASE | |
| +FLAGS 1: .* | |
| +FLAGS 2: .* | |
| + | |
| +Disassembly of section .text: | |
| + | |
| +[0-9a-f]+ <.text>: | |
| +.*: 70601075 campi \$2,\$3 | |
| +.*: 70a02035 campv \$4,\$5 | |
| +.*: 70e830b5 camwi \$6,\$7,\$8 | |
| +.*: 714048f5 ramri \$9,\$10 | |
| diff --git a/gas/testsuite/gas/mips/loongson-cam.s b/gas/testsuite/gas/mips/loongson-cam.s | |
| new file mode 100644 | |
| index 0000000..688e9d4 | |
| --- /dev/null | |
| +++ b/gas/testsuite/gas/mips/loongson-cam.s | |
| @@ -0,0 +1,7 @@ | |
| + .text | |
| + .set noreorder | |
| + | |
| + campi $2,$3 | |
| + campv $4,$5 | |
| + camwi $6,$7,$8 | |
| + ramri $9,$10 | |
| diff --git a/gas/testsuite/gas/mips/loongson-ext2.d b/gas/testsuite/gas/mips/loongson-ext2.d | |
| new file mode 100644 | |
| index 0000000..d821386 | |
| --- /dev/null | |
| +++ b/gas/testsuite/gas/mips/loongson-ext2.d | |
| @@ -0,0 +1,28 @@ | |
| +#as: -mloongson-ext2 -mabi=64 | |
| +#objdump: -M reg-names=numeric -M loongson-ext2 -dp | |
| +#name: Loongson EXT2 tests | |
| + | |
| +.*: file format .* | |
| + | |
| +private flags = .* | |
| + | |
| +MIPS ABI Flags Version: 0 | |
| +ISA: .* | |
| +GPR size: .* | |
| +CPR1 size: .* | |
| +CPR2 size: .* | |
| +FP ABI: .* | |
| +ISA Extension: None | |
| +ASEs: | |
| + Loongson EXT ASE | |
| + Loongson EXT2 ASE | |
| +FLAGS 1: .* | |
| +FLAGS 2: .* | |
| + | |
| +Disassembly of section .text: | |
| + | |
| +[0-9a-f]+ <.text>: | |
| +.*: 70801062 cto \$2,\$4 | |
| +.*: 70801022 ctz \$2,\$4 | |
| +.*: 708010e2 dcto \$2,\$4 | |
| +.*: 708010a2 dctz \$2,\$4 | |
| diff --git a/gas/testsuite/gas/mips/loongson-ext2.s b/gas/testsuite/gas/mips/loongson-ext2.s | |
| new file mode 100644 | |
| index 0000000..023a469 | |
| --- /dev/null | |
| +++ b/gas/testsuite/gas/mips/loongson-ext2.s | |
| @@ -0,0 +1,7 @@ | |
| + .text | |
| + .set noreorder | |
| + | |
| + cto $2,$4 | |
| + ctz $2,$4 | |
| + dcto $2,$4 | |
| + dctz $2,$4 | |
| diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp | |
| index 74c39d4..4de8771 100644 | |
| --- a/gas/testsuite/gas/mips/mips.exp | |
| +++ b/gas/testsuite/gas/mips/mips.exp | |
| @@ -1385,6 +1385,15 @@ if { [istarget mips*-*-vxworks*] } { | |
| run_dump_test "loongson-3a-2" | |
| run_dump_test "loongson-3a-3" | |
| + run_dump_test "loongson-2f-mmi" | |
| + run_dump_test "loongson-3a-mmi" | |
| + | |
| + run_dump_test "loongson-cam" | |
| + run_dump_test "loongson-ext2" | |
| + | |
| + run_dump_test_arches "loongson-cam" [mips_arch_list_matching gs464] | |
| + run_dump_test_arches "loongson-ext2" [mips_arch_list_matching gs464] | |
| + | |
| if { $has_newabi } { | |
| run_dump_test_arches "octeon" [mips_arch_list_matching octeon] | |
| } | |
| diff --git a/gold/mips.cc b/gold/mips.cc | |
| index 543a234..5795bd9 100644 | |
| --- a/gold/mips.cc | |
| +++ b/gold/mips.cc | |
| @@ -3984,7 +3984,9 @@ class Target_mips : public Sized_target<size, big_endian> | |
| mach_mips5 = 5, | |
| mach_mips_loongson_2e = 3001, | |
| mach_mips_loongson_2f = 3002, | |
| - mach_mips_loongson_3a = 3003, | |
| + mach_mips_gs464 = 3003, | |
| + mach_mips_gs464e = 3004, | |
| + mach_mips_gs264e = 3005, | |
| mach_mips_sb1 = 12310201, // octal 'SB', 01 | |
| mach_mips_octeon = 6501, | |
| mach_mips_octeonp = 6601, | |
| @@ -4150,7 +4152,9 @@ class Target_mips : public Sized_target<size, big_endian> | |
| this->add_extension(mach_mips_octeon2, mach_mips_octeonp); | |
| this->add_extension(mach_mips_octeonp, mach_mips_octeon); | |
| this->add_extension(mach_mips_octeon, mach_mipsisa64r2); | |
| - this->add_extension(mach_mips_loongson_3a, mach_mipsisa64r2); | |
| + this->add_extension(mach_mips_gs264e, mach_mips_gs464e); | |
| + this->add_extension(mach_mips_gs464e, mach_mips_gs464); | |
| + this->add_extension(mach_mips_gs464, mach_mipsisa64r2); | |
| // MIPS64 extensions. | |
| this->add_extension(mach_mipsisa64r2, mach_mipsisa64); | |
| @@ -8884,8 +8888,14 @@ Target_mips<size, big_endian>::elf_mips_mach(elfcpp::Elf_Word flags) | |
| case elfcpp::E_MIPS_MACH_LS2F: | |
| return mach_mips_loongson_2f; | |
| - case elfcpp::E_MIPS_MACH_LS3A: | |
| - return mach_mips_loongson_3a; | |
| + case elfcpp::E_MIPS_MACH_GS464: | |
| + return mach_mips_gs464; | |
| + | |
| + case elfcpp::E_MIPS_MACH_GS464E: | |
| + return mach_mips_gs464e; | |
| + | |
| + case elfcpp::E_MIPS_MACH_GS264E: | |
| + return mach_mips_gs264e; | |
| case elfcpp::E_MIPS_MACH_OCTEON3: | |
| return mach_mips_octeon3; | |
| @@ -8985,9 +8995,6 @@ Target_mips<size, big_endian>::mips_isa_ext_mach(unsigned int isa_ext) | |
| case elfcpp::AFL_EXT_LOONGSON_2F: | |
| return mach_mips_loongson_2f; | |
| - case elfcpp::AFL_EXT_LOONGSON_3A: | |
| - return mach_mips_loongson_3a; | |
| - | |
| case elfcpp::AFL_EXT_SB1: | |
| return mach_mips_sb1; | |
| @@ -9052,9 +9059,6 @@ Target_mips<size, big_endian>::mips_isa_ext(unsigned int mips_mach) | |
| case mach_mips_loongson_2f: | |
| return elfcpp::AFL_EXT_LOONGSON_2F; | |
| - case mach_mips_loongson_3a: | |
| - return elfcpp::AFL_EXT_LOONGSON_3A; | |
| - | |
| case mach_mips_sb1: | |
| return elfcpp::AFL_EXT_SB1; | |
| @@ -9186,7 +9190,7 @@ Target_mips<size, big_endian>::infer_abiflags( | |
| && abiflags->fp_abi != elfcpp::Val_GNU_MIPS_ABI_FP_SOFT | |
| && abiflags->fp_abi != elfcpp::Val_GNU_MIPS_ABI_FP_64A | |
| && abiflags->isa_level >= 32 | |
| - && abiflags->isa_ext != elfcpp::AFL_EXT_LOONGSON_3A) | |
| + && abiflags->ases != elfcpp::AFL_ASE_LOONGSON_EXT) | |
| abiflags->flags1 |= elfcpp::AFL_FLAGS1_ODDSPREG; | |
| } | |
| @@ -12556,8 +12560,12 @@ Target_mips<size, big_endian>::elf_mips_mach_name(elfcpp::Elf_Word e_flags) | |
| return "mips:loongson_2e"; | |
| case elfcpp::E_MIPS_MACH_LS2F: | |
| return "mips:loongson_2f"; | |
| - case elfcpp::E_MIPS_MACH_LS3A: | |
| - return "mips:loongson_3a"; | |
| + case elfcpp::E_MIPS_MACH_GS464: | |
| + return "mips:gs464"; | |
| + case elfcpp::E_MIPS_MACH_GS464E: | |
| + return "mips:gs464e"; | |
| + case elfcpp::E_MIPS_MACH_GS264E: | |
| + return "mips:gs264e"; | |
| case elfcpp::E_MIPS_MACH_OCTEON: | |
| return "mips:octeon"; | |
| case elfcpp::E_MIPS_MACH_OCTEON2: | |
| diff --git a/include/elf/mips.h b/include/elf/mips.h | |
| index 9de0b4e..fd02955 100644 | |
| --- a/include/elf/mips.h | |
| +++ b/include/elf/mips.h | |
| @@ -299,7 +299,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext) | |
| #define E_MIPS_MACH_9000 0x00990000 | |
| #define E_MIPS_MACH_LS2E 0x00A00000 | |
| #define E_MIPS_MACH_LS2F 0x00A10000 | |
| -#define E_MIPS_MACH_LS3A 0x00A20000 | |
| +#define E_MIPS_MACH_GS464 0x00A20000 | |
| +#define E_MIPS_MACH_GS464E 0x00A30000 | |
| +#define E_MIPS_MACH_GS264E 0x00A40000 | |
| /* Processor specific section indices. These sections do not actually | |
| exist. Symbols with a st_shndx field corresponding to one of these | |
| @@ -1235,14 +1237,17 @@ extern void bfd_mips_elf_swap_abiflags_v0_out | |
| #define AFL_ASE_XPA 0x00001000 /* XPA ASE. */ | |
| #define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */ | |
| #define AFL_ASE_MIPS16E2 0x00004000 /* MIPS16e2 ASE. */ | |
| -#define AFL_ASE_MASK 0x00007fff /* All ASEs. */ | |
| +#define AFL_ASE_LOONGSON_MMI 0x00040000 /* Loongson MMI ASE. */ | |
| +#define AFL_ASE_LOONGSON_CAM 0x00080000 /* Loongson CAM ASE. */ | |
| +#define AFL_ASE_LOONGSON_EXT 0x00100000 /* Loongson EXT instructions. */ | |
| +#define AFL_ASE_LOONGSON_EXT2 0x00200000 /* Loongson EXT2 instructions. */ | |
| +#define AFL_ASE_MASK 0x003effff /* All ASEs. */ | |
| /* Values for the isa_ext word of an ABI flags structure. */ | |
| #define AFL_EXT_XLR 1 /* RMI Xlr instruction. */ | |
| #define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */ | |
| #define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */ | |
| -#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */ | |
| #define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */ | |
| #define AFL_EXT_5900 6 /* MIPS R5900 instruction. */ | |
| #define AFL_EXT_4650 7 /* MIPS R4650 instruction. */ | |
| diff --git a/include/opcode/mips.h b/include/opcode/mips.h | |
| index a8036ab..2a32c1e 100644 | |
| --- a/include/opcode/mips.h | |
| +++ b/include/opcode/mips.h | |
| @@ -928,7 +928,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) | |
| "+S" Length-minus-one field of cins/exts. Requires msb position | |
| of the field to be <= 63. | |
| - Loongson-3A: | |
| + Loongson-ext ASE: | |
| "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) | |
| "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) | |
| "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) | |
| @@ -1256,8 +1256,6 @@ static const unsigned int mips_isa_table[] = { | |
| #define INSN_LOONGSON_2E 0x40000000 | |
| /* ST Microelectronics Loongson 2F. */ | |
| #define INSN_LOONGSON_2F 0x80000000 | |
| -/* Loongson 3A. */ | |
| -#define INSN_LOONGSON_3A 0x00000400 | |
| /* RMI Xlr instruction */ | |
| #define INSN_XLR 0x00000020 | |
| /* Imagination interAptiv MR2. */ | |
| @@ -1297,6 +1295,14 @@ static const unsigned int mips_isa_table[] = { | |
| /* The Virtualization ASE has eXtended Physical Addressing (XPA) | |
| instructions which are only valid when both ASEs are enabled. */ | |
| #define ASE_XPA_VIRT 0x00020000 | |
| +/* Loongson MultiMedia extensions Instructions (MMI). */ | |
| +#define ASE_LOONGSON_MMI 0x00200000 | |
| +/* Loongson Content Address Memory (CAM). */ | |
| +#define ASE_LOONGSON_CAM 0x00400000 | |
| +/* Loongson EXTensions (EXT) instructions. */ | |
| +#define ASE_LOONGSON_EXT 0x00800000 | |
| +/* Loongson EXTensions R2 (EXT2) instructions. */ | |
| +#define ASE_LOONGSON_EXT2 0x01000000 | |
| /* MIPS ISA defines, use instead of hardcoding ISA level. */ | |
| @@ -1361,7 +1367,9 @@ static const unsigned int mips_isa_table[] = { | |
| #define CPU_SB1 12310201 /* octal 'SB', 01. */ | |
| #define CPU_LOONGSON_2E 3001 | |
| #define CPU_LOONGSON_2F 3002 | |
| -#define CPU_LOONGSON_3A 3003 | |
| +#define CPU_GS464 3003 | |
| +#define CPU_GS464E 3004 | |
| +#define CPU_GS264E 3005 | |
| #define CPU_OCTEON 6501 | |
| #define CPU_OCTEONP 6601 | |
| #define CPU_OCTEON2 6502 | |
| @@ -1420,9 +1428,6 @@ cpu_is_member (int cpu, unsigned int mask) | |
| case CPU_LOONGSON_2F: | |
| return (mask & INSN_LOONGSON_2F) != 0; | |
| - case CPU_LOONGSON_3A: | |
| - return (mask & INSN_LOONGSON_3A) != 0; | |
| - | |
| case CPU_OCTEON: | |
| return (mask & INSN_OCTEON) != 0; | |
| diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp | |
| index 654f8ae..813ca2f 100644 | |
| --- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp | |
| +++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp | |
| @@ -36,6 +36,32 @@ if {[istarget mips*-*-irix6*]} { | |
| set ldemul "" | |
| } | |
| +# Check is ld supported 32bit emulations. | |
| +proc check_ld_support_32bit { } { | |
| + global ld | |
| + global echo | |
| + | |
| + set ld_output [remote_exec host $ld "-V"] | |
| + if [string match "*elf32*" $ld_output] then { | |
| + return 1 | |
| + } else { | |
| + return 0 | |
| + } | |
| +} | |
| + | |
| +# Check args is 32bit abis. | |
| +proc check_is_32bit_args {arg} { | |
| + | |
| + if { [string match "*-32*" $arg] | |
| + || [string match "*-mabi=32*" $arg] | |
| + || [string match "*-mabi=o64*" $arg] | |
| + || [string match "*-mgp32*" $arg] } { | |
| + return 1 | |
| + } else { | |
| + return 0 | |
| + } | |
| +} | |
| + | |
| # Assemble jr.s using each of the argument lists in ARGLIST. Return the | |
| # list of object files on success and an empty list on failure. | |
| proc assemble_for_flags {arglist} { | |
| @@ -70,6 +96,13 @@ proc good_combination {arglist flags args} { | |
| set testname "MIPS compatible objects: $arglist" | |
| set objs [assemble_for_flags $arglist] | |
| + foreach argsl $arglist { | |
| + if { [check_is_32bit_args $argsl] && ![check_ld_support_32bit] } { | |
| + unsupported $testname | |
| + return 0 | |
| + } | |
| + } | |
| + | |
| if {$objs == ""} { | |
| unresolved $testname | |
| } elseif {![ld_link "$ld $ldemul" $finalobj "-r $objs"]} { | |
| @@ -94,7 +127,12 @@ proc good_combination {arglist flags args} { | |
| foreach flag $flags { | |
| if {[lsearch -exact $gotflags $flag] < 0} { | |
| - set failed 1 | |
| + # The mips*-*-irix* not use o32 flags. | |
| + if {[istarget mips*-*-irix*] && $flag == "o32"} { | |
| + set failed 0 | |
| + } else { | |
| + set failed 1 | |
| + } | |
| } | |
| } | |
| @@ -156,6 +194,13 @@ proc bad_combination {arglist message} { | |
| set testname "MIPS incompatible objects: $arglist" | |
| set objs [assemble_for_flags $arglist] | |
| + foreach argsl $arglist { | |
| + if { [check_is_32bit_args $argsl] && ![check_ld_support_32bit] } { | |
| + unsupported $testname | |
| + return 0 | |
| + } | |
| + } | |
| + | |
| if {$objs == ""} { | |
| unresolved $testname | |
| } elseif {[ld_link "$ld $ldemul" $finalobj "-r $objs"] | |
| @@ -197,7 +242,7 @@ isa_conflict { "-march=sb1 -32" "-mips64r2 -32" } sb1 isa64r2 | |
| isa_conflict { "-march=vr4100 -32" "-march=r10000 -32" } 4100 8000 | |
| isa_conflict { "-march=r5900 -32" "-march=vr4111 -32" } 5900 4111 | |
| isa_conflict { "-march=loongson2e -32" "-march=loongson2f -32" } loongson_2e loongson_2f | |
| -isa_conflict { "-march=loongson3a -32" "-march=loongson2f -32" } loongson_3a loongson_2f | |
| +isa_conflict { "-march=gs464 -32" "-march=loongson2f -32" } gs464 loongson_2f | |
| isa_conflict { "-march=interaptiv-mr2 -32" \ | |
| "-march=r4010 -32" } interaptiv-mr2 4010 | |
| @@ -270,3 +315,12 @@ good_combination { "-march=interaptiv-mr2 -32" "-march=m5100 -32" } \ | |
| { mips32r2 interaptiv-mr2 } \ | |
| MIPS32r5 "Imagination interAptiv MR2" \ | |
| { "DSP ASE" "Enhanced VA Scheme" "MT ASE" } | |
| + | |
| +good_combination { "-march=gs464 -32" "-march=gs464e -32" } \ | |
| + { gs464e o32 } \ | |
| + MIPS64r2 "None" \ | |
| + { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" } | |
| +good_combination { "-march=gs264e -32" "-march=gs464e -32" } \ | |
| + { gs264e o32 } \ | |
| + MIPS64r2 "None" \ | |
| + { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" } | |
| diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c | |
| index 984fcbb..5b9e173 100644 | |
| --- a/opcodes/mips-dis.c | |
| +++ b/opcodes/mips-dis.c | |
| @@ -625,12 +625,29 @@ const struct mips_arch_choice mips_arch_choices[] = | |
| NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, | |
| { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, | |
| - ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric, | |
| + ISA_MIPS3 | INSN_LOONGSON_2F, ASE_LOONGSON_MMI, mips_cp0_names_numeric, | |
| NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, | |
| - { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, | |
| - ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, | |
| - NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, | |
| + /* The loongson3a is an alias of gs464 for compatibility */ | |
| + { "loongson3a", 1, bfd_mach_mips_gs464, CPU_GS464, | |
| + ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
| + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264, | |
| + mips_hwr_names_numeric }, | |
| + | |
| + { "g464", 1, bfd_mach_mips_gs464, CPU_GS464, | |
| + ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
| + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264, | |
| + mips_hwr_names_numeric }, | |
| + | |
| + { "g464e", 1, bfd_mach_mips_gs464e, CPU_GS464E, | |
| + ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT | |
| + | ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264, | |
| + mips_hwr_names_numeric }, | |
| + | |
| + { "g264e", 1, bfd_mach_mips_gs464e, CPU_GS264E, | |
| + ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT | |
| + | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, mips_cp0_names_numeric, NULL, | |
| + 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, | |
| { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, | |
| ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0, | |
| @@ -928,6 +945,31 @@ parse_mips_ase_option (const char *option) | |
| return TRUE; | |
| } | |
| + if (CONST_STRNEQ (option, "loongson-mmi")) | |
| + { | |
| + mips_ase |= ASE_LOONGSON_MMI; | |
| + return TRUE; | |
| + } | |
| + | |
| + if (CONST_STRNEQ (option, "loongson-cam")) | |
| + { | |
| + mips_ase |= ASE_LOONGSON_CAM; | |
| + return TRUE; | |
| + } | |
| + | |
| + /* Put here for match ext2 frist */ | |
| + if (CONST_STRNEQ (option, "loongson-ext2")) | |
| + { | |
| + mips_ase |= ASE_LOONGSON_EXT2; | |
| + return TRUE; | |
| + } | |
| + | |
| + if (CONST_STRNEQ (option, "loongson-ext")) | |
| + { | |
| + mips_ase |= ASE_LOONGSON_EXT; | |
| + return TRUE; | |
| + } | |
| + | |
| return FALSE; | |
| } | |
| @@ -2594,6 +2636,21 @@ with the -M switch (multiple options should be separated by commas):\n")); | |
| specified architecture.\n")); | |
| fprintf (stream, _("\n\ | |
| + loongson-mmi Recognize the Loongson MultiMedia extensions\n\ | |
| + Instructions (MMI) ASE instructions.\n")); | |
| + | |
| + fprintf (stream, _("\n\ | |
| + loongson-cam Recognize the Loongson Content Address Memory (CAM)\n\ | |
| + instructions.\n")); | |
| + | |
| + fprintf (stream, _("\n\ | |
| + loongson-ext Recognize the Loongson EXTensions (EXT)\n\ | |
| + instructions.\n")); | |
| + | |
| + fprintf (stream, _("\n\ | |
| + loongson-ext2 Recognize the Loongson EXTensions R2 (EXT2)\n\ | |
| + instructions.\n")); | |
| + fprintf (stream, _("\n\ | |
| For the options above, the following values are supported for \"ABI\":\n\ | |
| ")); | |
| for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) | |
| diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c | |
| index 2f0c41d..4b891a1 100644 | |
| --- a/opcodes/mips-opc.c | |
| +++ b/opcodes/mips-opc.c | |
| @@ -307,7 +307,6 @@ decode_mips_operand (const char *p) | |
| #define IL2E (INSN_LOONGSON_2E) | |
| #define IL2F (INSN_LOONGSON_2F) | |
| -#define IL3A (INSN_LOONGSON_3A) | |
| #define P3 INSN_4650 | |
| #define L1 INSN_4010 | |
| @@ -406,6 +405,18 @@ decode_mips_operand (const char *p) | |
| #define XPA ASE_XPA | |
| #define XPAVZ ASE_XPA_VIRT | |
| +/* Loongson MultiMedia extensions Instructions (MMI) support. */ | |
| +#define LMMI ASE_LOONGSON_MMI | |
| + | |
| +/* Loongson Content Address Memory (CAM) support. */ | |
| +#define LCAM ASE_LOONGSON_CAM | |
| + | |
| +/* Loongson EXTensions (EXT) instructions support. */ | |
| +#define LEXT ASE_LOONGSON_EXT | |
| + | |
| +/* Loongson EXTensions R2 (EXT2) instructions support. */ | |
| +#define LEXT2 ASE_LOONGSON_EXT2 | |
| + | |
| /* The order of overloaded instructions matters. Label arguments and | |
| register arguments look the same. Instructions that can have either | |
| for arguments must apear in the correct order in this table for the | |
| @@ -447,63 +458,67 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 }, | |
| {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
| -/* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 | |
| +/* Loongson specific instructions. Loongson gs464 (aka loongson3a) redefines the Coprocessor 2 | |
| instructions. Put them here so that disassembler will find them first. | |
| The assemblers uses a hash table based on the instruction name anyhow. */ | |
| -{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, | |
| -{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, | |
| -{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| -{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, | |
| -{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, | |
| -{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, | |
| -{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gslwlec1", "T,b,d", 0xc800001c, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gslwgtc1", "T,b,d", 0xc800001d, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gsldlec1", "T,b,d", 0xc800001e, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gsldgtc1", "T,b,d", 0xc800001f, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 }, | |
| -{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, | |
| -{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, | |
| -{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, | |
| -{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, | |
| -{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, | |
| -{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
| -{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
| -{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
| -{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
| -{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, | |
| -{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, | |
| -{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
| -{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
| -{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, LMS, IL3A, 0, 0 }, | |
| -{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 }, | |
| -{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, LMS, IL3A, 0, 0 }, | |
| -{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 }, | |
| +{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, | |
| +{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, | |
| +{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 }, | |
| +{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, | |
| +{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 }, | |
| +{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 }, | |
| +{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, | |
| +{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, | |
| +{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, | |
| +{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, | |
| +{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, | |
| +{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, | |
| +{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, | |
| +{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, | |
| +{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, | |
| +{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, | |
| +{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, | |
| +{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, | |
| +{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, | |
| +{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, | |
| +{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, | |
| +{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 }, | |
| +{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, | |
| +{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 }, | |
| +{"cto", "d,s", 0x70000062, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, | |
| +{"ctz", "d,s", 0x70000022, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, | |
| +{"dcto", "d,s", 0x700000e2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, | |
| +{"dctz", "d,s", 0x700000a2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, | |
| /* R5900 VU0 Macromode instructions. */ | |
| {"vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
| @@ -646,7 +661,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, I37 }, | |
| {"add", "D,S,T", 0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, | |
| -{"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
| +{"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, | |
| {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, | |
| {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, | |
| {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| @@ -667,7 +682,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"addu", "D,S,T", 0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, | |
| -{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
| +{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, | |
| {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
| {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
| @@ -677,7 +692,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"and", "D,S,T", 0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"and", "D,S,T", 0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"and", "D,S,T", 0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
| {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
| @@ -995,7 +1010,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
| {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, I69 }, | |
| {"dadd", "D,S,T", 0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, I69 }, | |
| {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, | |
| {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
| @@ -1135,25 +1150,25 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsll32 */ | |
| {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
| {"dsll", "D,S,T", 0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
| {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
| {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrav */ | |
| {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsra32 */ | |
| {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
| {"dsra", "D,S,T", 0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
| {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
| {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrlv */ | |
| {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */ | |
| {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
| {"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
| {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, I69 }, | |
| {"dsub", "D,S,T", 0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
| {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, | |
| {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | |
| @@ -1430,7 +1445,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, | |
| {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, | |
| {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, | |
| -{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F|IL3A, 0, 0 }, | |
| +{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F, LEXT, 0 }, | |
| {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, | |
| {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, | |
| {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| @@ -1622,7 +1637,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"nor", "D,S,T", 0x47a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| {"nor.ob", "D,S,Q", 0x4800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
| {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
| @@ -1630,7 +1645,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"or", "D,S,T", 0x45a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"or", "D,S,T", 0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"or", "D,S,T", 0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| {"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
| {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
| @@ -1843,7 +1858,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"seq", "S,T", 0x46a00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
| -{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, | |
| {"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, | |
| {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| @@ -1873,29 +1888,29 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
| -{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, | |
| {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
| -{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, | |
| {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* sllv */ | |
| {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, | |
| {"sll", "D,S,T", 0x45800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| {"sll.ob", "D,S,Q", 0x48000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
| {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
| {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
| -{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, | |
| {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
| {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
| {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
| -{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, | |
| {"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, | |
| {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| @@ -1911,13 +1926,13 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srav */ | |
| {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, | |
| {"sra", "D,S,T", 0x45c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
| {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srlv */ | |
| {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, | |
| {"srl", "D,S,T", 0x45800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| {"srl.ob", "D,S,Q", 0x48000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
| {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
| @@ -1926,7 +1941,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, I37 }, | |
| {"sub", "D,S,T", 0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, | |
| -{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
| +{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, | |
| {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, | |
| {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, | |
| {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| @@ -1942,7 +1957,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"subu", "D,S,T", 0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, | |
| -{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
| +{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, | |
| {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 }, | |
| {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, | |
| {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, | |
| @@ -2063,7 +2078,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
| {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| {"xor", "D,S,T", 0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"xor", "D,S,T", 0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"xor", "D,S,T", 0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
| {"xor.ob", "D,S,Q", 0x4800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
| {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
| @@ -2429,174 +2444,174 @@ const struct mips_opcode mips_builtin_opcodes[] = | |
| /* ST Microelectronics Loongson-2E and -2F. */ | |
| {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
| {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
| -{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
| +{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, | |
| {"packsshb", "D,S,T", 0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"packsswh", "D,S,T", 0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"packushb", "D,S,T", 0x47600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"paddb", "D,S,T", 0x47c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"paddb", "d,s,t", 0x70000208, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"paddh", "D,S,T", 0x47400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| {"paddh", "d,s,t", 0x70000108, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| -{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"paddw", "D,S,T", 0x47600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"paddw", "d,s,t", 0x70000008, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"paddd", "D,S,T", 0x47e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"paddsb", "D,S,T", 0x47800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"paddsb", "d,s,t", 0x70000608, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"paddsh", "D,S,T", 0x47000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"paddsh", "d,s,t", 0x70000508, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"paddush", "D,S,T", 0x47200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pandn", "D,S,T", 0x47e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pavgb", "D,S,T", 0x46600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pavgh", "D,S,T", 0x46400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pminub", "D,S,T", 0x46e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pmovmskb", "D,S", 0x46a00005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, LMMI, 0 }, | |
| {"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pmullh", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"biadd", "D,S", 0x46800005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, | |
| -{"biadd", "D,S", 0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"biadd", "D,S", 0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, LMMI, 0 }, | |
| {"pshufh", "D,S,T", 0x47000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psllh", "D,S,T", 0x46600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
| {"psllw", "D,S,T", 0x46400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
| {"psrah", "D,S,T", 0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
| {"psraw", "D,S,T", 0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
| {"psrlh", "D,S,T", 0x46600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
| {"psrlw", "D,S,T", 0x46400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
| {"psubb", "D,S,T", 0x47c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psubb", "d,s,t", 0x70000248, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"psubh", "D,S,T", 0x47400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psubh", "d,s,t", 0x70000148, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"psubw", "D,S,T", 0x47600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psubw", "d,s,t", 0x70000048, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"psubd", "D,S,T", 0x47e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psubsb", "D,S,T", 0x47800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psubsb", "d,s,t", 0x70000648, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"psubsh", "D,S,T", 0x47000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psubsh", "d,s,t", 0x70000548, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
| {"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"psubush", "D,S,T", 0x47200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
| -{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, | |
| {"sequ", "S,T", 0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
| -{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
| +{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, | |
| /* MIPS Enhanced VA Scheme */ | |
| {"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, | |
| {"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment