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probe-rs Sequence that logs everything
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| //! Example sequences that log things | |
| #[derive(Debug)] | |
| struct DefaultArmDebugSequence; | |
| impl probe_rs::architecture::arm::sequences::ArmDebugSequence for DefaultArmDebugSequence {} | |
| /// Example of an ARM debug sequence | |
| #[derive(Debug)] | |
| pub struct ExampleSequence; | |
| impl ExampleSequence { | |
| /// Create the sequencer for most ARMv7 STM32 families. | |
| pub fn create() -> std::sync::Arc<Self> { | |
| std::sync::Arc::new(Self) | |
| } | |
| } | |
| impl probe_rs::architecture::arm::sequences::ArmDebugSequence for ExampleSequence { | |
| fn debug_port_setup( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::DapProbe, | |
| dp: probe_rs::architecture::arm::dp::DpAddress, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!( | |
| "debug_port_setup(interface: {}, {dp:x?})", | |
| interface.get_name() | |
| ); | |
| DefaultArmDebugSequence | |
| .debug_port_setup(interface, dp) | |
| .inspect_err(|e| tracing::error!("Unable to setup debug port: {e}")) | |
| } | |
| fn reset_system( | |
| &self, | |
| core: &mut dyn probe_rs::architecture::arm::memory::ArmMemoryInterface, | |
| core_type: probe_rs::CoreType, | |
| debug_base: Option<u64>, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("reset_system(interface, {core_type:?}, {debug_base:x?})"); | |
| DefaultArmDebugSequence | |
| .reset_system(core, core_type, debug_base) | |
| .inspect_err(|e| tracing::error!("Unable to reset system: {e}")) | |
| } | |
| fn allowed_access_ports(&self) -> Vec<u8> { | |
| tracing::trace!("allowed_access_ports()"); | |
| DefaultArmDebugSequence.allowed_access_ports() | |
| } | |
| fn debug_port_connect( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::DapProbe, | |
| dp: probe_rs::architecture::arm::dp::DpAddress, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!( | |
| "debug_port_connect(interface: {}, {dp:x?})", | |
| interface.get_name() | |
| ); | |
| DefaultArmDebugSequence.debug_port_connect(interface, dp) | |
| } | |
| fn debug_port_start( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::DapAccess, | |
| dp: probe_rs::architecture::arm::dp::DpAddress, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("debug_port_start(interface, {dp:x?})"); | |
| DefaultArmDebugSequence | |
| .debug_port_start(interface, dp) | |
| .inspect_err(|e| tracing::error!("Unable to start debug port: {e}")) | |
| } | |
| fn debug_core_start( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::ArmDebugInterface, | |
| core_ap: &probe_rs::architecture::arm::FullyQualifiedApAddress, | |
| core_type: probe_rs::CoreType, | |
| debug_base: Option<u64>, | |
| cti_base: Option<u64>, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!( | |
| "debug_core_start(interface, {core_ap:x?}, {core_type:?}, {debug_base:08x?}, {cti_base:08x?})" | |
| ); | |
| DefaultArmDebugSequence | |
| .debug_core_start(interface, core_ap, core_type, debug_base, cti_base) | |
| .inspect_err(|e| tracing::error!("Unable to start debug core: {e}")) | |
| } | |
| fn debug_core_stop( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::memory::ArmMemoryInterface, | |
| core_type: probe_rs::CoreType, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("debug_core_stop(interface, {core_type:?})"); | |
| DefaultArmDebugSequence.debug_core_stop(interface, core_type) | |
| } | |
| fn debug_device_unlock( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::ArmDebugInterface, | |
| default_ap: &probe_rs::architecture::arm::FullyQualifiedApAddress, | |
| permissions: &probe_rs::Permissions, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("debug_device_unlock(interface, {default_ap:?}, {permissions:?})"); | |
| DefaultArmDebugSequence.debug_device_unlock(interface, default_ap, permissions) | |
| } | |
| fn debug_erase_sequence( | |
| &self, | |
| ) -> Option<Arc<dyn probe_rs::architecture::arm::sequences::DebugEraseSequence>> { | |
| tracing::trace!("debug_erase_sequence()"); | |
| DefaultArmDebugSequence.debug_erase_sequence() | |
| } | |
| fn debug_port_stop( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::DapProbe, | |
| dp: probe_rs::architecture::arm::dp::DpAddress, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!( | |
| "debug_port_stop(interface: {}, {dp:x?})", | |
| interface.get_name() | |
| ); | |
| DefaultArmDebugSequence.debug_port_stop(interface, dp) | |
| } | |
| fn prepare_running_on_ram( | |
| &self, | |
| vector_table_addr: u64, | |
| session: &mut probe_rs::Session, | |
| ) -> Result<(), probe_rs::Error> { | |
| tracing::trace!("prepare_running_on_ram({vector_table_addr:08x}, session)"); | |
| DefaultArmDebugSequence.prepare_running_on_ram(vector_table_addr, session) | |
| } | |
| fn recover_support_start( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::memory::ArmMemoryInterface, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("recover_support_start(interface)"); | |
| DefaultArmDebugSequence.recover_support_start(interface) | |
| } | |
| fn reset_catch_set( | |
| &self, | |
| core: &mut dyn probe_rs::architecture::arm::memory::ArmMemoryInterface, | |
| core_type: probe_rs::CoreType, | |
| debug_base: Option<u64>, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("reset_catch_set(core, {core_type:?}, {debug_base:08x?})"); | |
| DefaultArmDebugSequence.reset_catch_set(core, core_type, debug_base) | |
| } | |
| fn reset_hardware_assert( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::DapProbe, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("reset_hardware_assert(interface: {})", interface.get_name()); | |
| DefaultArmDebugSequence.reset_hardware_assert(interface) | |
| } | |
| fn reset_hardware_deassert( | |
| &self, | |
| probe: &mut dyn probe_rs::architecture::arm::ArmDebugInterface, | |
| default_ap: &probe_rs::architecture::arm::FullyQualifiedApAddress, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("reset_hardware_deassert(probe, {default_ap:x?})"); | |
| DefaultArmDebugSequence.reset_hardware_deassert(probe, default_ap) | |
| } | |
| fn trace_start( | |
| &self, | |
| interface: &mut dyn probe_rs::architecture::arm::ArmDebugInterface, | |
| components: &[probe_rs::architecture::arm::memory::CoresightComponent], | |
| sink: &probe_rs::architecture::arm::component::TraceSink, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("trace_start()"); | |
| DefaultArmDebugSequence.trace_start(interface, components, sink) | |
| } | |
| fn reset_catch_clear( | |
| &self, | |
| core: &mut dyn probe_rs::architecture::arm::memory::ArmMemoryInterface, | |
| core_type: probe_rs::CoreType, | |
| debug_base: Option<u64>, | |
| ) -> Result<(), probe_rs::architecture::arm::ArmError> { | |
| tracing::trace!("reset_catch_clear(core, {core_type:?}, {debug_base:08x?})"); | |
| DefaultArmDebugSequence.reset_catch_clear(core, core_type, debug_base) | |
| } | |
| } |
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