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CH32V003 TIM1 ISR Debug
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| #include "ch32v003fun.h" | |
| #include <stdio.h> | |
| // LEDs on A1 and A2 (to GND) | |
| #define LED_PORT GPIOA | |
| #define LED_PIN1 1 | |
| #define LED_PIN2 2 | |
| volatile unsigned int TIM1_UP_IRQHandler_INTFR = 0; | |
| volatile unsigned int TIM1_CC_IRQHandler_INTFR = 0; | |
| volatile unsigned int TIM1_TRG_COM_IRQHandler_INTFR = 0; | |
| volatile unsigned int TIM1_BRK_IRQHandler_INTFR = 0; | |
| void debugTimestamp() { | |
| printf("%03d.%03d: ", SysTick->CNT/48000000, SysTick->CNT/48000 % 1000); | |
| } | |
| void TIM1_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); | |
| void TIM1_UP_IRQHandler(void) { | |
| TIM1_UP_IRQHandler_INTFR = TIM1->INTFR; | |
| TIM1->INTFR = 0; | |
| } | |
| void TIM1_TRG_COM_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); | |
| void TIM1_TRG_COM_IRQHandler(void) { | |
| TIM1_TRG_COM_IRQHandler_INTFR = TIM1->INTFR; | |
| TIM1->INTFR = 0; | |
| } | |
| void TIM1_CC_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); | |
| void TIM1_CC_IRQHandler(void) { | |
| TIM1_CC_IRQHandler_INTFR = TIM1->INTFR; | |
| TIM1->INTFR = 0; | |
| } | |
| void TIM1_BRK_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); | |
| void TIM1_BRK_IRQHandler(void) { | |
| TIM1_BRK_IRQHandler_INTFR = TIM1->INTFR; | |
| TIM1->INTFR = 0; | |
| } | |
| int main() | |
| { | |
| SystemInit(); | |
| RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | RCC_APB2Periph_TIM1 | RCC_APB2Periph_AFIO; | |
| LED_PORT->CFGLR &= ~(0xf<<(4*LED_PIN1)); | |
| LED_PORT->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP)<<(4*LED_PIN1); | |
| LED_PORT->CFGLR &= ~(0xf<<(4*LED_PIN2)); | |
| LED_PORT->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP)<<(4*LED_PIN2); | |
| Delay_Ms(5000); | |
| LED_PORT->BSHR = 1<<(LED_PIN1+0); // Set LED_PIN HIGH | |
| LED_PORT->BSHR = 1<<(LED_PIN2+0); // Set LED_PIN HIGH | |
| Delay_Ms(100); | |
| debugTimestamp(); printf("### Debug Ready ###\r\n"); | |
| // Reset TIM1 to init all regs | |
| RCC->APB2PRSTR |= RCC_APB2Periph_TIM1; | |
| RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1; | |
| TIM1->PSC = 48000-1; // 1kHz | |
| TIM1->ATRLR = 2000-1; // | |
| TIM1->CH1CVR = 300; | |
| TIM1->CH2CVR = 900; | |
| TIM1->CH3CVR = 0xFFFFFFFF; | |
| TIM1->CH4CVR = 0xFFFFFFFF; | |
| // Timer CNT resets to 0 regardless of TIM_ARPE set or not | |
| TIM1->CTLR1 |= TIM_OPM; // | TIM_ARPE; // One-Pulse-Mode + Auto-Reload | |
| //TIM1->DMAINTENR |= TIM_UIE | TIM_TIE | TIM_BIE | TIM_COMIE; | |
| //TIM1->DMAINTENR |= TIM_UIE | TIM_TIE | TIM_BIE | TIM_COMIE | TIM_CC1IE | TIM_CC2IE | TIM_CC3IE; | |
| TIM1->DMAINTENR |= TIM_CC1IE | TIM_CC2IE | TIM_CC3IE; | |
| TIM1->SWEVGR |= TIM_UG; // REQUIRED to set the PSC correctly!!! | |
| //TIM1->INTFR &= ~TIM_UIF; // Clears the Interrupt Flag set by TIM_UG before so it won't fire immediately! | |
| TIM1->CTLR1 |= TIM_CEN; | |
| debugTimestamp(); printf("TIM1->CNT: %4d; TIM1->INTFR: %02x; CTLR1: %04x; SWEVGR: %04x; DMAINTENR: %04x\r\n", | |
| TIM1->CNT, TIM1->INTFR, TIM1->CTLR1, TIM1->SWEVGR, TIM1->DMAINTENR); | |
| NVIC_EnableIRQ(TIM1_UP_IRQn); | |
| NVIC_EnableIRQ(TIM1_TRG_COM_IRQn); | |
| NVIC_EnableIRQ(TIM1_BRK_IRQn); | |
| NVIC_EnableIRQ(TIM1_CC_IRQn); | |
| unsigned long lastTick = 0; | |
| while(1) { | |
| if(SysTick->CNT - lastTick > 48e3*200) { | |
| lastTick = SysTick->CNT; | |
| debugTimestamp(); printf("TIM1->CNT: %4d; TIM1->INTFR: %02x\r\n", TIM1->CNT, TIM1->INTFR); | |
| } | |
| if(TIM1_UP_IRQHandler_INTFR) { | |
| debugTimestamp(); printf("TIM1->CNT: %4d; TIM1->INTFR: %02x (TIM1_UP_IRQ)\r\n", TIM1->CNT, TIM1_UP_IRQHandler_INTFR); | |
| TIM1_UP_IRQHandler_INTFR = 0; | |
| } | |
| if(TIM1_CC_IRQHandler_INTFR) { | |
| debugTimestamp(); printf("TIM1->CNT: %4d; TIM1->INTFR: %02x (TIM1_CC_IRQ)\r\n", TIM1->CNT, TIM1_CC_IRQHandler_INTFR); | |
| TIM1_CC_IRQHandler_INTFR = 0; | |
| } | |
| if(TIM1_BRK_IRQHandler_INTFR) { | |
| debugTimestamp(); printf("TIM1->CNT: %4d; TIM1->INTFR: %02x (TIM1_BRK_IRQ)\r\n", TIM1->CNT, TIM1_BRK_IRQHandler_INTFR); | |
| TIM1_BRK_IRQHandler_INTFR = 0; | |
| } | |
| if(TIM1_TRG_COM_IRQHandler_INTFR) { | |
| debugTimestamp(); printf("TIM1->CNT: %4d; TIM1->INTFR: %02x (TIM1_TRG_COM_IRQ)\r\n", TIM1->CNT, TIM1_TRG_COM_IRQHandler_INTFR); | |
| TIM1_TRG_COM_IRQHandler_INTFR = 0; | |
| } | |
| } | |
| } | |
| /* | |
| > minichlink.exe -bT | |
| Found WCH Link | |
| WCH Programmer is LinkE version 2.10 | |
| Chip Type: 003 | |
| Part Type (A): 0x0010 (This is the capacity code, in KB) | |
| Part UUID : 44-4b-ab-cd-ac-5b-bc-43 | |
| PFlags : ff-ff-ff-ff | |
| Part Type (B): 00-33-05-00 | |
| Interface Setup | |
| 059.456: ### Debug Ready ### | |
| 059.460: TIM1->CNT: 2; TIM1->INTFR: 01; CTLR1: 0009; SWEVGR: 0000; DMAINTENR: 000e <- TIM_CC1IE | TIM_CC2IE | TIM_CC3IE | |
| 059.489: TIM1->CNT: 31; TIM1->INTFR: 01 | |
| 059.689: TIM1->CNT: 230; TIM1->INTFR: 01 | |
| 059.760: TIM1->CNT: 301; TIM1->INTFR: 00 (TIM1_UP_IRQ) <- Why UP ISR? And Why no Flag set? | |
| 059.779: TIM1->CNT: 320; TIM1->INTFR: 03 (TIM1_CC_IRQ) <- CH1 triggered, okay! (and UP Flag is set?) | |
| 059.889: TIM1->CNT: 431; TIM1->INTFR: 00 | |
| 060.089: TIM1->CNT: 631; TIM1->INTFR: 00 | |
| 060.289: TIM1->CNT: 831; TIM1->INTFR: 00 | |
| 060.360: TIM1->CNT: 901; TIM1->INTFR: 04 (TIM1_CC_IRQ) <- CH2 triggered, okay! | |
| 060.489: TIM1->CNT: 1030; TIM1->INTFR: 00 | |
| 060.689: TIM1->CNT: 1230; TIM1->INTFR: 00 | |
| 060.889: TIM1->CNT: 1430; TIM1->INTFR: 00 | |
| 061.089: TIM1->CNT: 1631; TIM1->INTFR: 00 | |
| 061.289: TIM1->CNT: 1831; TIM1->INTFR: 00 | |
| 061.460: TIM1->CNT: 0; TIM1->INTFR: 19 (TIM1_CC_IRQ) <- Why have CH3+CH4 triggered? And why is this not an UP ISR? | |
| 061.489: TIM1->CNT: 0; TIM1->INTFR: 00 | |
| 061.689: TIM1->CNT: 0; TIM1->INTFR: 00 | |
| ... | |
| > minichlink.exe -bT | |
| Found WCH Link | |
| WCH Programmer is LinkE version 2.10 | |
| Chip Type: 003 | |
| Part Type (A): 0x0010 (This is the capacity code, in KB) | |
| Part UUID : 44-4b-ab-cd-ac-5b-bc-43 | |
| PFlags : ff-ff-ff-ff | |
| Part Type (B): 00-33-05-00 | |
| Interface Setup | |
| 010.772: ### Debug Ready ### | |
| 010.776: TIM1->CNT: 2; TIM1->INTFR: 01; CTLR1: 0009; SWEVGR: 0000; DMAINTENR: 000e | |
| 010.805: TIM1->CNT: 31; TIM1->INTFR: 01 | |
| 011.005: TIM1->CNT: 231; TIM1->INTFR: 01 | |
| 011.076: TIM1->CNT: 302; TIM1->INTFR: 03 (TIM1_CC_IRQ) <- CH1 triggered, okay! (and UP Flag is set?) | |
| 011.205: TIM1->CNT: 430; TIM1->INTFR: 00 | |
| 011.405: TIM1->CNT: 631; TIM1->INTFR: 00 | |
| 011.605: TIM1->CNT: 830; TIM1->INTFR: 00 | |
| 011.676: TIM1->CNT: 901; TIM1->INTFR: 04 (TIM1_CC_IRQ) <- CH2 triggered, okay! | |
| 011.805: TIM1->CNT: 1030; TIM1->INTFR: 00 | |
| 012.005: TIM1->CNT: 1230; TIM1->INTFR: 00 | |
| 012.205: TIM1->CNT: 1431; TIM1->INTFR: 00 | |
| 012.405: TIM1->CNT: 1630; TIM1->INTFR: 00 | |
| 012.605: TIM1->CNT: 1830; TIM1->INTFR: 00 <- It just froze at this point?! | |
| ^C | |
| > minichlink.exe -bT | |
| Found WCH Link | |
| WCH Programmer is LinkE version 2.10 | |
| Chip Type: 003 | |
| Part Type (A): 0x0010 (This is the capacity code, in KB) | |
| Part UUID : 44-4b-ab-cd-ac-5b-bc-43 | |
| PFlags : ff-ff-ff-ff | |
| Part Type (B): 00-33-05-00 | |
| Interface Setup | |
| 035.788: ### Debug Ready ### | |
| 035.792: TIM1->CNT: 1; TIM1->INTFR: 01; CTLR1: 0009; SWEVGR: 0000; DMAINTENR: 000e | |
| 035.828: TIM1->CNT: 38; TIM1->INTFR: 01 | |
| 036.028: TIM1->CNT: 237; TIM1->INTFR: 01 | |
| 036.092: TIM1->CNT: 301; TIM1->INTFR: 03 (TIM1_CC_IRQ) <- CH1 triggered, okay! (and UP Flag is set?) | |
| 036.228: TIM1->CNT: 439; TIM1->INTFR: 00 | |
| 036.428: TIM1->CNT: 637; TIM1->INTFR: 00 | |
| 036.628: TIM1->CNT: 837; TIM1->INTFR: 00 | |
| 036.692: TIM1->CNT: 902; TIM1->INTFR: 04 (TIM1_CC_IRQ) <- CH2 triggered, okay! | |
| 036.828: TIM1->CNT: 1037; TIM1->INTFR: 00 | |
| 037.028: TIM1->CNT: 1239; TIM1->INTFR: 00 | |
| 037.228: TIM1->CNT: 1437; TIM1->INTFR: 00 | |
| 037.428: TIM1->CNT: 1637; TIM1->INTFR: 00 | |
| 037.628: TIM1->CNT: 1838; TIM1->INTFR: 00 | |
| 037.792: TIM1->CNT: 0; TIM1->INTFR: 19 <- Why have CH3+CH4 triggered? And why is this not an UP ISR? | |
| 037.828: TIM1->CNT: 0; TIM1->INTFR: 00 | |
| 038.028: TIM1->CNT: 0; TIM1->INTFR: 00 | |
| ... | |
| > minichlink.exe -bT | |
| Found WCH Link | |
| WCH Programmer is LinkE version 2.10 | |
| Chip Type: 003 | |
| Part Type (A): 0x0010 (This is the capacity code, in KB) | |
| Part UUID : 44-4b-ab-cd-ac-5b-bc-43 | |
| PFlags : ff-ff-ff-ff | |
| Part Type (B): 00-33-05-00 | |
| Interface Setup | |
| 088.973: ### Debug Ready ### | |
| 088.977: TIM1->CNT: 1; TIM1->INTFR: 01; CTLR1: 0009; SWEVGR: 0000; DMAINTENR: 000e | |
| 089.004: TIM1->CNT: 29; TIM1->INTFR: 01 | |
| 089.204: TIM1->CNT: 228; TIM1->INTFR: 01 | |
| 089.277: TIM1->CNT: 301; TIM1->INTFR: 03 (TIM1_CC_IRQ) <- CH1 triggered, okay! (and UP Flag is set?) | |
| 089.404: TIM1->CNT: 428; TIM1->INTFR: 00 | |
| 000.126: TIM1->CNT: 628; TIM1->INTFR: 00 | |
| 000.326: TIM1->CNT: 828; TIM1->INTFR: 00 | |
| 000.398: TIM1->CNT: 901; TIM1->INTFR: 00 (TIM1_TRG_COM_IRQ) <- Why COM? TIM_COMIE is not set! | |
| 000.419: TIM1->CNT: 922; TIM1->INTFR: 04 (TIM1_CC_IRQ) <- CH2 triggered, but late! | |
| 000.526: TIM1->CNT: 1029; TIM1->INTFR: 00 | |
| 000.726: TIM1->CNT: 1229; TIM1->INTFR: 00 | |
| 000.926: TIM1->CNT: 1429; TIM1->INTFR: 00 | |
| 001.126: TIM1->CNT: 1628; TIM1->INTFR: 00 | |
| 001.326: TIM1->CNT: 1828; TIM1->INTFR: 00 <- It just froze at this point?! | |
| ^C | |
| >minichlink.exe -bT | |
| Found WCH Link | |
| WCH Programmer is LinkE version 2.10 | |
| Chip Type: 003 | |
| Part Type (A): 0x0010 (This is the capacity code, in KB) | |
| Part UUID : 44-4b-ab-cd-ac-5b-bc-43 | |
| PFlags : ff-ff-ff-ff | |
| Part Type (B): 00-33-05-00 | |
| Interface Setup | |
| 073.563: ### Debug Ready ### | |
| 073.567: TIM1->CNT: 1; TIM1->INTFR: 01; CTLR1: 0009; SWEVGR: 0000; DMAINTENR: 000e | |
| 073.597: TIM1->CNT: 32; TIM1->INTFR: 01 | |
| 073.797: TIM1->CNT: 232; TIM1->INTFR: 01 <- It just froze at this point?! CC ISR should have been called next ... | |
| ^C | |
| */ |
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Using
__attribute__((interrupt()))instead of__attribute__((interrupt("WCH-Interrupt-fast")))solves the issues ...